1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 * 16 * Portions of this code based on: 17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 18 * for Linux kernel 2.4.x. 19 * 20 * Written 2002 ShuChen <shuchen@realtek.com.tw> 21 * See Linux Driver for full information 22 * 23 * Linux Driver Version 1.27a, 10.02.2002 24 * 25 * Thanks to: 26 * Jean Chen of RealTek Semiconductor Corp. for 27 * providing the evaluation NIC used to develop 28 * this driver. RealTek's support for Etherboot 29 * is appreciated. 30 * 31 * REVISION HISTORY: 32 * ================ 33 * 34 * v1.0 11-26-2003 timlegge Initial port of Linux driver 35 * v1.5 01-17-2004 timlegge Initial driver output cleanup 36 * 37 * Indent Options: indent -kr -i8 38 ***************************************************************************/ 39 /* 40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 41 * Modified to use le32_to_cpu and cpu_to_le32 properly 42 */ 43 #include <common.h> 44 #include <malloc.h> 45 #include <net.h> 46 #include <netdev.h> 47 #include <asm/io.h> 48 #include <pci.h> 49 50 #undef DEBUG_RTL8169 51 #undef DEBUG_RTL8169_TX 52 #undef DEBUG_RTL8169_RX 53 54 #define drv_version "v1.5" 55 #define drv_date "01-17-2004" 56 57 static u32 ioaddr; 58 59 /* Condensed operations for readability. */ 60 #define currticks() get_timer(0) 61 62 /* media options */ 63 #define MAX_UNITS 8 64 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 65 66 /* MAC address length*/ 67 #define MAC_ADDR_LEN 6 68 69 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 70 #define MAX_ETH_FRAME_SIZE 1536 71 72 #define TX_FIFO_THRESH 256 /* In bytes */ 73 74 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 75 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 76 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 77 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 78 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 79 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 80 81 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 82 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 83 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 84 #define RX_BUF_LEN 8192 85 86 #define RTL_MIN_IO_SIZE 0x80 87 #define TX_TIMEOUT (6*HZ) 88 89 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 90 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 91 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 92 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 93 #define RTL_R8(reg) readb (ioaddr + (reg)) 94 #define RTL_R16(reg) readw (ioaddr + (reg)) 95 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 96 97 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 98 #define ETH_ALEN MAC_ADDR_LEN 99 #define ETH_ZLEN 60 100 101 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, (pci_addr_t)a) 102 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, (phys_addr_t)a) 103 104 enum RTL8169_registers { 105 MAC0 = 0, /* Ethernet hardware address. */ 106 MAR0 = 8, /* Multicast filter. */ 107 TxDescStartAddrLow = 0x20, 108 TxDescStartAddrHigh = 0x24, 109 TxHDescStartAddrLow = 0x28, 110 TxHDescStartAddrHigh = 0x2c, 111 FLASH = 0x30, 112 ERSR = 0x36, 113 ChipCmd = 0x37, 114 TxPoll = 0x38, 115 IntrMask = 0x3C, 116 IntrStatus = 0x3E, 117 TxConfig = 0x40, 118 RxConfig = 0x44, 119 RxMissed = 0x4C, 120 Cfg9346 = 0x50, 121 Config0 = 0x51, 122 Config1 = 0x52, 123 Config2 = 0x53, 124 Config3 = 0x54, 125 Config4 = 0x55, 126 Config5 = 0x56, 127 MultiIntr = 0x5C, 128 PHYAR = 0x60, 129 TBICSR = 0x64, 130 TBI_ANAR = 0x68, 131 TBI_LPAR = 0x6A, 132 PHYstatus = 0x6C, 133 RxMaxSize = 0xDA, 134 CPlusCmd = 0xE0, 135 RxDescStartAddrLow = 0xE4, 136 RxDescStartAddrHigh = 0xE8, 137 EarlyTxThres = 0xEC, 138 FuncEvent = 0xF0, 139 FuncEventMask = 0xF4, 140 FuncPresetState = 0xF8, 141 FuncForceEvent = 0xFC, 142 }; 143 144 enum RTL8169_register_content { 145 /*InterruptStatusBits */ 146 SYSErr = 0x8000, 147 PCSTimeout = 0x4000, 148 SWInt = 0x0100, 149 TxDescUnavail = 0x80, 150 RxFIFOOver = 0x40, 151 RxUnderrun = 0x20, 152 RxOverflow = 0x10, 153 TxErr = 0x08, 154 TxOK = 0x04, 155 RxErr = 0x02, 156 RxOK = 0x01, 157 158 /*RxStatusDesc */ 159 RxRES = 0x00200000, 160 RxCRC = 0x00080000, 161 RxRUNT = 0x00100000, 162 RxRWT = 0x00400000, 163 164 /*ChipCmdBits */ 165 CmdReset = 0x10, 166 CmdRxEnb = 0x08, 167 CmdTxEnb = 0x04, 168 RxBufEmpty = 0x01, 169 170 /*Cfg9346Bits */ 171 Cfg9346_Lock = 0x00, 172 Cfg9346_Unlock = 0xC0, 173 174 /*rx_mode_bits */ 175 AcceptErr = 0x20, 176 AcceptRunt = 0x10, 177 AcceptBroadcast = 0x08, 178 AcceptMulticast = 0x04, 179 AcceptMyPhys = 0x02, 180 AcceptAllPhys = 0x01, 181 182 /*RxConfigBits */ 183 RxCfgFIFOShift = 13, 184 RxCfgDMAShift = 8, 185 186 /*TxConfigBits */ 187 TxInterFrameGapShift = 24, 188 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 189 190 /*rtl8169_PHYstatus */ 191 TBI_Enable = 0x80, 192 TxFlowCtrl = 0x40, 193 RxFlowCtrl = 0x20, 194 _1000bpsF = 0x10, 195 _100bps = 0x08, 196 _10bps = 0x04, 197 LinkStatus = 0x02, 198 FullDup = 0x01, 199 200 /*GIGABIT_PHY_registers */ 201 PHY_CTRL_REG = 0, 202 PHY_STAT_REG = 1, 203 PHY_AUTO_NEGO_REG = 4, 204 PHY_1000_CTRL_REG = 9, 205 206 /*GIGABIT_PHY_REG_BIT */ 207 PHY_Restart_Auto_Nego = 0x0200, 208 PHY_Enable_Auto_Nego = 0x1000, 209 210 /* PHY_STAT_REG = 1; */ 211 PHY_Auto_Nego_Comp = 0x0020, 212 213 /* PHY_AUTO_NEGO_REG = 4; */ 214 PHY_Cap_10_Half = 0x0020, 215 PHY_Cap_10_Full = 0x0040, 216 PHY_Cap_100_Half = 0x0080, 217 PHY_Cap_100_Full = 0x0100, 218 219 /* PHY_1000_CTRL_REG = 9; */ 220 PHY_Cap_1000_Full = 0x0200, 221 222 PHY_Cap_Null = 0x0, 223 224 /*_MediaType*/ 225 _10_Half = 0x01, 226 _10_Full = 0x02, 227 _100_Half = 0x04, 228 _100_Full = 0x08, 229 _1000_Full = 0x10, 230 231 /*_TBICSRBit*/ 232 TBILinkOK = 0x02000000, 233 }; 234 235 static struct { 236 const char *name; 237 u8 version; /* depend on RTL8169 docs */ 238 u32 RxConfigMask; /* should clear the bits supported by this chip */ 239 } rtl_chip_info[] = { 240 {"RTL-8169", 0x00, 0xff7e1880,}, 241 {"RTL-8169", 0x04, 0xff7e1880,}, 242 {"RTL-8169", 0x00, 0xff7e1880,}, 243 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 244 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 245 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 246 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 247 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 248 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 249 {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, 250 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, 251 {"RTL-8101e", 0x34, 0xff7e1880,}, 252 {"RTL-8100e", 0x32, 0xff7e1880,}, 253 }; 254 255 enum _DescStatusBit { 256 OWNbit = 0x80000000, 257 EORbit = 0x40000000, 258 FSbit = 0x20000000, 259 LSbit = 0x10000000, 260 }; 261 262 struct TxDesc { 263 u32 status; 264 u32 vlan_tag; 265 u32 buf_addr; 266 u32 buf_Haddr; 267 }; 268 269 struct RxDesc { 270 u32 status; 271 u32 vlan_tag; 272 u32 buf_addr; 273 u32 buf_Haddr; 274 }; 275 276 /* Define the TX Descriptor */ 277 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; 278 /* __attribute__ ((aligned(256))); */ 279 280 /* Create a static buffer of size RX_BUF_SZ for each 281 TX Descriptor. All descriptors point to a 282 part of this buffer */ 283 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; 284 285 /* Define the RX Descriptor */ 286 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; 287 /* __attribute__ ((aligned(256))); */ 288 289 /* Create a static buffer of size RX_BUF_SZ for each 290 RX Descriptor All descriptors point to a 291 part of this buffer */ 292 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; 293 294 struct rtl8169_private { 295 void *mmio_addr; /* memory map physical address */ 296 int chipset; 297 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 298 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 299 unsigned long dirty_tx; 300 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ 301 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ 302 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 303 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 304 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 305 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 306 unsigned char *Tx_skbuff[NUM_TX_DESC]; 307 } tpx; 308 309 static struct rtl8169_private *tpc; 310 311 static const u16 rtl8169_intr_mask = 312 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 313 TxOK | RxErr | RxOK; 314 static const unsigned int rtl8169_rx_config = 315 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 316 317 static struct pci_device_id supported[] = { 318 {PCI_VENDOR_ID_REALTEK, 0x8167}, 319 {PCI_VENDOR_ID_REALTEK, 0x8168}, 320 {PCI_VENDOR_ID_REALTEK, 0x8169}, 321 {} 322 }; 323 324 void mdio_write(int RegAddr, int value) 325 { 326 int i; 327 328 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 329 udelay(1000); 330 331 for (i = 2000; i > 0; i--) { 332 /* Check if the RTL8169 has completed writing to the specified MII register */ 333 if (!(RTL_R32(PHYAR) & 0x80000000)) { 334 break; 335 } else { 336 udelay(100); 337 } 338 } 339 } 340 341 int mdio_read(int RegAddr) 342 { 343 int i, value = -1; 344 345 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 346 udelay(1000); 347 348 for (i = 2000; i > 0; i--) { 349 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 350 if (RTL_R32(PHYAR) & 0x80000000) { 351 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 352 break; 353 } else { 354 udelay(100); 355 } 356 } 357 return value; 358 } 359 360 static int rtl8169_init_board(struct eth_device *dev) 361 { 362 int i; 363 u32 tmp; 364 365 #ifdef DEBUG_RTL8169 366 printf ("%s\n", __FUNCTION__); 367 #endif 368 ioaddr = dev->iobase; 369 370 /* Soft reset the chip. */ 371 RTL_W8(ChipCmd, CmdReset); 372 373 /* Check that the chip has finished the reset. */ 374 for (i = 1000; i > 0; i--) 375 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 376 break; 377 else 378 udelay(10); 379 380 /* identify chip attached to board */ 381 tmp = RTL_R32(TxConfig); 382 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 383 384 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 385 if (tmp == rtl_chip_info[i].version) { 386 tpc->chipset = i; 387 goto match; 388 } 389 } 390 391 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 392 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 393 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 394 tpc->chipset = 0; 395 396 match: 397 return 0; 398 } 399 400 /* 401 * Cache maintenance functions. These are simple wrappers around the more 402 * general purpose flush_cache() and invalidate_dcache_range() functions. 403 */ 404 405 static void rtl_inval_rx_desc(struct RxDesc *desc) 406 { 407 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 408 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 409 410 invalidate_dcache_range(start, end); 411 } 412 413 static void rtl_flush_rx_desc(struct RxDesc *desc) 414 { 415 flush_cache((unsigned long)desc, sizeof(*desc)); 416 } 417 418 static void rtl_inval_tx_desc(struct TxDesc *desc) 419 { 420 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 421 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 422 423 invalidate_dcache_range(start, end); 424 } 425 426 static void rtl_flush_tx_desc(struct TxDesc *desc) 427 { 428 flush_cache((unsigned long)desc, sizeof(*desc)); 429 } 430 431 static void rtl_inval_buffer(void *buf, size_t size) 432 { 433 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 434 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 435 436 invalidate_dcache_range(start, end); 437 } 438 439 static void rtl_flush_buffer(void *buf, size_t size) 440 { 441 flush_cache((unsigned long)buf, size); 442 } 443 444 /************************************************************************** 445 RECV - Receive a frame 446 ***************************************************************************/ 447 static int rtl_recv(struct eth_device *dev) 448 { 449 /* return true if there's an ethernet packet ready to read */ 450 /* nic->packet should contain data on return */ 451 /* nic->packetlen should contain length of data */ 452 int cur_rx; 453 int length = 0; 454 455 #ifdef DEBUG_RTL8169_RX 456 printf ("%s\n", __FUNCTION__); 457 #endif 458 ioaddr = dev->iobase; 459 460 cur_rx = tpc->cur_rx; 461 462 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); 463 464 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 465 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 466 unsigned char rxdata[RX_BUF_LEN]; 467 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 468 status) & 0x00001FFF) - 4; 469 470 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); 471 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 472 473 if (cur_rx == NUM_RX_DESC - 1) 474 tpc->RxDescArray[cur_rx].status = 475 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 476 else 477 tpc->RxDescArray[cur_rx].status = 478 cpu_to_le32(OWNbit + RX_BUF_SIZE); 479 tpc->RxDescArray[cur_rx].buf_addr = 480 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx])); 481 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); 482 483 NetReceive(rxdata, length); 484 } else { 485 puts("Error Rx"); 486 } 487 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 488 tpc->cur_rx = cur_rx; 489 return 1; 490 491 } else { 492 ushort sts = RTL_R8(IntrStatus); 493 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 494 udelay(100); /* wait */ 495 } 496 tpc->cur_rx = cur_rx; 497 return (0); /* initially as this is called to flush the input */ 498 } 499 500 #define HZ 1000 501 /************************************************************************** 502 SEND - Transmit a frame 503 ***************************************************************************/ 504 static int rtl_send(struct eth_device *dev, void *packet, int length) 505 { 506 /* send the packet to destination */ 507 508 u32 to; 509 u8 *ptxb; 510 int entry = tpc->cur_tx % NUM_TX_DESC; 511 u32 len = length; 512 int ret; 513 514 #ifdef DEBUG_RTL8169_TX 515 int stime = currticks(); 516 printf ("%s\n", __FUNCTION__); 517 printf("sending %d bytes\n", len); 518 #endif 519 520 ioaddr = dev->iobase; 521 522 /* point to the current txb incase multiple tx_rings are used */ 523 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 524 memcpy(ptxb, (char *)packet, (int)length); 525 rtl_flush_buffer(ptxb, length); 526 527 while (len < ETH_ZLEN) 528 ptxb[len++] = '\0'; 529 530 tpc->TxDescArray[entry].buf_Haddr = 0; 531 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb)); 532 if (entry != (NUM_TX_DESC - 1)) { 533 tpc->TxDescArray[entry].status = 534 cpu_to_le32((OWNbit | FSbit | LSbit) | 535 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 536 } else { 537 tpc->TxDescArray[entry].status = 538 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 539 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 540 } 541 rtl_flush_tx_desc(&tpc->TxDescArray[entry]); 542 RTL_W8(TxPoll, 0x40); /* set polling bit */ 543 544 tpc->cur_tx++; 545 to = currticks() + TX_TIMEOUT; 546 do { 547 rtl_inval_tx_desc(&tpc->TxDescArray[entry]); 548 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 549 && (currticks() < to)); /* wait */ 550 551 if (currticks() >= to) { 552 #ifdef DEBUG_RTL8169_TX 553 puts("tx timeout/error\n"); 554 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 555 #endif 556 ret = 0; 557 } else { 558 #ifdef DEBUG_RTL8169_TX 559 puts("tx done\n"); 560 #endif 561 ret = length; 562 } 563 /* Delay to make net console (nc) work properly */ 564 udelay(20); 565 return ret; 566 } 567 568 static void rtl8169_set_rx_mode(struct eth_device *dev) 569 { 570 u32 mc_filter[2]; /* Multicast hash filter */ 571 int rx_mode; 572 u32 tmp = 0; 573 574 #ifdef DEBUG_RTL8169 575 printf ("%s\n", __FUNCTION__); 576 #endif 577 578 /* IFF_ALLMULTI */ 579 /* Too many to filter perfectly -- accept all multicasts. */ 580 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 581 mc_filter[1] = mc_filter[0] = 0xffffffff; 582 583 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 584 rtl_chip_info[tpc->chipset].RxConfigMask); 585 586 RTL_W32(RxConfig, tmp); 587 RTL_W32(MAR0 + 0, mc_filter[0]); 588 RTL_W32(MAR0 + 4, mc_filter[1]); 589 } 590 591 static void rtl8169_hw_start(struct eth_device *dev) 592 { 593 u32 i; 594 595 #ifdef DEBUG_RTL8169 596 int stime = currticks(); 597 printf ("%s\n", __FUNCTION__); 598 #endif 599 600 #if 0 601 /* Soft reset the chip. */ 602 RTL_W8(ChipCmd, CmdReset); 603 604 /* Check that the chip has finished the reset. */ 605 for (i = 1000; i > 0; i--) { 606 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 607 break; 608 else 609 udelay(10); 610 } 611 #endif 612 613 RTL_W8(Cfg9346, Cfg9346_Unlock); 614 615 /* RTL-8169sb/8110sb or previous version */ 616 if (tpc->chipset <= 5) 617 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 618 619 RTL_W8(EarlyTxThres, EarlyTxThld); 620 621 /* For gigabit rtl8169 */ 622 RTL_W16(RxMaxSize, RxPacketMaxSize); 623 624 /* Set Rx Config register */ 625 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 626 rtl_chip_info[tpc->chipset].RxConfigMask); 627 RTL_W32(RxConfig, i); 628 629 /* Set DMA burst size and Interframe Gap Time */ 630 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 631 (InterFrameGap << TxInterFrameGapShift)); 632 633 634 tpc->cur_rx = 0; 635 636 RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray)); 637 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 638 RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray)); 639 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 640 641 /* RTL-8169sc/8110sc or later version */ 642 if (tpc->chipset > 5) 643 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 644 645 RTL_W8(Cfg9346, Cfg9346_Lock); 646 udelay(10); 647 648 RTL_W32(RxMissed, 0); 649 650 rtl8169_set_rx_mode(dev); 651 652 /* no early-rx interrupts */ 653 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 654 655 #ifdef DEBUG_RTL8169 656 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 657 #endif 658 } 659 660 static void rtl8169_init_ring(struct eth_device *dev) 661 { 662 int i; 663 664 #ifdef DEBUG_RTL8169 665 int stime = currticks(); 666 printf ("%s\n", __FUNCTION__); 667 #endif 668 669 tpc->cur_rx = 0; 670 tpc->cur_tx = 0; 671 tpc->dirty_tx = 0; 672 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 673 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 674 675 for (i = 0; i < NUM_TX_DESC; i++) { 676 tpc->Tx_skbuff[i] = &txb[i]; 677 } 678 679 for (i = 0; i < NUM_RX_DESC; i++) { 680 if (i == (NUM_RX_DESC - 1)) 681 tpc->RxDescArray[i].status = 682 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 683 else 684 tpc->RxDescArray[i].status = 685 cpu_to_le32(OWNbit + RX_BUF_SIZE); 686 687 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 688 tpc->RxDescArray[i].buf_addr = 689 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i])); 690 rtl_flush_rx_desc(&tpc->RxDescArray[i]); 691 } 692 693 #ifdef DEBUG_RTL8169 694 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 695 #endif 696 } 697 698 /************************************************************************** 699 RESET - Finish setting up the ethernet interface 700 ***************************************************************************/ 701 static int rtl_reset(struct eth_device *dev, bd_t *bis) 702 { 703 int i; 704 705 #ifdef DEBUG_RTL8169 706 int stime = currticks(); 707 printf ("%s\n", __FUNCTION__); 708 #endif 709 710 tpc->TxDescArrays = tx_ring; 711 /* Tx Desscriptor needs 256 bytes alignment; */ 712 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays + 713 255) & ~255); 714 715 tpc->RxDescArrays = rx_ring; 716 /* Rx Desscriptor needs 256 bytes alignment; */ 717 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays + 718 255) & ~255); 719 720 rtl8169_init_ring(dev); 721 rtl8169_hw_start(dev); 722 /* Construct a perfect filter frame with the mac address as first match 723 * and broadcast for all others */ 724 for (i = 0; i < 192; i++) 725 txb[i] = 0xFF; 726 727 txb[0] = dev->enetaddr[0]; 728 txb[1] = dev->enetaddr[1]; 729 txb[2] = dev->enetaddr[2]; 730 txb[3] = dev->enetaddr[3]; 731 txb[4] = dev->enetaddr[4]; 732 txb[5] = dev->enetaddr[5]; 733 734 #ifdef DEBUG_RTL8169 735 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 736 #endif 737 return 0; 738 } 739 740 /************************************************************************** 741 HALT - Turn off ethernet interface 742 ***************************************************************************/ 743 static void rtl_halt(struct eth_device *dev) 744 { 745 int i; 746 747 #ifdef DEBUG_RTL8169 748 printf ("%s\n", __FUNCTION__); 749 #endif 750 751 ioaddr = dev->iobase; 752 753 /* Stop the chip's Tx and Rx DMA processes. */ 754 RTL_W8(ChipCmd, 0x00); 755 756 /* Disable interrupts by clearing the interrupt mask. */ 757 RTL_W16(IntrMask, 0x0000); 758 759 RTL_W32(RxMissed, 0); 760 761 tpc->TxDescArrays = NULL; 762 tpc->RxDescArrays = NULL; 763 tpc->TxDescArray = NULL; 764 tpc->RxDescArray = NULL; 765 for (i = 0; i < NUM_RX_DESC; i++) { 766 tpc->RxBufferRing[i] = NULL; 767 } 768 } 769 770 /************************************************************************** 771 INIT - Look for an adapter, this routine's visible to the outside 772 ***************************************************************************/ 773 774 #define board_found 1 775 #define valid_link 0 776 static int rtl_init(struct eth_device *dev, bd_t *bis) 777 { 778 static int board_idx = -1; 779 int i, rc; 780 int option = -1, Cap10_100 = 0, Cap1000 = 0; 781 782 #ifdef DEBUG_RTL8169 783 printf ("%s\n", __FUNCTION__); 784 #endif 785 786 ioaddr = dev->iobase; 787 788 board_idx++; 789 790 /* point to private storage */ 791 tpc = &tpx; 792 793 rc = rtl8169_init_board(dev); 794 if (rc) 795 return rc; 796 797 /* Get MAC address. FIXME: read EEPROM */ 798 for (i = 0; i < MAC_ADDR_LEN; i++) 799 dev->enetaddr[i] = RTL_R8(MAC0 + i); 800 801 #ifdef DEBUG_RTL8169 802 printf("chipset = %d\n", tpc->chipset); 803 printf("MAC Address"); 804 for (i = 0; i < MAC_ADDR_LEN; i++) 805 printf(":%02x", dev->enetaddr[i]); 806 putc('\n'); 807 #endif 808 809 #ifdef DEBUG_RTL8169 810 /* Print out some hardware info */ 811 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); 812 #endif 813 814 /* if TBI is not endbled */ 815 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 816 int val = mdio_read(PHY_AUTO_NEGO_REG); 817 818 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 819 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 820 if (option > 0) { 821 #ifdef DEBUG_RTL8169 822 printf("%s: Force-mode Enabled.\n", dev->name); 823 #endif 824 Cap10_100 = 0, Cap1000 = 0; 825 switch (option) { 826 case _10_Half: 827 Cap10_100 = PHY_Cap_10_Half; 828 Cap1000 = PHY_Cap_Null; 829 break; 830 case _10_Full: 831 Cap10_100 = PHY_Cap_10_Full; 832 Cap1000 = PHY_Cap_Null; 833 break; 834 case _100_Half: 835 Cap10_100 = PHY_Cap_100_Half; 836 Cap1000 = PHY_Cap_Null; 837 break; 838 case _100_Full: 839 Cap10_100 = PHY_Cap_100_Full; 840 Cap1000 = PHY_Cap_Null; 841 break; 842 case _1000_Full: 843 Cap10_100 = PHY_Cap_Null; 844 Cap1000 = PHY_Cap_1000_Full; 845 break; 846 default: 847 break; 848 } 849 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 850 mdio_write(PHY_1000_CTRL_REG, Cap1000); 851 } else { 852 #ifdef DEBUG_RTL8169 853 printf("%s: Auto-negotiation Enabled.\n", 854 dev->name); 855 #endif 856 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 857 mdio_write(PHY_AUTO_NEGO_REG, 858 PHY_Cap_10_Half | PHY_Cap_10_Full | 859 PHY_Cap_100_Half | PHY_Cap_100_Full | 860 (val & 0x1F)); 861 862 /* enable 1000 Full Mode */ 863 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 864 865 } 866 867 /* Enable auto-negotiation and restart auto-nigotiation */ 868 mdio_write(PHY_CTRL_REG, 869 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 870 udelay(100); 871 872 /* wait for auto-negotiation process */ 873 for (i = 10000; i > 0; i--) { 874 /* check if auto-negotiation complete */ 875 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 876 udelay(100); 877 option = RTL_R8(PHYstatus); 878 if (option & _1000bpsF) { 879 #ifdef DEBUG_RTL8169 880 printf("%s: 1000Mbps Full-duplex operation.\n", 881 dev->name); 882 #endif 883 } else { 884 #ifdef DEBUG_RTL8169 885 printf("%s: %sMbps %s-duplex operation.\n", 886 dev->name, 887 (option & _100bps) ? "100" : 888 "10", 889 (option & FullDup) ? "Full" : 890 "Half"); 891 #endif 892 } 893 break; 894 } else { 895 udelay(100); 896 } 897 } /* end for-loop to wait for auto-negotiation process */ 898 899 } else { 900 udelay(100); 901 #ifdef DEBUG_RTL8169 902 printf 903 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 904 dev->name, 905 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 906 #endif 907 } 908 909 return 1; 910 } 911 912 int rtl8169_initialize(bd_t *bis) 913 { 914 pci_dev_t devno; 915 int card_number = 0; 916 struct eth_device *dev; 917 u32 iobase; 918 int idx=0; 919 920 while(1){ 921 unsigned int region; 922 u16 device; 923 924 /* Find RTL8169 */ 925 if ((devno = pci_find_devices(supported, idx++)) < 0) 926 break; 927 928 pci_read_config_word(devno, PCI_DEVICE_ID, &device); 929 switch (device) { 930 case 0x8168: 931 region = 2; 932 break; 933 934 default: 935 region = 1; 936 break; 937 } 938 939 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); 940 iobase &= ~0xf; 941 942 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 943 944 dev = (struct eth_device *)malloc(sizeof *dev); 945 if (!dev) { 946 printf("Can not allocate memory of rtl8169\n"); 947 break; 948 } 949 950 memset(dev, 0, sizeof(*dev)); 951 sprintf (dev->name, "RTL8169#%d", card_number); 952 953 dev->priv = (void *) devno; 954 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 955 956 dev->init = rtl_reset; 957 dev->halt = rtl_halt; 958 dev->send = rtl_send; 959 dev->recv = rtl_recv; 960 961 eth_register (dev); 962 963 rtl_init(dev, bis); 964 965 card_number++; 966 } 967 return card_number; 968 } 969