1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 * 16 * Portions of this code based on: 17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 18 * for Linux kernel 2.4.x. 19 * 20 * Written 2002 ShuChen <shuchen@realtek.com.tw> 21 * See Linux Driver for full information 22 * 23 * Linux Driver Version 1.27a, 10.02.2002 24 * 25 * Thanks to: 26 * Jean Chen of RealTek Semiconductor Corp. for 27 * providing the evaluation NIC used to develop 28 * this driver. RealTek's support for Etherboot 29 * is appreciated. 30 * 31 * REVISION HISTORY: 32 * ================ 33 * 34 * v1.0 11-26-2003 timlegge Initial port of Linux driver 35 * v1.5 01-17-2004 timlegge Initial driver output cleanup 36 * 37 * Indent Options: indent -kr -i8 38 ***************************************************************************/ 39 /* 40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 41 * Modified to use le32_to_cpu and cpu_to_le32 properly 42 */ 43 #include <common.h> 44 #include <dm.h> 45 #include <errno.h> 46 #include <malloc.h> 47 #include <net.h> 48 #ifndef CONFIG_DM_ETH 49 #include <netdev.h> 50 #endif 51 #include <asm/io.h> 52 #include <pci.h> 53 54 #undef DEBUG_RTL8169 55 #undef DEBUG_RTL8169_TX 56 #undef DEBUG_RTL8169_RX 57 58 #define drv_version "v1.5" 59 #define drv_date "01-17-2004" 60 61 static unsigned long ioaddr; 62 63 /* Condensed operations for readability. */ 64 #define currticks() get_timer(0) 65 66 /* media options */ 67 #define MAX_UNITS 8 68 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 69 70 /* MAC address length*/ 71 #define MAC_ADDR_LEN 6 72 73 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 74 #define MAX_ETH_FRAME_SIZE 1536 75 76 #define TX_FIFO_THRESH 256 /* In bytes */ 77 78 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 79 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 80 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 81 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 82 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 83 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 84 85 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 86 #ifdef CONFIG_SYS_RX_ETH_BUFFER 87 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER 88 #else 89 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 90 #endif 91 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 92 #define RX_BUF_LEN 8192 93 94 #define RTL_MIN_IO_SIZE 0x80 95 #define TX_TIMEOUT (6*HZ) 96 97 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 98 #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg)) 99 #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg)) 100 #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg)) 101 #define RTL_R8(reg) readb(ioaddr + (reg)) 102 #define RTL_R16(reg) readw(ioaddr + (reg)) 103 #define RTL_R32(reg) readl(ioaddr + (reg)) 104 105 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 106 #define ETH_ALEN MAC_ADDR_LEN 107 #define ETH_ZLEN 60 108 109 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \ 110 (pci_addr_t)(unsigned long)a) 111 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \ 112 (phys_addr_t)a) 113 114 enum RTL8169_registers { 115 MAC0 = 0, /* Ethernet hardware address. */ 116 MAR0 = 8, /* Multicast filter. */ 117 TxDescStartAddrLow = 0x20, 118 TxDescStartAddrHigh = 0x24, 119 TxHDescStartAddrLow = 0x28, 120 TxHDescStartAddrHigh = 0x2c, 121 FLASH = 0x30, 122 ERSR = 0x36, 123 ChipCmd = 0x37, 124 TxPoll = 0x38, 125 IntrMask = 0x3C, 126 IntrStatus = 0x3E, 127 TxConfig = 0x40, 128 RxConfig = 0x44, 129 RxMissed = 0x4C, 130 Cfg9346 = 0x50, 131 Config0 = 0x51, 132 Config1 = 0x52, 133 Config2 = 0x53, 134 Config3 = 0x54, 135 Config4 = 0x55, 136 Config5 = 0x56, 137 MultiIntr = 0x5C, 138 PHYAR = 0x60, 139 TBICSR = 0x64, 140 TBI_ANAR = 0x68, 141 TBI_LPAR = 0x6A, 142 PHYstatus = 0x6C, 143 RxMaxSize = 0xDA, 144 CPlusCmd = 0xE0, 145 RxDescStartAddrLow = 0xE4, 146 RxDescStartAddrHigh = 0xE8, 147 EarlyTxThres = 0xEC, 148 FuncEvent = 0xF0, 149 FuncEventMask = 0xF4, 150 FuncPresetState = 0xF8, 151 FuncForceEvent = 0xFC, 152 }; 153 154 enum RTL8169_register_content { 155 /*InterruptStatusBits */ 156 SYSErr = 0x8000, 157 PCSTimeout = 0x4000, 158 SWInt = 0x0100, 159 TxDescUnavail = 0x80, 160 RxFIFOOver = 0x40, 161 RxUnderrun = 0x20, 162 RxOverflow = 0x10, 163 TxErr = 0x08, 164 TxOK = 0x04, 165 RxErr = 0x02, 166 RxOK = 0x01, 167 168 /*RxStatusDesc */ 169 RxRES = 0x00200000, 170 RxCRC = 0x00080000, 171 RxRUNT = 0x00100000, 172 RxRWT = 0x00400000, 173 174 /*ChipCmdBits */ 175 CmdReset = 0x10, 176 CmdRxEnb = 0x08, 177 CmdTxEnb = 0x04, 178 RxBufEmpty = 0x01, 179 180 /*Cfg9346Bits */ 181 Cfg9346_Lock = 0x00, 182 Cfg9346_Unlock = 0xC0, 183 184 /*rx_mode_bits */ 185 AcceptErr = 0x20, 186 AcceptRunt = 0x10, 187 AcceptBroadcast = 0x08, 188 AcceptMulticast = 0x04, 189 AcceptMyPhys = 0x02, 190 AcceptAllPhys = 0x01, 191 192 /*RxConfigBits */ 193 RxCfgFIFOShift = 13, 194 RxCfgDMAShift = 8, 195 196 /*TxConfigBits */ 197 TxInterFrameGapShift = 24, 198 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 199 200 /*rtl8169_PHYstatus */ 201 TBI_Enable = 0x80, 202 TxFlowCtrl = 0x40, 203 RxFlowCtrl = 0x20, 204 _1000bpsF = 0x10, 205 _100bps = 0x08, 206 _10bps = 0x04, 207 LinkStatus = 0x02, 208 FullDup = 0x01, 209 210 /*GIGABIT_PHY_registers */ 211 PHY_CTRL_REG = 0, 212 PHY_STAT_REG = 1, 213 PHY_AUTO_NEGO_REG = 4, 214 PHY_1000_CTRL_REG = 9, 215 216 /*GIGABIT_PHY_REG_BIT */ 217 PHY_Restart_Auto_Nego = 0x0200, 218 PHY_Enable_Auto_Nego = 0x1000, 219 220 /* PHY_STAT_REG = 1; */ 221 PHY_Auto_Nego_Comp = 0x0020, 222 223 /* PHY_AUTO_NEGO_REG = 4; */ 224 PHY_Cap_10_Half = 0x0020, 225 PHY_Cap_10_Full = 0x0040, 226 PHY_Cap_100_Half = 0x0080, 227 PHY_Cap_100_Full = 0x0100, 228 229 /* PHY_1000_CTRL_REG = 9; */ 230 PHY_Cap_1000_Full = 0x0200, 231 232 PHY_Cap_Null = 0x0, 233 234 /*_MediaType*/ 235 _10_Half = 0x01, 236 _10_Full = 0x02, 237 _100_Half = 0x04, 238 _100_Full = 0x08, 239 _1000_Full = 0x10, 240 241 /*_TBICSRBit*/ 242 TBILinkOK = 0x02000000, 243 }; 244 245 static struct { 246 const char *name; 247 u8 version; /* depend on RTL8169 docs */ 248 u32 RxConfigMask; /* should clear the bits supported by this chip */ 249 } rtl_chip_info[] = { 250 {"RTL-8169", 0x00, 0xff7e1880,}, 251 {"RTL-8169", 0x04, 0xff7e1880,}, 252 {"RTL-8169", 0x00, 0xff7e1880,}, 253 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 254 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 255 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 256 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 257 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 258 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 259 {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, 260 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, 261 {"RTL-8168/8111g", 0x4c, 0xff7e1880,}, 262 {"RTL-8101e", 0x34, 0xff7e1880,}, 263 {"RTL-8100e", 0x32, 0xff7e1880,}, 264 }; 265 266 enum _DescStatusBit { 267 OWNbit = 0x80000000, 268 EORbit = 0x40000000, 269 FSbit = 0x20000000, 270 LSbit = 0x10000000, 271 }; 272 273 struct TxDesc { 274 u32 status; 275 u32 vlan_tag; 276 u32 buf_addr; 277 u32 buf_Haddr; 278 }; 279 280 struct RxDesc { 281 u32 status; 282 u32 vlan_tag; 283 u32 buf_addr; 284 u32 buf_Haddr; 285 }; 286 287 static unsigned char rxdata[RX_BUF_LEN]; 288 289 #define RTL8169_DESC_SIZE 16 290 291 #if ARCH_DMA_MINALIGN > 256 292 # define RTL8169_ALIGN ARCH_DMA_MINALIGN 293 #else 294 # define RTL8169_ALIGN 256 295 #endif 296 297 /* 298 * Warn if the cache-line size is larger than the descriptor size. In such 299 * cases the driver will likely fail because the CPU needs to flush the cache 300 * when requeuing RX buffers, therefore descriptors written by the hardware 301 * may be discarded. 302 * 303 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause 304 * the driver to allocate descriptors from a pool of non-cached memory. 305 */ 306 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN 307 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \ 308 !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_X86) 309 #warning cache-line size is larger than descriptor size 310 #endif 311 #endif 312 313 /* 314 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All 315 * descriptors point to a part of this buffer. 316 */ 317 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 318 319 /* 320 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All 321 * descriptors point to a part of this buffer. 322 */ 323 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 324 325 struct rtl8169_private { 326 ulong iobase; 327 void *mmio_addr; /* memory map physical address */ 328 int chipset; 329 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 330 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 331 unsigned long dirty_tx; 332 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 333 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 334 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 335 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 336 unsigned char *Tx_skbuff[NUM_TX_DESC]; 337 } tpx; 338 339 static struct rtl8169_private *tpc; 340 341 static const u16 rtl8169_intr_mask = 342 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 343 TxOK | RxErr | RxOK; 344 static const unsigned int rtl8169_rx_config = 345 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 346 347 static struct pci_device_id supported[] = { 348 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) }, 349 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) }, 350 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) }, 351 {} 352 }; 353 354 void mdio_write(int RegAddr, int value) 355 { 356 int i; 357 358 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 359 udelay(1000); 360 361 for (i = 2000; i > 0; i--) { 362 /* Check if the RTL8169 has completed writing to the specified MII register */ 363 if (!(RTL_R32(PHYAR) & 0x80000000)) { 364 break; 365 } else { 366 udelay(100); 367 } 368 } 369 } 370 371 int mdio_read(int RegAddr) 372 { 373 int i, value = -1; 374 375 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 376 udelay(1000); 377 378 for (i = 2000; i > 0; i--) { 379 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 380 if (RTL_R32(PHYAR) & 0x80000000) { 381 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 382 break; 383 } else { 384 udelay(100); 385 } 386 } 387 return value; 388 } 389 390 static int rtl8169_init_board(unsigned long dev_iobase, const char *name) 391 { 392 int i; 393 u32 tmp; 394 395 #ifdef DEBUG_RTL8169 396 printf ("%s\n", __FUNCTION__); 397 #endif 398 ioaddr = dev_iobase; 399 400 /* Soft reset the chip. */ 401 RTL_W8(ChipCmd, CmdReset); 402 403 /* Check that the chip has finished the reset. */ 404 for (i = 1000; i > 0; i--) 405 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 406 break; 407 else 408 udelay(10); 409 410 /* identify chip attached to board */ 411 tmp = RTL_R32(TxConfig); 412 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 413 414 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 415 if (tmp == rtl_chip_info[i].version) { 416 tpc->chipset = i; 417 goto match; 418 } 419 } 420 421 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 422 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", 423 name); 424 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 425 tpc->chipset = 0; 426 427 match: 428 return 0; 429 } 430 431 /* 432 * TX and RX descriptors are 16 bytes. This causes problems with the cache 433 * maintenance on CPUs where the cache-line size exceeds the size of these 434 * descriptors. What will happen is that when the driver receives a packet 435 * it will be immediately requeued for the hardware to reuse. The CPU will 436 * therefore need to flush the cache-line containing the descriptor, which 437 * will cause all other descriptors in the same cache-line to be flushed 438 * along with it. If one of those descriptors had been written to by the 439 * device those changes (and the associated packet) will be lost. 440 * 441 * To work around this, we make use of non-cached memory if available. If 442 * descriptors are mapped uncached there's no need to manually flush them 443 * or invalidate them. 444 * 445 * Note that this only applies to descriptors. The packet data buffers do 446 * not have the same constraints since they are 1536 bytes large, so they 447 * are unlikely to share cache-lines. 448 */ 449 static void *rtl_alloc_descs(unsigned int num) 450 { 451 size_t size = num * RTL8169_DESC_SIZE; 452 453 #ifdef CONFIG_SYS_NONCACHED_MEMORY 454 return (void *)noncached_alloc(size, RTL8169_ALIGN); 455 #else 456 return memalign(RTL8169_ALIGN, size); 457 #endif 458 } 459 460 /* 461 * Cache maintenance functions. These are simple wrappers around the more 462 * general purpose flush_cache() and invalidate_dcache_range() functions. 463 */ 464 465 static void rtl_inval_rx_desc(struct RxDesc *desc) 466 { 467 #ifndef CONFIG_SYS_NONCACHED_MEMORY 468 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 469 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 470 471 invalidate_dcache_range(start, end); 472 #endif 473 } 474 475 static void rtl_flush_rx_desc(struct RxDesc *desc) 476 { 477 #ifndef CONFIG_SYS_NONCACHED_MEMORY 478 flush_cache((unsigned long)desc, sizeof(*desc)); 479 #endif 480 } 481 482 static void rtl_inval_tx_desc(struct TxDesc *desc) 483 { 484 #ifndef CONFIG_SYS_NONCACHED_MEMORY 485 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 486 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 487 488 invalidate_dcache_range(start, end); 489 #endif 490 } 491 492 static void rtl_flush_tx_desc(struct TxDesc *desc) 493 { 494 #ifndef CONFIG_SYS_NONCACHED_MEMORY 495 flush_cache((unsigned long)desc, sizeof(*desc)); 496 #endif 497 } 498 499 static void rtl_inval_buffer(void *buf, size_t size) 500 { 501 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 502 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 503 504 invalidate_dcache_range(start, end); 505 } 506 507 static void rtl_flush_buffer(void *buf, size_t size) 508 { 509 flush_cache((unsigned long)buf, size); 510 } 511 512 /************************************************************************** 513 RECV - Receive a frame 514 ***************************************************************************/ 515 static int rtl_recv_common(pci_dev_t bdf, unsigned long dev_iobase, 516 uchar **packetp) 517 { 518 /* return true if there's an ethernet packet ready to read */ 519 /* nic->packet should contain data on return */ 520 /* nic->packetlen should contain length of data */ 521 int cur_rx; 522 int length = 0; 523 524 #ifdef DEBUG_RTL8169_RX 525 printf ("%s\n", __FUNCTION__); 526 #endif 527 ioaddr = dev_iobase; 528 529 cur_rx = tpc->cur_rx; 530 531 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); 532 533 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 534 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 535 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 536 status) & 0x00001FFF) - 4; 537 538 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); 539 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 540 541 if (cur_rx == NUM_RX_DESC - 1) 542 tpc->RxDescArray[cur_rx].status = 543 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 544 else 545 tpc->RxDescArray[cur_rx].status = 546 cpu_to_le32(OWNbit + RX_BUF_SIZE); 547 tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32( 548 pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long) 549 tpc->RxBufferRing[cur_rx])); 550 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); 551 #ifdef CONFIG_DM_ETH 552 *packetp = rxdata; 553 #else 554 net_process_received_packet(rxdata, length); 555 #endif 556 } else { 557 puts("Error Rx"); 558 length = -EIO; 559 } 560 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 561 tpc->cur_rx = cur_rx; 562 return length; 563 564 } else { 565 ushort sts = RTL_R8(IntrStatus); 566 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 567 udelay(100); /* wait */ 568 } 569 tpc->cur_rx = cur_rx; 570 return (0); /* initially as this is called to flush the input */ 571 } 572 573 #ifdef CONFIG_DM_ETH 574 int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp) 575 { 576 struct rtl8169_private *priv = dev_get_priv(dev); 577 578 return rtl_recv_common(pci_get_bdf(dev), priv->iobase, packetp); 579 } 580 #else 581 static int rtl_recv(struct eth_device *dev) 582 { 583 return rtl_recv_common((pci_dev_t)dev->priv, dev->iobase, NULL); 584 } 585 #endif /* nCONFIG_DM_ETH */ 586 587 #define HZ 1000 588 /************************************************************************** 589 SEND - Transmit a frame 590 ***************************************************************************/ 591 static int rtl_send_common(pci_dev_t bdf, unsigned long dev_iobase, 592 void *packet, int length) 593 { 594 /* send the packet to destination */ 595 596 u32 to; 597 u8 *ptxb; 598 int entry = tpc->cur_tx % NUM_TX_DESC; 599 u32 len = length; 600 int ret; 601 602 #ifdef DEBUG_RTL8169_TX 603 int stime = currticks(); 604 printf ("%s\n", __FUNCTION__); 605 printf("sending %d bytes\n", len); 606 #endif 607 608 ioaddr = dev_iobase; 609 610 /* point to the current txb incase multiple tx_rings are used */ 611 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 612 memcpy(ptxb, (char *)packet, (int)length); 613 rtl_flush_buffer(ptxb, length); 614 615 while (len < ETH_ZLEN) 616 ptxb[len++] = '\0'; 617 618 tpc->TxDescArray[entry].buf_Haddr = 0; 619 tpc->TxDescArray[entry].buf_addr = cpu_to_le32( 620 pci_mem_to_phys(bdf, (pci_addr_t)(unsigned long)ptxb)); 621 if (entry != (NUM_TX_DESC - 1)) { 622 tpc->TxDescArray[entry].status = 623 cpu_to_le32((OWNbit | FSbit | LSbit) | 624 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 625 } else { 626 tpc->TxDescArray[entry].status = 627 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 628 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 629 } 630 rtl_flush_tx_desc(&tpc->TxDescArray[entry]); 631 RTL_W8(TxPoll, 0x40); /* set polling bit */ 632 633 tpc->cur_tx++; 634 to = currticks() + TX_TIMEOUT; 635 do { 636 rtl_inval_tx_desc(&tpc->TxDescArray[entry]); 637 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 638 && (currticks() < to)); /* wait */ 639 640 if (currticks() >= to) { 641 #ifdef DEBUG_RTL8169_TX 642 puts("tx timeout/error\n"); 643 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 644 #endif 645 ret = 0; 646 } else { 647 #ifdef DEBUG_RTL8169_TX 648 puts("tx done\n"); 649 #endif 650 ret = length; 651 } 652 /* Delay to make net console (nc) work properly */ 653 udelay(20); 654 return ret; 655 } 656 657 #ifdef CONFIG_DM_ETH 658 int rtl8169_eth_send(struct udevice *dev, void *packet, int length) 659 { 660 struct rtl8169_private *priv = dev_get_priv(dev); 661 662 return rtl_send_common(pci_get_bdf(dev), priv->iobase, packet, length); 663 } 664 665 #else 666 static int rtl_send(struct eth_device *dev, void *packet, int length) 667 { 668 return rtl_send_common((pci_dev_t)dev->priv, dev->iobase, packet, 669 length); 670 } 671 #endif 672 673 static void rtl8169_set_rx_mode(void) 674 { 675 u32 mc_filter[2]; /* Multicast hash filter */ 676 int rx_mode; 677 u32 tmp = 0; 678 679 #ifdef DEBUG_RTL8169 680 printf ("%s\n", __FUNCTION__); 681 #endif 682 683 /* IFF_ALLMULTI */ 684 /* Too many to filter perfectly -- accept all multicasts. */ 685 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 686 mc_filter[1] = mc_filter[0] = 0xffffffff; 687 688 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 689 rtl_chip_info[tpc->chipset].RxConfigMask); 690 691 RTL_W32(RxConfig, tmp); 692 RTL_W32(MAR0 + 0, mc_filter[0]); 693 RTL_W32(MAR0 + 4, mc_filter[1]); 694 } 695 696 static void rtl8169_hw_start(pci_dev_t bdf) 697 { 698 u32 i; 699 700 #ifdef DEBUG_RTL8169 701 int stime = currticks(); 702 printf ("%s\n", __FUNCTION__); 703 #endif 704 705 #if 0 706 /* Soft reset the chip. */ 707 RTL_W8(ChipCmd, CmdReset); 708 709 /* Check that the chip has finished the reset. */ 710 for (i = 1000; i > 0; i--) { 711 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 712 break; 713 else 714 udelay(10); 715 } 716 #endif 717 718 RTL_W8(Cfg9346, Cfg9346_Unlock); 719 720 /* RTL-8169sb/8110sb or previous version */ 721 if (tpc->chipset <= 5) 722 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 723 724 RTL_W8(EarlyTxThres, EarlyTxThld); 725 726 /* For gigabit rtl8169 */ 727 RTL_W16(RxMaxSize, RxPacketMaxSize); 728 729 /* Set Rx Config register */ 730 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 731 rtl_chip_info[tpc->chipset].RxConfigMask); 732 RTL_W32(RxConfig, i); 733 734 /* Set DMA burst size and Interframe Gap Time */ 735 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 736 (InterFrameGap << TxInterFrameGapShift)); 737 738 739 tpc->cur_rx = 0; 740 741 RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(bdf, 742 (pci_addr_t)(unsigned long)tpc->TxDescArray)); 743 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 744 RTL_W32(RxDescStartAddrLow, pci_mem_to_phys( 745 bdf, (pci_addr_t)(unsigned long)tpc->RxDescArray)); 746 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 747 748 /* RTL-8169sc/8110sc or later version */ 749 if (tpc->chipset > 5) 750 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 751 752 RTL_W8(Cfg9346, Cfg9346_Lock); 753 udelay(10); 754 755 RTL_W32(RxMissed, 0); 756 757 rtl8169_set_rx_mode(); 758 759 /* no early-rx interrupts */ 760 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 761 762 #ifdef DEBUG_RTL8169 763 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 764 #endif 765 } 766 767 static void rtl8169_init_ring(pci_dev_t bdf) 768 { 769 int i; 770 771 #ifdef DEBUG_RTL8169 772 int stime = currticks(); 773 printf ("%s\n", __FUNCTION__); 774 #endif 775 776 tpc->cur_rx = 0; 777 tpc->cur_tx = 0; 778 tpc->dirty_tx = 0; 779 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 780 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 781 782 for (i = 0; i < NUM_TX_DESC; i++) { 783 tpc->Tx_skbuff[i] = &txb[i]; 784 } 785 786 for (i = 0; i < NUM_RX_DESC; i++) { 787 if (i == (NUM_RX_DESC - 1)) 788 tpc->RxDescArray[i].status = 789 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 790 else 791 tpc->RxDescArray[i].status = 792 cpu_to_le32(OWNbit + RX_BUF_SIZE); 793 794 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 795 tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys( 796 bdf, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i])); 797 rtl_flush_rx_desc(&tpc->RxDescArray[i]); 798 } 799 800 #ifdef DEBUG_RTL8169 801 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 802 #endif 803 } 804 805 static void rtl8169_common_start(pci_dev_t bdf, unsigned char *enetaddr) 806 { 807 int i; 808 809 #ifdef DEBUG_RTL8169 810 int stime = currticks(); 811 printf ("%s\n", __FUNCTION__); 812 #endif 813 814 rtl8169_init_ring(bdf); 815 rtl8169_hw_start(bdf); 816 /* Construct a perfect filter frame with the mac address as first match 817 * and broadcast for all others */ 818 for (i = 0; i < 192; i++) 819 txb[i] = 0xFF; 820 821 txb[0] = enetaddr[0]; 822 txb[1] = enetaddr[1]; 823 txb[2] = enetaddr[2]; 824 txb[3] = enetaddr[3]; 825 txb[4] = enetaddr[4]; 826 txb[5] = enetaddr[5]; 827 828 #ifdef DEBUG_RTL8169 829 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 830 #endif 831 } 832 833 #ifdef CONFIG_DM_ETH 834 static int rtl8169_eth_start(struct udevice *dev) 835 { 836 struct eth_pdata *plat = dev_get_platdata(dev); 837 838 rtl8169_common_start(pci_get_bdf(dev), plat->enetaddr); 839 840 return 0; 841 } 842 #else 843 /************************************************************************** 844 RESET - Finish setting up the ethernet interface 845 ***************************************************************************/ 846 static int rtl_reset(struct eth_device *dev, bd_t *bis) 847 { 848 rtl8169_common_start((pci_dev_t)dev->priv, dev->enetaddr); 849 850 return 0; 851 } 852 #endif /* nCONFIG_DM_ETH */ 853 854 static void rtl_halt_common(unsigned long dev_iobase) 855 { 856 int i; 857 858 #ifdef DEBUG_RTL8169 859 printf ("%s\n", __FUNCTION__); 860 #endif 861 862 ioaddr = dev_iobase; 863 864 /* Stop the chip's Tx and Rx DMA processes. */ 865 RTL_W8(ChipCmd, 0x00); 866 867 /* Disable interrupts by clearing the interrupt mask. */ 868 RTL_W16(IntrMask, 0x0000); 869 870 RTL_W32(RxMissed, 0); 871 872 for (i = 0; i < NUM_RX_DESC; i++) { 873 tpc->RxBufferRing[i] = NULL; 874 } 875 } 876 877 #ifdef CONFIG_DM_ETH 878 void rtl8169_eth_stop(struct udevice *dev) 879 { 880 struct rtl8169_private *priv = dev_get_priv(dev); 881 882 rtl_halt_common(priv->iobase); 883 } 884 #else 885 /************************************************************************** 886 HALT - Turn off ethernet interface 887 ***************************************************************************/ 888 static void rtl_halt(struct eth_device *dev) 889 { 890 rtl_halt_common(dev->iobase); 891 } 892 #endif 893 894 /************************************************************************** 895 INIT - Look for an adapter, this routine's visible to the outside 896 ***************************************************************************/ 897 898 #define board_found 1 899 #define valid_link 0 900 static int rtl_init(unsigned long dev_ioaddr, const char *name, 901 unsigned char *enetaddr) 902 { 903 static int board_idx = -1; 904 int i, rc; 905 int option = -1, Cap10_100 = 0, Cap1000 = 0; 906 907 #ifdef DEBUG_RTL8169 908 printf ("%s\n", __FUNCTION__); 909 #endif 910 ioaddr = dev_ioaddr; 911 912 board_idx++; 913 914 /* point to private storage */ 915 tpc = &tpx; 916 917 rc = rtl8169_init_board(ioaddr, name); 918 if (rc) 919 return rc; 920 921 /* Get MAC address. FIXME: read EEPROM */ 922 for (i = 0; i < MAC_ADDR_LEN; i++) 923 enetaddr[i] = RTL_R8(MAC0 + i); 924 925 #ifdef DEBUG_RTL8169 926 printf("chipset = %d\n", tpc->chipset); 927 printf("MAC Address"); 928 for (i = 0; i < MAC_ADDR_LEN; i++) 929 printf(":%02x", enetaddr[i]); 930 putc('\n'); 931 #endif 932 933 #ifdef DEBUG_RTL8169 934 /* Print out some hardware info */ 935 printf("%s: at ioaddr 0x%lx\n", name, ioaddr); 936 #endif 937 938 /* if TBI is not endbled */ 939 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 940 int val = mdio_read(PHY_AUTO_NEGO_REG); 941 942 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 943 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 944 if (option > 0) { 945 #ifdef DEBUG_RTL8169 946 printf("%s: Force-mode Enabled.\n", dev->name); 947 #endif 948 Cap10_100 = 0, Cap1000 = 0; 949 switch (option) { 950 case _10_Half: 951 Cap10_100 = PHY_Cap_10_Half; 952 Cap1000 = PHY_Cap_Null; 953 break; 954 case _10_Full: 955 Cap10_100 = PHY_Cap_10_Full; 956 Cap1000 = PHY_Cap_Null; 957 break; 958 case _100_Half: 959 Cap10_100 = PHY_Cap_100_Half; 960 Cap1000 = PHY_Cap_Null; 961 break; 962 case _100_Full: 963 Cap10_100 = PHY_Cap_100_Full; 964 Cap1000 = PHY_Cap_Null; 965 break; 966 case _1000_Full: 967 Cap10_100 = PHY_Cap_Null; 968 Cap1000 = PHY_Cap_1000_Full; 969 break; 970 default: 971 break; 972 } 973 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 974 mdio_write(PHY_1000_CTRL_REG, Cap1000); 975 } else { 976 #ifdef DEBUG_RTL8169 977 printf("%s: Auto-negotiation Enabled.\n", 978 dev->name); 979 #endif 980 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 981 mdio_write(PHY_AUTO_NEGO_REG, 982 PHY_Cap_10_Half | PHY_Cap_10_Full | 983 PHY_Cap_100_Half | PHY_Cap_100_Full | 984 (val & 0x1F)); 985 986 /* enable 1000 Full Mode */ 987 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 988 989 } 990 991 /* Enable auto-negotiation and restart auto-nigotiation */ 992 mdio_write(PHY_CTRL_REG, 993 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 994 udelay(100); 995 996 /* wait for auto-negotiation process */ 997 for (i = 10000; i > 0; i--) { 998 /* check if auto-negotiation complete */ 999 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 1000 udelay(100); 1001 option = RTL_R8(PHYstatus); 1002 if (option & _1000bpsF) { 1003 #ifdef DEBUG_RTL8169 1004 printf("%s: 1000Mbps Full-duplex operation.\n", 1005 dev->name); 1006 #endif 1007 } else { 1008 #ifdef DEBUG_RTL8169 1009 printf("%s: %sMbps %s-duplex operation.\n", 1010 dev->name, 1011 (option & _100bps) ? "100" : 1012 "10", 1013 (option & FullDup) ? "Full" : 1014 "Half"); 1015 #endif 1016 } 1017 break; 1018 } else { 1019 udelay(100); 1020 } 1021 } /* end for-loop to wait for auto-negotiation process */ 1022 1023 } else { 1024 udelay(100); 1025 #ifdef DEBUG_RTL8169 1026 printf 1027 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 1028 dev->name, 1029 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 1030 #endif 1031 } 1032 1033 1034 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); 1035 if (!tpc->RxDescArray) 1036 return -ENOMEM; 1037 1038 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC); 1039 if (!tpc->TxDescArray) 1040 return -ENOMEM; 1041 1042 return 0; 1043 } 1044 1045 #ifndef CONFIG_DM_ETH 1046 int rtl8169_initialize(bd_t *bis) 1047 { 1048 pci_dev_t devno; 1049 int card_number = 0; 1050 struct eth_device *dev; 1051 u32 iobase; 1052 int idx=0; 1053 1054 while(1){ 1055 unsigned int region; 1056 u16 device; 1057 int err; 1058 1059 /* Find RTL8169 */ 1060 if ((devno = pci_find_devices(supported, idx++)) < 0) 1061 break; 1062 1063 pci_read_config_word(devno, PCI_DEVICE_ID, &device); 1064 switch (device) { 1065 case 0x8168: 1066 region = 2; 1067 break; 1068 1069 default: 1070 region = 1; 1071 break; 1072 } 1073 1074 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); 1075 iobase &= ~0xf; 1076 1077 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 1078 1079 dev = (struct eth_device *)malloc(sizeof *dev); 1080 if (!dev) { 1081 printf("Can not allocate memory of rtl8169\n"); 1082 break; 1083 } 1084 1085 memset(dev, 0, sizeof(*dev)); 1086 sprintf (dev->name, "RTL8169#%d", card_number); 1087 1088 dev->priv = (void *)(unsigned long)devno; 1089 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 1090 1091 dev->init = rtl_reset; 1092 dev->halt = rtl_halt; 1093 dev->send = rtl_send; 1094 dev->recv = rtl_recv; 1095 1096 err = rtl_init(dev->iobase, dev->name, dev->enetaddr); 1097 if (err < 0) { 1098 printf(pr_fmt("failed to initialize card: %d\n"), err); 1099 free(dev); 1100 continue; 1101 } 1102 1103 eth_register (dev); 1104 1105 card_number++; 1106 } 1107 return card_number; 1108 } 1109 #endif 1110 1111 #ifdef CONFIG_DM_ETH 1112 static int rtl8169_eth_probe(struct udevice *dev) 1113 { 1114 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev); 1115 struct rtl8169_private *priv = dev_get_priv(dev); 1116 struct eth_pdata *plat = dev_get_platdata(dev); 1117 u32 iobase; 1118 int region; 1119 int ret; 1120 1121 debug("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 1122 switch (pplat->device) { 1123 case 0x8168: 1124 region = 2; 1125 break; 1126 default: 1127 region = 1; 1128 break; 1129 } 1130 pci_read_config32(pci_get_bdf(dev), PCI_BASE_ADDRESS_0 + region * 4, 1131 &iobase); 1132 iobase &= ~0xf; 1133 priv->iobase = (int)pci_mem_to_phys(pci_get_bdf(dev), iobase); 1134 1135 ret = rtl_init(priv->iobase, dev->name, plat->enetaddr); 1136 if (ret < 0) { 1137 printf(pr_fmt("failed to initialize card: %d\n"), ret); 1138 return ret; 1139 } 1140 1141 return 0; 1142 } 1143 1144 static const struct eth_ops rtl8169_eth_ops = { 1145 .start = rtl8169_eth_start, 1146 .send = rtl8169_eth_send, 1147 .recv = rtl8169_eth_recv, 1148 .stop = rtl8169_eth_stop, 1149 }; 1150 1151 static const struct udevice_id rtl8169_eth_ids[] = { 1152 { .compatible = "realtek,rtl8169" }, 1153 { } 1154 }; 1155 1156 U_BOOT_DRIVER(eth_rtl8169) = { 1157 .name = "eth_rtl8169", 1158 .id = UCLASS_ETH, 1159 .of_match = rtl8169_eth_ids, 1160 .probe = rtl8169_eth_probe, 1161 .ops = &rtl8169_eth_ops, 1162 .priv_auto_alloc_size = sizeof(struct rtl8169_private), 1163 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1164 }; 1165 1166 U_BOOT_PCI_DEVICE(eth_rtl8169, supported); 1167 #endif 1168