1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 28 * Portions of this code based on: 29 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 30 * for Linux kernel 2.4.x. 31 * 32 * Written 2002 ShuChen <shuchen@realtek.com.tw> 33 * See Linux Driver for full information 34 * 35 * Linux Driver Version 1.27a, 10.02.2002 36 * 37 * Thanks to: 38 * Jean Chen of RealTek Semiconductor Corp. for 39 * providing the evaluation NIC used to develop 40 * this driver. RealTek's support for Etherboot 41 * is appreciated. 42 * 43 * REVISION HISTORY: 44 * ================ 45 * 46 * v1.0 11-26-2003 timlegge Initial port of Linux driver 47 * v1.5 01-17-2004 timlegge Initial driver output cleanup 48 * 49 * Indent Options: indent -kr -i8 50 ***************************************************************************/ 51 /* 52 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 53 * Modified to use le32_to_cpu and cpu_to_le32 properly 54 */ 55 #include <common.h> 56 #include <malloc.h> 57 #include <net.h> 58 #include <netdev.h> 59 #include <asm/io.h> 60 #include <pci.h> 61 62 #undef DEBUG_RTL8169 63 #undef DEBUG_RTL8169_TX 64 #undef DEBUG_RTL8169_RX 65 66 #define drv_version "v1.5" 67 #define drv_date "01-17-2004" 68 69 static u32 ioaddr; 70 71 /* Condensed operations for readability. */ 72 #define currticks() get_timer(0) 73 74 /* media options */ 75 #define MAX_UNITS 8 76 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 77 78 /* MAC address length*/ 79 #define MAC_ADDR_LEN 6 80 81 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 82 #define MAX_ETH_FRAME_SIZE 1536 83 84 #define TX_FIFO_THRESH 256 /* In bytes */ 85 86 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 87 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 88 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 89 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 90 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 91 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 92 93 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 94 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 95 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 96 #define RX_BUF_LEN 8192 97 98 #define RTL_MIN_IO_SIZE 0x80 99 #define TX_TIMEOUT (6*HZ) 100 101 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 105 #define RTL_R8(reg) readb (ioaddr + (reg)) 106 #define RTL_R16(reg) readw (ioaddr + (reg)) 107 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 108 109 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 110 #define ETH_ALEN MAC_ADDR_LEN 111 #define ETH_ZLEN 60 112 113 enum RTL8169_registers { 114 MAC0 = 0, /* Ethernet hardware address. */ 115 MAR0 = 8, /* Multicast filter. */ 116 TxDescStartAddrLow = 0x20, 117 TxDescStartAddrHigh = 0x24, 118 TxHDescStartAddrLow = 0x28, 119 TxHDescStartAddrHigh = 0x2c, 120 FLASH = 0x30, 121 ERSR = 0x36, 122 ChipCmd = 0x37, 123 TxPoll = 0x38, 124 IntrMask = 0x3C, 125 IntrStatus = 0x3E, 126 TxConfig = 0x40, 127 RxConfig = 0x44, 128 RxMissed = 0x4C, 129 Cfg9346 = 0x50, 130 Config0 = 0x51, 131 Config1 = 0x52, 132 Config2 = 0x53, 133 Config3 = 0x54, 134 Config4 = 0x55, 135 Config5 = 0x56, 136 MultiIntr = 0x5C, 137 PHYAR = 0x60, 138 TBICSR = 0x64, 139 TBI_ANAR = 0x68, 140 TBI_LPAR = 0x6A, 141 PHYstatus = 0x6C, 142 RxMaxSize = 0xDA, 143 CPlusCmd = 0xE0, 144 RxDescStartAddrLow = 0xE4, 145 RxDescStartAddrHigh = 0xE8, 146 EarlyTxThres = 0xEC, 147 FuncEvent = 0xF0, 148 FuncEventMask = 0xF4, 149 FuncPresetState = 0xF8, 150 FuncForceEvent = 0xFC, 151 }; 152 153 enum RTL8169_register_content { 154 /*InterruptStatusBits */ 155 SYSErr = 0x8000, 156 PCSTimeout = 0x4000, 157 SWInt = 0x0100, 158 TxDescUnavail = 0x80, 159 RxFIFOOver = 0x40, 160 RxUnderrun = 0x20, 161 RxOverflow = 0x10, 162 TxErr = 0x08, 163 TxOK = 0x04, 164 RxErr = 0x02, 165 RxOK = 0x01, 166 167 /*RxStatusDesc */ 168 RxRES = 0x00200000, 169 RxCRC = 0x00080000, 170 RxRUNT = 0x00100000, 171 RxRWT = 0x00400000, 172 173 /*ChipCmdBits */ 174 CmdReset = 0x10, 175 CmdRxEnb = 0x08, 176 CmdTxEnb = 0x04, 177 RxBufEmpty = 0x01, 178 179 /*Cfg9346Bits */ 180 Cfg9346_Lock = 0x00, 181 Cfg9346_Unlock = 0xC0, 182 183 /*rx_mode_bits */ 184 AcceptErr = 0x20, 185 AcceptRunt = 0x10, 186 AcceptBroadcast = 0x08, 187 AcceptMulticast = 0x04, 188 AcceptMyPhys = 0x02, 189 AcceptAllPhys = 0x01, 190 191 /*RxConfigBits */ 192 RxCfgFIFOShift = 13, 193 RxCfgDMAShift = 8, 194 195 /*TxConfigBits */ 196 TxInterFrameGapShift = 24, 197 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 198 199 /*rtl8169_PHYstatus */ 200 TBI_Enable = 0x80, 201 TxFlowCtrl = 0x40, 202 RxFlowCtrl = 0x20, 203 _1000bpsF = 0x10, 204 _100bps = 0x08, 205 _10bps = 0x04, 206 LinkStatus = 0x02, 207 FullDup = 0x01, 208 209 /*GIGABIT_PHY_registers */ 210 PHY_CTRL_REG = 0, 211 PHY_STAT_REG = 1, 212 PHY_AUTO_NEGO_REG = 4, 213 PHY_1000_CTRL_REG = 9, 214 215 /*GIGABIT_PHY_REG_BIT */ 216 PHY_Restart_Auto_Nego = 0x0200, 217 PHY_Enable_Auto_Nego = 0x1000, 218 219 /* PHY_STAT_REG = 1; */ 220 PHY_Auto_Nego_Comp = 0x0020, 221 222 /* PHY_AUTO_NEGO_REG = 4; */ 223 PHY_Cap_10_Half = 0x0020, 224 PHY_Cap_10_Full = 0x0040, 225 PHY_Cap_100_Half = 0x0080, 226 PHY_Cap_100_Full = 0x0100, 227 228 /* PHY_1000_CTRL_REG = 9; */ 229 PHY_Cap_1000_Full = 0x0200, 230 231 PHY_Cap_Null = 0x0, 232 233 /*_MediaType*/ 234 _10_Half = 0x01, 235 _10_Full = 0x02, 236 _100_Half = 0x04, 237 _100_Full = 0x08, 238 _1000_Full = 0x10, 239 240 /*_TBICSRBit*/ 241 TBILinkOK = 0x02000000, 242 }; 243 244 static struct { 245 const char *name; 246 u8 version; /* depend on RTL8169 docs */ 247 u32 RxConfigMask; /* should clear the bits supported by this chip */ 248 } rtl_chip_info[] = { 249 {"RTL-8169", 0x00, 0xff7e1880,}, 250 {"RTL-8169", 0x04, 0xff7e1880,}, 251 {"RTL-8169", 0x00, 0xff7e1880,}, 252 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 253 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 254 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 255 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 256 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 257 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 258 {"RTL-8101e", 0x34, 0xff7e1880,}, 259 {"RTL-8100e", 0x32, 0xff7e1880,}, 260 }; 261 262 enum _DescStatusBit { 263 OWNbit = 0x80000000, 264 EORbit = 0x40000000, 265 FSbit = 0x20000000, 266 LSbit = 0x10000000, 267 }; 268 269 struct TxDesc { 270 u32 status; 271 u32 vlan_tag; 272 u32 buf_addr; 273 u32 buf_Haddr; 274 }; 275 276 struct RxDesc { 277 u32 status; 278 u32 vlan_tag; 279 u32 buf_addr; 280 u32 buf_Haddr; 281 }; 282 283 /* Define the TX Descriptor */ 284 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; 285 /* __attribute__ ((aligned(256))); */ 286 287 /* Create a static buffer of size RX_BUF_SZ for each 288 TX Descriptor. All descriptors point to a 289 part of this buffer */ 290 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; 291 292 /* Define the RX Descriptor */ 293 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; 294 /* __attribute__ ((aligned(256))); */ 295 296 /* Create a static buffer of size RX_BUF_SZ for each 297 RX Descriptor All descriptors point to a 298 part of this buffer */ 299 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; 300 301 struct rtl8169_private { 302 void *mmio_addr; /* memory map physical address */ 303 int chipset; 304 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 305 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 306 unsigned long dirty_tx; 307 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ 308 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ 309 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 310 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 311 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 312 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 313 unsigned char *Tx_skbuff[NUM_TX_DESC]; 314 } tpx; 315 316 static struct rtl8169_private *tpc; 317 318 static const u16 rtl8169_intr_mask = 319 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 320 TxOK | RxErr | RxOK; 321 static const unsigned int rtl8169_rx_config = 322 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 323 324 static struct pci_device_id supported[] = { 325 {PCI_VENDOR_ID_REALTEK, 0x8167}, 326 {PCI_VENDOR_ID_REALTEK, 0x8169}, 327 {} 328 }; 329 330 void mdio_write(int RegAddr, int value) 331 { 332 int i; 333 334 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 335 udelay(1000); 336 337 for (i = 2000; i > 0; i--) { 338 /* Check if the RTL8169 has completed writing to the specified MII register */ 339 if (!(RTL_R32(PHYAR) & 0x80000000)) { 340 break; 341 } else { 342 udelay(100); 343 } 344 } 345 } 346 347 int mdio_read(int RegAddr) 348 { 349 int i, value = -1; 350 351 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 352 udelay(1000); 353 354 for (i = 2000; i > 0; i--) { 355 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 356 if (RTL_R32(PHYAR) & 0x80000000) { 357 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 358 break; 359 } else { 360 udelay(100); 361 } 362 } 363 return value; 364 } 365 366 static int rtl8169_init_board(struct eth_device *dev) 367 { 368 int i; 369 u32 tmp; 370 371 #ifdef DEBUG_RTL8169 372 printf ("%s\n", __FUNCTION__); 373 #endif 374 ioaddr = dev->iobase; 375 376 /* Soft reset the chip. */ 377 RTL_W8(ChipCmd, CmdReset); 378 379 /* Check that the chip has finished the reset. */ 380 for (i = 1000; i > 0; i--) 381 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 382 break; 383 else 384 udelay(10); 385 386 /* identify chip attached to board */ 387 tmp = RTL_R32(TxConfig); 388 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 389 390 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 391 if (tmp == rtl_chip_info[i].version) { 392 tpc->chipset = i; 393 goto match; 394 } 395 } 396 397 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 398 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 399 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 400 tpc->chipset = 0; 401 402 match: 403 return 0; 404 } 405 406 /************************************************************************** 407 RECV - Receive a frame 408 ***************************************************************************/ 409 static int rtl_recv(struct eth_device *dev) 410 { 411 /* return true if there's an ethernet packet ready to read */ 412 /* nic->packet should contain data on return */ 413 /* nic->packetlen should contain length of data */ 414 int cur_rx; 415 int length = 0; 416 417 #ifdef DEBUG_RTL8169_RX 418 printf ("%s\n", __FUNCTION__); 419 #endif 420 ioaddr = dev->iobase; 421 422 cur_rx = tpc->cur_rx; 423 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 424 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 425 unsigned char rxdata[RX_BUF_LEN]; 426 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 427 status) & 0x00001FFF) - 4; 428 429 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 430 NetReceive(rxdata, length); 431 432 if (cur_rx == NUM_RX_DESC - 1) 433 tpc->RxDescArray[cur_rx].status = 434 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 435 else 436 tpc->RxDescArray[cur_rx].status = 437 cpu_to_le32(OWNbit + RX_BUF_SIZE); 438 tpc->RxDescArray[cur_rx].buf_addr = 439 cpu_to_le32((unsigned long)tpc->RxBufferRing[cur_rx]); 440 } else { 441 puts("Error Rx"); 442 } 443 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 444 tpc->cur_rx = cur_rx; 445 return 1; 446 447 } else { 448 ushort sts = RTL_R8(IntrStatus); 449 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 450 udelay(100); /* wait */ 451 } 452 tpc->cur_rx = cur_rx; 453 return (0); /* initially as this is called to flush the input */ 454 } 455 456 #define HZ 1000 457 /************************************************************************** 458 SEND - Transmit a frame 459 ***************************************************************************/ 460 static int rtl_send(struct eth_device *dev, volatile void *packet, int length) 461 { 462 /* send the packet to destination */ 463 464 u32 to; 465 u8 *ptxb; 466 int entry = tpc->cur_tx % NUM_TX_DESC; 467 u32 len = length; 468 int ret; 469 470 #ifdef DEBUG_RTL8169_TX 471 int stime = currticks(); 472 printf ("%s\n", __FUNCTION__); 473 printf("sending %d bytes\n", len); 474 #endif 475 476 ioaddr = dev->iobase; 477 478 /* point to the current txb incase multiple tx_rings are used */ 479 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 480 memcpy(ptxb, (char *)packet, (int)length); 481 482 while (len < ETH_ZLEN) 483 ptxb[len++] = '\0'; 484 485 tpc->TxDescArray[entry].buf_Haddr = 0; 486 tpc->TxDescArray[entry].buf_addr = cpu_to_le32((unsigned long)ptxb); 487 if (entry != (NUM_TX_DESC - 1)) { 488 tpc->TxDescArray[entry].status = 489 cpu_to_le32((OWNbit | FSbit | LSbit) | 490 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 491 } else { 492 tpc->TxDescArray[entry].status = 493 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 494 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 495 } 496 RTL_W8(TxPoll, 0x40); /* set polling bit */ 497 498 tpc->cur_tx++; 499 to = currticks() + TX_TIMEOUT; 500 while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 501 && (currticks() < to)); /* wait */ 502 503 if (currticks() >= to) { 504 #ifdef DEBUG_RTL8169_TX 505 puts ("tx timeout/error\n"); 506 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 507 #endif 508 ret = 0; 509 } else { 510 #ifdef DEBUG_RTL8169_TX 511 puts("tx done\n"); 512 #endif 513 ret = length; 514 } 515 /* Delay to make net console (nc) work properly */ 516 udelay(20); 517 return ret; 518 } 519 520 static void rtl8169_set_rx_mode(struct eth_device *dev) 521 { 522 u32 mc_filter[2]; /* Multicast hash filter */ 523 int rx_mode; 524 u32 tmp = 0; 525 526 #ifdef DEBUG_RTL8169 527 printf ("%s\n", __FUNCTION__); 528 #endif 529 530 /* IFF_ALLMULTI */ 531 /* Too many to filter perfectly -- accept all multicasts. */ 532 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 533 mc_filter[1] = mc_filter[0] = 0xffffffff; 534 535 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 536 rtl_chip_info[tpc->chipset].RxConfigMask); 537 538 RTL_W32(RxConfig, tmp); 539 RTL_W32(MAR0 + 0, mc_filter[0]); 540 RTL_W32(MAR0 + 4, mc_filter[1]); 541 } 542 543 static void rtl8169_hw_start(struct eth_device *dev) 544 { 545 u32 i; 546 547 #ifdef DEBUG_RTL8169 548 int stime = currticks(); 549 printf ("%s\n", __FUNCTION__); 550 #endif 551 552 #if 0 553 /* Soft reset the chip. */ 554 RTL_W8(ChipCmd, CmdReset); 555 556 /* Check that the chip has finished the reset. */ 557 for (i = 1000; i > 0; i--) { 558 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 559 break; 560 else 561 udelay(10); 562 } 563 #endif 564 565 RTL_W8(Cfg9346, Cfg9346_Unlock); 566 567 /* RTL-8169sb/8110sb or previous version */ 568 if (tpc->chipset <= 5) 569 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 570 571 RTL_W8(EarlyTxThres, EarlyTxThld); 572 573 /* For gigabit rtl8169 */ 574 RTL_W16(RxMaxSize, RxPacketMaxSize); 575 576 /* Set Rx Config register */ 577 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 578 rtl_chip_info[tpc->chipset].RxConfigMask); 579 RTL_W32(RxConfig, i); 580 581 /* Set DMA burst size and Interframe Gap Time */ 582 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 583 (InterFrameGap << TxInterFrameGapShift)); 584 585 586 tpc->cur_rx = 0; 587 588 RTL_W32(TxDescStartAddrLow, (unsigned long)tpc->TxDescArray); 589 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 590 RTL_W32(RxDescStartAddrLow, (unsigned long)tpc->RxDescArray); 591 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 592 593 /* RTL-8169sc/8110sc or later version */ 594 if (tpc->chipset > 5) 595 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 596 597 RTL_W8(Cfg9346, Cfg9346_Lock); 598 udelay(10); 599 600 RTL_W32(RxMissed, 0); 601 602 rtl8169_set_rx_mode(dev); 603 604 /* no early-rx interrupts */ 605 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 606 607 #ifdef DEBUG_RTL8169 608 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 609 #endif 610 } 611 612 static void rtl8169_init_ring(struct eth_device *dev) 613 { 614 int i; 615 616 #ifdef DEBUG_RTL8169 617 int stime = currticks(); 618 printf ("%s\n", __FUNCTION__); 619 #endif 620 621 tpc->cur_rx = 0; 622 tpc->cur_tx = 0; 623 tpc->dirty_tx = 0; 624 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 625 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 626 627 for (i = 0; i < NUM_TX_DESC; i++) { 628 tpc->Tx_skbuff[i] = &txb[i]; 629 } 630 631 for (i = 0; i < NUM_RX_DESC; i++) { 632 if (i == (NUM_RX_DESC - 1)) 633 tpc->RxDescArray[i].status = 634 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 635 else 636 tpc->RxDescArray[i].status = 637 cpu_to_le32(OWNbit + RX_BUF_SIZE); 638 639 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 640 tpc->RxDescArray[i].buf_addr = 641 cpu_to_le32((unsigned long)tpc->RxBufferRing[i]); 642 } 643 644 #ifdef DEBUG_RTL8169 645 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 646 #endif 647 } 648 649 /************************************************************************** 650 RESET - Finish setting up the ethernet interface 651 ***************************************************************************/ 652 static int rtl_reset(struct eth_device *dev, bd_t *bis) 653 { 654 int i; 655 656 #ifdef DEBUG_RTL8169 657 int stime = currticks(); 658 printf ("%s\n", __FUNCTION__); 659 #endif 660 661 tpc->TxDescArrays = tx_ring; 662 /* Tx Desscriptor needs 256 bytes alignment; */ 663 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays + 664 255) & ~255); 665 666 tpc->RxDescArrays = rx_ring; 667 /* Rx Desscriptor needs 256 bytes alignment; */ 668 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays + 669 255) & ~255); 670 671 rtl8169_init_ring(dev); 672 rtl8169_hw_start(dev); 673 /* Construct a perfect filter frame with the mac address as first match 674 * and broadcast for all others */ 675 for (i = 0; i < 192; i++) 676 txb[i] = 0xFF; 677 678 txb[0] = dev->enetaddr[0]; 679 txb[1] = dev->enetaddr[1]; 680 txb[2] = dev->enetaddr[2]; 681 txb[3] = dev->enetaddr[3]; 682 txb[4] = dev->enetaddr[4]; 683 txb[5] = dev->enetaddr[5]; 684 685 #ifdef DEBUG_RTL8169 686 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 687 #endif 688 return 0; 689 } 690 691 /************************************************************************** 692 HALT - Turn off ethernet interface 693 ***************************************************************************/ 694 static void rtl_halt(struct eth_device *dev) 695 { 696 int i; 697 698 #ifdef DEBUG_RTL8169 699 printf ("%s\n", __FUNCTION__); 700 #endif 701 702 ioaddr = dev->iobase; 703 704 /* Stop the chip's Tx and Rx DMA processes. */ 705 RTL_W8(ChipCmd, 0x00); 706 707 /* Disable interrupts by clearing the interrupt mask. */ 708 RTL_W16(IntrMask, 0x0000); 709 710 RTL_W32(RxMissed, 0); 711 712 tpc->TxDescArrays = NULL; 713 tpc->RxDescArrays = NULL; 714 tpc->TxDescArray = NULL; 715 tpc->RxDescArray = NULL; 716 for (i = 0; i < NUM_RX_DESC; i++) { 717 tpc->RxBufferRing[i] = NULL; 718 } 719 } 720 721 /************************************************************************** 722 INIT - Look for an adapter, this routine's visible to the outside 723 ***************************************************************************/ 724 725 #define board_found 1 726 #define valid_link 0 727 static int rtl_init(struct eth_device *dev, bd_t *bis) 728 { 729 static int board_idx = -1; 730 static int printed_version = 0; 731 int i, rc; 732 int option = -1, Cap10_100 = 0, Cap1000 = 0; 733 734 #ifdef DEBUG_RTL8169 735 printf ("%s\n", __FUNCTION__); 736 #endif 737 738 ioaddr = dev->iobase; 739 740 board_idx++; 741 742 printed_version = 1; 743 744 /* point to private storage */ 745 tpc = &tpx; 746 747 rc = rtl8169_init_board(dev); 748 if (rc) 749 return rc; 750 751 /* Get MAC address. FIXME: read EEPROM */ 752 for (i = 0; i < MAC_ADDR_LEN; i++) 753 bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i); 754 755 #ifdef DEBUG_RTL8169 756 printf("chipset = %d\n", tpc->chipset); 757 printf("MAC Address"); 758 for (i = 0; i < MAC_ADDR_LEN; i++) 759 printf(":%02x", dev->enetaddr[i]); 760 putc('\n'); 761 #endif 762 763 #ifdef DEBUG_RTL8169 764 /* Print out some hardware info */ 765 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); 766 #endif 767 768 /* if TBI is not endbled */ 769 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 770 int val = mdio_read(PHY_AUTO_NEGO_REG); 771 772 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 773 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 774 if (option > 0) { 775 #ifdef DEBUG_RTL8169 776 printf("%s: Force-mode Enabled.\n", dev->name); 777 #endif 778 Cap10_100 = 0, Cap1000 = 0; 779 switch (option) { 780 case _10_Half: 781 Cap10_100 = PHY_Cap_10_Half; 782 Cap1000 = PHY_Cap_Null; 783 break; 784 case _10_Full: 785 Cap10_100 = PHY_Cap_10_Full; 786 Cap1000 = PHY_Cap_Null; 787 break; 788 case _100_Half: 789 Cap10_100 = PHY_Cap_100_Half; 790 Cap1000 = PHY_Cap_Null; 791 break; 792 case _100_Full: 793 Cap10_100 = PHY_Cap_100_Full; 794 Cap1000 = PHY_Cap_Null; 795 break; 796 case _1000_Full: 797 Cap10_100 = PHY_Cap_Null; 798 Cap1000 = PHY_Cap_1000_Full; 799 break; 800 default: 801 break; 802 } 803 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 804 mdio_write(PHY_1000_CTRL_REG, Cap1000); 805 } else { 806 #ifdef DEBUG_RTL8169 807 printf("%s: Auto-negotiation Enabled.\n", 808 dev->name); 809 #endif 810 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 811 mdio_write(PHY_AUTO_NEGO_REG, 812 PHY_Cap_10_Half | PHY_Cap_10_Full | 813 PHY_Cap_100_Half | PHY_Cap_100_Full | 814 (val & 0x1F)); 815 816 /* enable 1000 Full Mode */ 817 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 818 819 } 820 821 /* Enable auto-negotiation and restart auto-nigotiation */ 822 mdio_write(PHY_CTRL_REG, 823 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 824 udelay(100); 825 826 /* wait for auto-negotiation process */ 827 for (i = 10000; i > 0; i--) { 828 /* check if auto-negotiation complete */ 829 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 830 udelay(100); 831 option = RTL_R8(PHYstatus); 832 if (option & _1000bpsF) { 833 #ifdef DEBUG_RTL8169 834 printf("%s: 1000Mbps Full-duplex operation.\n", 835 dev->name); 836 #endif 837 } else { 838 #ifdef DEBUG_RTL8169 839 printf("%s: %sMbps %s-duplex operation.\n", 840 dev->name, 841 (option & _100bps) ? "100" : 842 "10", 843 (option & FullDup) ? "Full" : 844 "Half"); 845 #endif 846 } 847 break; 848 } else { 849 udelay(100); 850 } 851 } /* end for-loop to wait for auto-negotiation process */ 852 853 } else { 854 udelay(100); 855 #ifdef DEBUG_RTL8169 856 printf 857 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 858 dev->name, 859 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 860 #endif 861 } 862 863 return 1; 864 } 865 866 int rtl8169_initialize(bd_t *bis) 867 { 868 pci_dev_t devno; 869 int card_number = 0; 870 struct eth_device *dev; 871 u32 iobase; 872 int idx=0; 873 874 while(1){ 875 /* Find RTL8169 */ 876 if ((devno = pci_find_devices(supported, idx++)) < 0) 877 break; 878 879 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); 880 iobase &= ~0xf; 881 882 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 883 884 dev = (struct eth_device *)malloc(sizeof *dev); 885 886 sprintf (dev->name, "RTL8169#%d", card_number); 887 888 dev->priv = (void *) devno; 889 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 890 891 dev->init = rtl_reset; 892 dev->halt = rtl_halt; 893 dev->send = rtl_send; 894 dev->recv = rtl_recv; 895 896 eth_register (dev); 897 898 rtl_init(dev, bis); 899 900 card_number++; 901 } 902 return card_number; 903 } 904