1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 28 * Portions of this code based on: 29 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 30 * for Linux kernel 2.4.x. 31 * 32 * Written 2002 ShuChen <shuchen@realtek.com.tw> 33 * See Linux Driver for full information 34 * 35 * Linux Driver Version 1.27a, 10.02.2002 36 * 37 * Thanks to: 38 * Jean Chen of RealTek Semiconductor Corp. for 39 * providing the evaluation NIC used to develop 40 * this driver. RealTek's support for Etherboot 41 * is appreciated. 42 * 43 * REVISION HISTORY: 44 * ================ 45 * 46 * v1.0 11-26-2003 timlegge Initial port of Linux driver 47 * v1.5 01-17-2004 timlegge Initial driver output cleanup 48 * 49 * Indent Options: indent -kr -i8 50 ***************************************************************************/ 51 /* 52 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 53 * Modified to use le32_to_cpu and cpu_to_le32 properly 54 */ 55 #include <common.h> 56 #include <malloc.h> 57 #include <net.h> 58 #include <asm/io.h> 59 #include <pci.h> 60 61 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ 62 defined(CONFIG_RTL8169) 63 64 #undef DEBUG_RTL8169 65 #undef DEBUG_RTL8169_TX 66 #undef DEBUG_RTL8169_RX 67 68 #define drv_version "v1.5" 69 #define drv_date "01-17-2004" 70 71 static u32 ioaddr; 72 73 /* Condensed operations for readability. */ 74 #define currticks() get_timer(0) 75 76 /* media options */ 77 #define MAX_UNITS 8 78 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 79 80 /* MAC address length*/ 81 #define MAC_ADDR_LEN 6 82 83 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 84 #define MAX_ETH_FRAME_SIZE 1536 85 86 #define TX_FIFO_THRESH 256 /* In bytes */ 87 88 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 89 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 90 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 91 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 92 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 93 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 94 95 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 96 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 97 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 98 #define RX_BUF_LEN 8192 99 100 #define RTL_MIN_IO_SIZE 0x80 101 #define TX_TIMEOUT (6*HZ) 102 103 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 104 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) 105 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) 106 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) 107 #define RTL_R8(reg) readb (ioaddr + (reg)) 108 #define RTL_R16(reg) readw (ioaddr + (reg)) 109 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) 110 111 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 112 #define ETH_ALEN MAC_ADDR_LEN 113 #define ETH_ZLEN 60 114 115 enum RTL8169_registers { 116 MAC0 = 0, /* Ethernet hardware address. */ 117 MAR0 = 8, /* Multicast filter. */ 118 TxDescStartAddr = 0x20, 119 TxHDescStartAddr = 0x28, 120 FLASH = 0x30, 121 ERSR = 0x36, 122 ChipCmd = 0x37, 123 TxPoll = 0x38, 124 IntrMask = 0x3C, 125 IntrStatus = 0x3E, 126 TxConfig = 0x40, 127 RxConfig = 0x44, 128 RxMissed = 0x4C, 129 Cfg9346 = 0x50, 130 Config0 = 0x51, 131 Config1 = 0x52, 132 Config2 = 0x53, 133 Config3 = 0x54, 134 Config4 = 0x55, 135 Config5 = 0x56, 136 MultiIntr = 0x5C, 137 PHYAR = 0x60, 138 TBICSR = 0x64, 139 TBI_ANAR = 0x68, 140 TBI_LPAR = 0x6A, 141 PHYstatus = 0x6C, 142 RxMaxSize = 0xDA, 143 CPlusCmd = 0xE0, 144 RxDescStartAddr = 0xE4, 145 EarlyTxThres = 0xEC, 146 FuncEvent = 0xF0, 147 FuncEventMask = 0xF4, 148 FuncPresetState = 0xF8, 149 FuncForceEvent = 0xFC, 150 }; 151 152 enum RTL8169_register_content { 153 /*InterruptStatusBits */ 154 SYSErr = 0x8000, 155 PCSTimeout = 0x4000, 156 SWInt = 0x0100, 157 TxDescUnavail = 0x80, 158 RxFIFOOver = 0x40, 159 RxUnderrun = 0x20, 160 RxOverflow = 0x10, 161 TxErr = 0x08, 162 TxOK = 0x04, 163 RxErr = 0x02, 164 RxOK = 0x01, 165 166 /*RxStatusDesc */ 167 RxRES = 0x00200000, 168 RxCRC = 0x00080000, 169 RxRUNT = 0x00100000, 170 RxRWT = 0x00400000, 171 172 /*ChipCmdBits */ 173 CmdReset = 0x10, 174 CmdRxEnb = 0x08, 175 CmdTxEnb = 0x04, 176 RxBufEmpty = 0x01, 177 178 /*Cfg9346Bits */ 179 Cfg9346_Lock = 0x00, 180 Cfg9346_Unlock = 0xC0, 181 182 /*rx_mode_bits */ 183 AcceptErr = 0x20, 184 AcceptRunt = 0x10, 185 AcceptBroadcast = 0x08, 186 AcceptMulticast = 0x04, 187 AcceptMyPhys = 0x02, 188 AcceptAllPhys = 0x01, 189 190 /*RxConfigBits */ 191 RxCfgFIFOShift = 13, 192 RxCfgDMAShift = 8, 193 194 /*TxConfigBits */ 195 TxInterFrameGapShift = 24, 196 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 197 198 /*rtl8169_PHYstatus */ 199 TBI_Enable = 0x80, 200 TxFlowCtrl = 0x40, 201 RxFlowCtrl = 0x20, 202 _1000bpsF = 0x10, 203 _100bps = 0x08, 204 _10bps = 0x04, 205 LinkStatus = 0x02, 206 FullDup = 0x01, 207 208 /*GIGABIT_PHY_registers */ 209 PHY_CTRL_REG = 0, 210 PHY_STAT_REG = 1, 211 PHY_AUTO_NEGO_REG = 4, 212 PHY_1000_CTRL_REG = 9, 213 214 /*GIGABIT_PHY_REG_BIT */ 215 PHY_Restart_Auto_Nego = 0x0200, 216 PHY_Enable_Auto_Nego = 0x1000, 217 218 /* PHY_STAT_REG = 1; */ 219 PHY_Auto_Nego_Comp = 0x0020, 220 221 /* PHY_AUTO_NEGO_REG = 4; */ 222 PHY_Cap_10_Half = 0x0020, 223 PHY_Cap_10_Full = 0x0040, 224 PHY_Cap_100_Half = 0x0080, 225 PHY_Cap_100_Full = 0x0100, 226 227 /* PHY_1000_CTRL_REG = 9; */ 228 PHY_Cap_1000_Full = 0x0200, 229 230 PHY_Cap_Null = 0x0, 231 232 /*_MediaType*/ 233 _10_Half = 0x01, 234 _10_Full = 0x02, 235 _100_Half = 0x04, 236 _100_Full = 0x08, 237 _1000_Full = 0x10, 238 239 /*_TBICSRBit*/ 240 TBILinkOK = 0x02000000, 241 }; 242 243 static struct { 244 const char *name; 245 u8 version; /* depend on RTL8169 docs */ 246 u32 RxConfigMask; /* should clear the bits supported by this chip */ 247 } rtl_chip_info[] = { 248 {"RTL-8169", 0x00, 0xff7e1880,}, 249 {"RTL-8169", 0x04, 0xff7e1880,}, 250 }; 251 252 enum _DescStatusBit { 253 OWNbit = 0x80000000, 254 EORbit = 0x40000000, 255 FSbit = 0x20000000, 256 LSbit = 0x10000000, 257 }; 258 259 struct TxDesc { 260 u32 status; 261 u32 vlan_tag; 262 u32 buf_addr; 263 u32 buf_Haddr; 264 }; 265 266 struct RxDesc { 267 u32 status; 268 u32 vlan_tag; 269 u32 buf_addr; 270 u32 buf_Haddr; 271 }; 272 273 /* Define the TX Descriptor */ 274 static u8 tx_ring[NUM_TX_DESC * sizeof(struct TxDesc) + 256]; 275 /* __attribute__ ((aligned(256))); */ 276 277 /* Create a static buffer of size RX_BUF_SZ for each 278 TX Descriptor. All descriptors point to a 279 part of this buffer */ 280 static unsigned char txb[NUM_TX_DESC * RX_BUF_SIZE]; 281 282 /* Define the RX Descriptor */ 283 static u8 rx_ring[NUM_RX_DESC * sizeof(struct TxDesc) + 256]; 284 /* __attribute__ ((aligned(256))); */ 285 286 /* Create a static buffer of size RX_BUF_SZ for each 287 RX Descriptor All descriptors point to a 288 part of this buffer */ 289 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]; 290 291 struct rtl8169_private { 292 void *mmio_addr; /* memory map physical address */ 293 int chipset; 294 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 295 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 296 unsigned long dirty_tx; 297 unsigned char *TxDescArrays; /* Index of Tx Descriptor buffer */ 298 unsigned char *RxDescArrays; /* Index of Rx Descriptor buffer */ 299 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 300 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 301 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 302 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 303 unsigned char *Tx_skbuff[NUM_TX_DESC]; 304 } tpx; 305 306 static struct rtl8169_private *tpc; 307 308 static const u16 rtl8169_intr_mask = 309 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 310 TxOK | RxErr | RxOK; 311 static const unsigned int rtl8169_rx_config = 312 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 313 314 static struct pci_device_id supported[] = { 315 {PCI_VENDOR_ID_REALTEK, 0x8169}, 316 {} 317 }; 318 319 void mdio_write(int RegAddr, int value) 320 { 321 int i; 322 323 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 324 udelay(1000); 325 326 for (i = 2000; i > 0; i--) { 327 /* Check if the RTL8169 has completed writing to the specified MII register */ 328 if (!(RTL_R32(PHYAR) & 0x80000000)) { 329 break; 330 } else { 331 udelay(100); 332 } 333 } 334 } 335 336 int mdio_read(int RegAddr) 337 { 338 int i, value = -1; 339 340 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 341 udelay(1000); 342 343 for (i = 2000; i > 0; i--) { 344 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 345 if (RTL_R32(PHYAR) & 0x80000000) { 346 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 347 break; 348 } else { 349 udelay(100); 350 } 351 } 352 return value; 353 } 354 355 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) 356 357 static int rtl8169_init_board(struct eth_device *dev) 358 { 359 int i; 360 u32 tmp; 361 362 #ifdef DEBUG_RTL8169 363 printf ("%s\n", __FUNCTION__); 364 #endif 365 ioaddr = dev->iobase; 366 367 /* Soft reset the chip. */ 368 RTL_W8(ChipCmd, CmdReset); 369 370 /* Check that the chip has finished the reset. */ 371 for (i = 1000; i > 0; i--) 372 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 373 break; 374 else 375 udelay(10); 376 377 /* identify chip attached to board */ 378 tmp = RTL_R32(TxConfig); 379 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 380 381 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 382 if (tmp == rtl_chip_info[i].version) { 383 tpc->chipset = i; 384 goto match; 385 } 386 } 387 388 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 389 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 390 printf("PCI device: TxConfig = 0x%hX\n", (unsigned long) RTL_R32(TxConfig)); 391 tpc->chipset = 0; 392 393 match: 394 return 0; 395 } 396 397 /************************************************************************** 398 RECV - Receive a frame 399 ***************************************************************************/ 400 static int rtl_recv(struct eth_device *dev) 401 { 402 /* return true if there's an ethernet packet ready to read */ 403 /* nic->packet should contain data on return */ 404 /* nic->packetlen should contain length of data */ 405 int cur_rx; 406 int length = 0; 407 408 #ifdef DEBUG_RTL8169_RX 409 printf ("%s\n", __FUNCTION__); 410 #endif 411 ioaddr = dev->iobase; 412 413 cur_rx = tpc->cur_rx; 414 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 415 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 416 unsigned char rxdata[RX_BUF_LEN]; 417 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 418 status) & 0x00001FFF) - 4; 419 420 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 421 NetReceive(rxdata, length); 422 423 if (cur_rx == NUM_RX_DESC - 1) 424 tpc->RxDescArray[cur_rx].status = 425 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 426 else 427 tpc->RxDescArray[cur_rx].status = 428 cpu_to_le32(OWNbit + RX_BUF_SIZE); 429 tpc->RxDescArray[cur_rx].buf_addr = 430 cpu_to_le32(tpc->RxBufferRing[cur_rx]); 431 } else { 432 puts("Error Rx"); 433 } 434 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 435 tpc->cur_rx = cur_rx; 436 return 1; 437 438 } 439 tpc->cur_rx = cur_rx; 440 return (0); /* initially as this is called to flush the input */ 441 } 442 443 #define HZ 1000 444 /************************************************************************** 445 SEND - Transmit a frame 446 ***************************************************************************/ 447 static int rtl_send(struct eth_device *dev, volatile void *packet, int length) 448 { 449 /* send the packet to destination */ 450 451 u32 to; 452 u8 *ptxb; 453 int entry = tpc->cur_tx % NUM_TX_DESC; 454 u32 len = length; 455 int ret; 456 457 #ifdef DEBUG_RTL8169_TX 458 int stime = currticks(); 459 printf ("%s\n", __FUNCTION__); 460 printf("sending %d bytes\n", len); 461 #endif 462 463 ioaddr = dev->iobase; 464 465 /* point to the current txb incase multiple tx_rings are used */ 466 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 467 memcpy(ptxb, (char *)packet, (int)length); 468 469 while (len < ETH_ZLEN) 470 ptxb[len++] = '\0'; 471 472 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(ptxb); 473 if (entry != (NUM_TX_DESC - 1)) { 474 tpc->TxDescArray[entry].status = 475 cpu_to_le32((OWNbit | FSbit | LSbit) | 476 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 477 } else { 478 tpc->TxDescArray[entry].status = 479 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 480 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 481 } 482 RTL_W8(TxPoll, 0x40); /* set polling bit */ 483 484 tpc->cur_tx++; 485 to = currticks() + TX_TIMEOUT; 486 while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 487 && (currticks() < to)); /* wait */ 488 489 if (currticks() >= to) { 490 #ifdef DEBUG_RTL8169_TX 491 puts ("tx timeout/error\n"); 492 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 493 #endif 494 ret = 0; 495 } else { 496 #ifdef DEBUG_RTL8169_TX 497 puts("tx done\n"); 498 #endif 499 ret = length; 500 } 501 /* Delay to make net console (nc) work properly */ 502 udelay(20); 503 return ret; 504 } 505 506 static void rtl8169_set_rx_mode(struct eth_device *dev) 507 { 508 u32 mc_filter[2]; /* Multicast hash filter */ 509 int rx_mode; 510 u32 tmp = 0; 511 512 #ifdef DEBUG_RTL8169 513 printf ("%s\n", __FUNCTION__); 514 #endif 515 516 /* IFF_ALLMULTI */ 517 /* Too many to filter perfectly -- accept all multicasts. */ 518 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 519 mc_filter[1] = mc_filter[0] = 0xffffffff; 520 521 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 522 rtl_chip_info[tpc->chipset].RxConfigMask); 523 524 RTL_W32(RxConfig, tmp); 525 RTL_W32(MAR0 + 0, mc_filter[0]); 526 RTL_W32(MAR0 + 4, mc_filter[1]); 527 } 528 529 static void rtl8169_hw_start(struct eth_device *dev) 530 { 531 u32 i; 532 533 #ifdef DEBUG_RTL8169 534 int stime = currticks(); 535 printf ("%s\n", __FUNCTION__); 536 #endif 537 538 #if 0 539 /* Soft reset the chip. */ 540 RTL_W8(ChipCmd, CmdReset); 541 542 /* Check that the chip has finished the reset. */ 543 for (i = 1000; i > 0; i--) { 544 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 545 break; 546 else 547 udelay(10); 548 } 549 #endif 550 551 RTL_W8(Cfg9346, Cfg9346_Unlock); 552 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 553 RTL_W8(EarlyTxThres, EarlyTxThld); 554 555 /* For gigabit rtl8169 */ 556 RTL_W16(RxMaxSize, RxPacketMaxSize); 557 558 /* Set Rx Config register */ 559 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 560 rtl_chip_info[tpc->chipset].RxConfigMask); 561 RTL_W32(RxConfig, i); 562 563 /* Set DMA burst size and Interframe Gap Time */ 564 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 565 (InterFrameGap << TxInterFrameGapShift)); 566 567 568 tpc->cur_rx = 0; 569 570 RTL_W32(TxDescStartAddr, tpc->TxDescArray); 571 RTL_W32(RxDescStartAddr, tpc->RxDescArray); 572 RTL_W8(Cfg9346, Cfg9346_Lock); 573 udelay(10); 574 575 RTL_W32(RxMissed, 0); 576 577 rtl8169_set_rx_mode(dev); 578 579 /* no early-rx interrupts */ 580 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 581 582 #ifdef DEBUG_RTL8169 583 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 584 #endif 585 } 586 587 static void rtl8169_init_ring(struct eth_device *dev) 588 { 589 int i; 590 591 #ifdef DEBUG_RTL8169 592 int stime = currticks(); 593 printf ("%s\n", __FUNCTION__); 594 #endif 595 596 tpc->cur_rx = 0; 597 tpc->cur_tx = 0; 598 tpc->dirty_tx = 0; 599 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 600 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 601 602 for (i = 0; i < NUM_TX_DESC; i++) { 603 tpc->Tx_skbuff[i] = &txb[i]; 604 } 605 606 for (i = 0; i < NUM_RX_DESC; i++) { 607 if (i == (NUM_RX_DESC - 1)) 608 tpc->RxDescArray[i].status = 609 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 610 else 611 tpc->RxDescArray[i].status = 612 cpu_to_le32(OWNbit + RX_BUF_SIZE); 613 614 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 615 tpc->RxDescArray[i].buf_addr = 616 cpu_to_le32(tpc->RxBufferRing[i]); 617 } 618 619 #ifdef DEBUG_RTL8169 620 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 621 #endif 622 } 623 624 /************************************************************************** 625 RESET - Finish setting up the ethernet interface 626 ***************************************************************************/ 627 static void rtl_reset(struct eth_device *dev, bd_t *bis) 628 { 629 int i; 630 631 #ifdef DEBUG_RTL8169 632 int stime = currticks(); 633 printf ("%s\n", __FUNCTION__); 634 #endif 635 636 tpc->TxDescArrays = tx_ring; 637 /* Tx Desscriptor needs 256 bytes alignment; */ 638 tpc->TxDescArray = (struct TxDesc *) ((unsigned long)(tpc->TxDescArrays + 639 255) & ~255); 640 641 tpc->RxDescArrays = rx_ring; 642 /* Rx Desscriptor needs 256 bytes alignment; */ 643 tpc->RxDescArray = (struct RxDesc *) ((unsigned long)(tpc->RxDescArrays + 644 255) & ~255); 645 646 rtl8169_init_ring(dev); 647 rtl8169_hw_start(dev); 648 /* Construct a perfect filter frame with the mac address as first match 649 * and broadcast for all others */ 650 for (i = 0; i < 192; i++) 651 txb[i] = 0xFF; 652 653 txb[0] = dev->enetaddr[0]; 654 txb[1] = dev->enetaddr[1]; 655 txb[2] = dev->enetaddr[2]; 656 txb[3] = dev->enetaddr[3]; 657 txb[4] = dev->enetaddr[4]; 658 txb[5] = dev->enetaddr[5]; 659 660 #ifdef DEBUG_RTL8169 661 printf ("%s elapsed time : %d\n", __FUNCTION__, currticks()-stime); 662 #endif 663 } 664 665 /************************************************************************** 666 HALT - Turn off ethernet interface 667 ***************************************************************************/ 668 static void rtl_halt(struct eth_device *dev) 669 { 670 int i; 671 672 #ifdef DEBUG_RTL8169 673 printf ("%s\n", __FUNCTION__); 674 #endif 675 676 ioaddr = dev->iobase; 677 678 /* Stop the chip's Tx and Rx DMA processes. */ 679 RTL_W8(ChipCmd, 0x00); 680 681 /* Disable interrupts by clearing the interrupt mask. */ 682 RTL_W16(IntrMask, 0x0000); 683 684 RTL_W32(RxMissed, 0); 685 686 tpc->TxDescArrays = NULL; 687 tpc->RxDescArrays = NULL; 688 tpc->TxDescArray = NULL; 689 tpc->RxDescArray = NULL; 690 for (i = 0; i < NUM_RX_DESC; i++) { 691 tpc->RxBufferRing[i] = NULL; 692 } 693 } 694 695 /************************************************************************** 696 INIT - Look for an adapter, this routine's visible to the outside 697 ***************************************************************************/ 698 699 #define board_found 1 700 #define valid_link 0 701 static int rtl_init(struct eth_device *dev, bd_t *bis) 702 { 703 static int board_idx = -1; 704 static int printed_version = 0; 705 int i, rc; 706 int option = -1, Cap10_100 = 0, Cap1000 = 0; 707 708 #ifdef DEBUG_RTL8169 709 printf ("%s\n", __FUNCTION__); 710 #endif 711 712 ioaddr = dev->iobase; 713 714 board_idx++; 715 716 printed_version = 1; 717 718 /* point to private storage */ 719 tpc = &tpx; 720 721 rc = rtl8169_init_board(dev); 722 if (rc) 723 return rc; 724 725 /* Get MAC address. FIXME: read EEPROM */ 726 for (i = 0; i < MAC_ADDR_LEN; i++) 727 bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i); 728 729 #ifdef DEBUG_RTL8169 730 printf("MAC Address"); 731 for (i = 0; i < MAC_ADDR_LEN; i++) 732 printf(":%02x", dev->enetaddr[i]); 733 putc('\n'); 734 #endif 735 736 #ifdef DEBUG_RTL8169 737 /* Print out some hardware info */ 738 printf("%s: at ioaddr 0x%x\n", dev->name, ioaddr); 739 #endif 740 741 /* if TBI is not endbled */ 742 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 743 int val = mdio_read(PHY_AUTO_NEGO_REG); 744 745 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 746 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 747 if (option > 0) { 748 #ifdef DEBUG_RTL8169 749 printf("%s: Force-mode Enabled.\n", dev->name); 750 #endif 751 Cap10_100 = 0, Cap1000 = 0; 752 switch (option) { 753 case _10_Half: 754 Cap10_100 = PHY_Cap_10_Half; 755 Cap1000 = PHY_Cap_Null; 756 break; 757 case _10_Full: 758 Cap10_100 = PHY_Cap_10_Full; 759 Cap1000 = PHY_Cap_Null; 760 break; 761 case _100_Half: 762 Cap10_100 = PHY_Cap_100_Half; 763 Cap1000 = PHY_Cap_Null; 764 break; 765 case _100_Full: 766 Cap10_100 = PHY_Cap_100_Full; 767 Cap1000 = PHY_Cap_Null; 768 break; 769 case _1000_Full: 770 Cap10_100 = PHY_Cap_Null; 771 Cap1000 = PHY_Cap_1000_Full; 772 break; 773 default: 774 break; 775 } 776 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 777 mdio_write(PHY_1000_CTRL_REG, Cap1000); 778 } else { 779 #ifdef DEBUG_RTL8169 780 printf("%s: Auto-negotiation Enabled.\n", 781 dev->name); 782 #endif 783 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 784 mdio_write(PHY_AUTO_NEGO_REG, 785 PHY_Cap_10_Half | PHY_Cap_10_Full | 786 PHY_Cap_100_Half | PHY_Cap_100_Full | 787 (val & 0x1F)); 788 789 /* enable 1000 Full Mode */ 790 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 791 792 } 793 794 /* Enable auto-negotiation and restart auto-nigotiation */ 795 mdio_write(PHY_CTRL_REG, 796 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 797 udelay(100); 798 799 /* wait for auto-negotiation process */ 800 for (i = 10000; i > 0; i--) { 801 /* check if auto-negotiation complete */ 802 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 803 udelay(100); 804 option = RTL_R8(PHYstatus); 805 if (option & _1000bpsF) { 806 #ifdef DEBUG_RTL8169 807 printf("%s: 1000Mbps Full-duplex operation.\n", 808 dev->name); 809 #endif 810 } else { 811 #ifdef DEBUG_RTL8169 812 printf("%s: %sMbps %s-duplex operation.\n", 813 dev->name, 814 (option & _100bps) ? "100" : 815 "10", 816 (option & FullDup) ? "Full" : 817 "Half"); 818 #endif 819 } 820 break; 821 } else { 822 udelay(100); 823 } 824 } /* end for-loop to wait for auto-negotiation process */ 825 826 } else { 827 udelay(100); 828 #ifdef DEBUG_RTL8169 829 printf 830 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 831 dev->name, 832 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 833 #endif 834 } 835 836 return 1; 837 } 838 839 int rtl8169_initialize(bd_t *bis) 840 { 841 pci_dev_t devno; 842 int card_number = 0; 843 struct eth_device *dev; 844 u32 iobase; 845 int idx=0; 846 847 while(1){ 848 /* Find RTL8169 */ 849 if ((devno = pci_find_devices(supported, idx++)) < 0) 850 break; 851 852 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); 853 iobase &= ~0xf; 854 855 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 856 857 dev = (struct eth_device *)malloc(sizeof *dev); 858 859 sprintf (dev->name, "RTL8169#%d", card_number); 860 861 dev->priv = (void *) devno; 862 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 863 864 dev->init = rtl_reset; 865 dev->halt = rtl_halt; 866 dev->send = rtl_send; 867 dev->recv = rtl_recv; 868 869 eth_register (dev); 870 871 rtl_init(dev, bis); 872 873 card_number++; 874 } 875 return card_number; 876 } 877 878 #endif 879