1 /* 2 * rtl8169.c : U-Boot driver for the RealTek RTL8169 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from r8169.c of etherboot 7 * 8 */ 9 10 /************************************************************************** 11 * r8169.c: Etherboot device driver for the RealTek RTL-8169 Gigabit 12 * Written 2003 by Timothy Legge <tlegge@rogers.com> 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 * 16 * Portions of this code based on: 17 * r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver 18 * for Linux kernel 2.4.x. 19 * 20 * Written 2002 ShuChen <shuchen@realtek.com.tw> 21 * See Linux Driver for full information 22 * 23 * Linux Driver Version 1.27a, 10.02.2002 24 * 25 * Thanks to: 26 * Jean Chen of RealTek Semiconductor Corp. for 27 * providing the evaluation NIC used to develop 28 * this driver. RealTek's support for Etherboot 29 * is appreciated. 30 * 31 * REVISION HISTORY: 32 * ================ 33 * 34 * v1.0 11-26-2003 timlegge Initial port of Linux driver 35 * v1.5 01-17-2004 timlegge Initial driver output cleanup 36 * 37 * Indent Options: indent -kr -i8 38 ***************************************************************************/ 39 /* 40 * 26 August 2006 Mihai Georgian <u-boot@linuxnotincluded.org.uk> 41 * Modified to use le32_to_cpu and cpu_to_le32 properly 42 */ 43 #include <common.h> 44 #include <errno.h> 45 #include <malloc.h> 46 #include <net.h> 47 #include <netdev.h> 48 #include <asm/io.h> 49 #include <pci.h> 50 51 #undef DEBUG_RTL8169 52 #undef DEBUG_RTL8169_TX 53 #undef DEBUG_RTL8169_RX 54 55 #define drv_version "v1.5" 56 #define drv_date "01-17-2004" 57 58 static unsigned long ioaddr; 59 60 /* Condensed operations for readability. */ 61 #define currticks() get_timer(0) 62 63 /* media options */ 64 #define MAX_UNITS 8 65 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; 66 67 /* MAC address length*/ 68 #define MAC_ADDR_LEN 6 69 70 /* max supported gigabit ethernet frame size -- must be at least (dev->mtu+14+4).*/ 71 #define MAX_ETH_FRAME_SIZE 1536 72 73 #define TX_FIFO_THRESH 256 /* In bytes */ 74 75 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ 76 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 77 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ 78 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ 79 #define RxPacketMaxSize 0x0800 /* Maximum size supported is 16K-1 */ 80 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 81 82 #define NUM_TX_DESC 1 /* Number of Tx descriptor registers */ 83 #ifdef CONFIG_SYS_RX_ETH_BUFFER 84 #define NUM_RX_DESC CONFIG_SYS_RX_ETH_BUFFER 85 #else 86 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers */ 87 #endif 88 #define RX_BUF_SIZE 1536 /* Rx Buffer size */ 89 #define RX_BUF_LEN 8192 90 91 #define RTL_MIN_IO_SIZE 0x80 92 #define TX_TIMEOUT (6*HZ) 93 94 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */ 95 #define RTL_W8(reg, val8) writeb((val8), ioaddr + (reg)) 96 #define RTL_W16(reg, val16) writew((val16), ioaddr + (reg)) 97 #define RTL_W32(reg, val32) writel((val32), ioaddr + (reg)) 98 #define RTL_R8(reg) readb(ioaddr + (reg)) 99 #define RTL_R16(reg) readw(ioaddr + (reg)) 100 #define RTL_R32(reg) readl(ioaddr + (reg)) 101 102 #define ETH_FRAME_LEN MAX_ETH_FRAME_SIZE 103 #define ETH_ALEN MAC_ADDR_LEN 104 #define ETH_ZLEN 60 105 106 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \ 107 (pci_addr_t)(unsigned long)a) 108 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)(unsigned long)dev->priv, \ 109 (phys_addr_t)a) 110 111 enum RTL8169_registers { 112 MAC0 = 0, /* Ethernet hardware address. */ 113 MAR0 = 8, /* Multicast filter. */ 114 TxDescStartAddrLow = 0x20, 115 TxDescStartAddrHigh = 0x24, 116 TxHDescStartAddrLow = 0x28, 117 TxHDescStartAddrHigh = 0x2c, 118 FLASH = 0x30, 119 ERSR = 0x36, 120 ChipCmd = 0x37, 121 TxPoll = 0x38, 122 IntrMask = 0x3C, 123 IntrStatus = 0x3E, 124 TxConfig = 0x40, 125 RxConfig = 0x44, 126 RxMissed = 0x4C, 127 Cfg9346 = 0x50, 128 Config0 = 0x51, 129 Config1 = 0x52, 130 Config2 = 0x53, 131 Config3 = 0x54, 132 Config4 = 0x55, 133 Config5 = 0x56, 134 MultiIntr = 0x5C, 135 PHYAR = 0x60, 136 TBICSR = 0x64, 137 TBI_ANAR = 0x68, 138 TBI_LPAR = 0x6A, 139 PHYstatus = 0x6C, 140 RxMaxSize = 0xDA, 141 CPlusCmd = 0xE0, 142 RxDescStartAddrLow = 0xE4, 143 RxDescStartAddrHigh = 0xE8, 144 EarlyTxThres = 0xEC, 145 FuncEvent = 0xF0, 146 FuncEventMask = 0xF4, 147 FuncPresetState = 0xF8, 148 FuncForceEvent = 0xFC, 149 }; 150 151 enum RTL8169_register_content { 152 /*InterruptStatusBits */ 153 SYSErr = 0x8000, 154 PCSTimeout = 0x4000, 155 SWInt = 0x0100, 156 TxDescUnavail = 0x80, 157 RxFIFOOver = 0x40, 158 RxUnderrun = 0x20, 159 RxOverflow = 0x10, 160 TxErr = 0x08, 161 TxOK = 0x04, 162 RxErr = 0x02, 163 RxOK = 0x01, 164 165 /*RxStatusDesc */ 166 RxRES = 0x00200000, 167 RxCRC = 0x00080000, 168 RxRUNT = 0x00100000, 169 RxRWT = 0x00400000, 170 171 /*ChipCmdBits */ 172 CmdReset = 0x10, 173 CmdRxEnb = 0x08, 174 CmdTxEnb = 0x04, 175 RxBufEmpty = 0x01, 176 177 /*Cfg9346Bits */ 178 Cfg9346_Lock = 0x00, 179 Cfg9346_Unlock = 0xC0, 180 181 /*rx_mode_bits */ 182 AcceptErr = 0x20, 183 AcceptRunt = 0x10, 184 AcceptBroadcast = 0x08, 185 AcceptMulticast = 0x04, 186 AcceptMyPhys = 0x02, 187 AcceptAllPhys = 0x01, 188 189 /*RxConfigBits */ 190 RxCfgFIFOShift = 13, 191 RxCfgDMAShift = 8, 192 193 /*TxConfigBits */ 194 TxInterFrameGapShift = 24, 195 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 196 197 /*rtl8169_PHYstatus */ 198 TBI_Enable = 0x80, 199 TxFlowCtrl = 0x40, 200 RxFlowCtrl = 0x20, 201 _1000bpsF = 0x10, 202 _100bps = 0x08, 203 _10bps = 0x04, 204 LinkStatus = 0x02, 205 FullDup = 0x01, 206 207 /*GIGABIT_PHY_registers */ 208 PHY_CTRL_REG = 0, 209 PHY_STAT_REG = 1, 210 PHY_AUTO_NEGO_REG = 4, 211 PHY_1000_CTRL_REG = 9, 212 213 /*GIGABIT_PHY_REG_BIT */ 214 PHY_Restart_Auto_Nego = 0x0200, 215 PHY_Enable_Auto_Nego = 0x1000, 216 217 /* PHY_STAT_REG = 1; */ 218 PHY_Auto_Nego_Comp = 0x0020, 219 220 /* PHY_AUTO_NEGO_REG = 4; */ 221 PHY_Cap_10_Half = 0x0020, 222 PHY_Cap_10_Full = 0x0040, 223 PHY_Cap_100_Half = 0x0080, 224 PHY_Cap_100_Full = 0x0100, 225 226 /* PHY_1000_CTRL_REG = 9; */ 227 PHY_Cap_1000_Full = 0x0200, 228 229 PHY_Cap_Null = 0x0, 230 231 /*_MediaType*/ 232 _10_Half = 0x01, 233 _10_Full = 0x02, 234 _100_Half = 0x04, 235 _100_Full = 0x08, 236 _1000_Full = 0x10, 237 238 /*_TBICSRBit*/ 239 TBILinkOK = 0x02000000, 240 }; 241 242 static struct { 243 const char *name; 244 u8 version; /* depend on RTL8169 docs */ 245 u32 RxConfigMask; /* should clear the bits supported by this chip */ 246 } rtl_chip_info[] = { 247 {"RTL-8169", 0x00, 0xff7e1880,}, 248 {"RTL-8169", 0x04, 0xff7e1880,}, 249 {"RTL-8169", 0x00, 0xff7e1880,}, 250 {"RTL-8169s/8110s", 0x02, 0xff7e1880,}, 251 {"RTL-8169s/8110s", 0x04, 0xff7e1880,}, 252 {"RTL-8169sb/8110sb", 0x10, 0xff7e1880,}, 253 {"RTL-8169sc/8110sc", 0x18, 0xff7e1880,}, 254 {"RTL-8168b/8111sb", 0x30, 0xff7e1880,}, 255 {"RTL-8168b/8111sb", 0x38, 0xff7e1880,}, 256 {"RTL-8168d/8111d", 0x28, 0xff7e1880,}, 257 {"RTL-8168evl/8111evl", 0x2e, 0xff7e1880,}, 258 {"RTL-8168/8111g", 0x4c, 0xff7e1880,}, 259 {"RTL-8101e", 0x34, 0xff7e1880,}, 260 {"RTL-8100e", 0x32, 0xff7e1880,}, 261 }; 262 263 enum _DescStatusBit { 264 OWNbit = 0x80000000, 265 EORbit = 0x40000000, 266 FSbit = 0x20000000, 267 LSbit = 0x10000000, 268 }; 269 270 struct TxDesc { 271 u32 status; 272 u32 vlan_tag; 273 u32 buf_addr; 274 u32 buf_Haddr; 275 }; 276 277 struct RxDesc { 278 u32 status; 279 u32 vlan_tag; 280 u32 buf_addr; 281 u32 buf_Haddr; 282 }; 283 284 #define RTL8169_DESC_SIZE 16 285 286 #if ARCH_DMA_MINALIGN > 256 287 # define RTL8169_ALIGN ARCH_DMA_MINALIGN 288 #else 289 # define RTL8169_ALIGN 256 290 #endif 291 292 /* 293 * Warn if the cache-line size is larger than the descriptor size. In such 294 * cases the driver will likely fail because the CPU needs to flush the cache 295 * when requeuing RX buffers, therefore descriptors written by the hardware 296 * may be discarded. 297 * 298 * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause 299 * the driver to allocate descriptors from a pool of non-cached memory. 300 */ 301 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN 302 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && !defined(CONFIG_SYS_DCACHE_OFF) 303 #warning cache-line size is larger than descriptor size 304 #endif 305 #endif 306 307 /* 308 * Create a static buffer of size RX_BUF_SZ for each TX Descriptor. All 309 * descriptors point to a part of this buffer. 310 */ 311 DEFINE_ALIGN_BUFFER(u8, txb, NUM_TX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 312 313 /* 314 * Create a static buffer of size RX_BUF_SZ for each RX Descriptor. All 315 * descriptors point to a part of this buffer. 316 */ 317 DEFINE_ALIGN_BUFFER(u8, rxb, NUM_RX_DESC * RX_BUF_SIZE, RTL8169_ALIGN); 318 319 struct rtl8169_private { 320 void *mmio_addr; /* memory map physical address */ 321 int chipset; 322 unsigned long cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 323 unsigned long cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 324 unsigned long dirty_tx; 325 struct TxDesc *TxDescArray; /* Index of 256-alignment Tx Descriptor buffer */ 326 struct RxDesc *RxDescArray; /* Index of 256-alignment Rx Descriptor buffer */ 327 unsigned char *RxBufferRings; /* Index of Rx Buffer */ 328 unsigned char *RxBufferRing[NUM_RX_DESC]; /* Index of Rx Buffer array */ 329 unsigned char *Tx_skbuff[NUM_TX_DESC]; 330 } tpx; 331 332 static struct rtl8169_private *tpc; 333 334 static const u16 rtl8169_intr_mask = 335 SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr | 336 TxOK | RxErr | RxOK; 337 static const unsigned int rtl8169_rx_config = 338 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); 339 340 static struct pci_device_id supported[] = { 341 {PCI_VENDOR_ID_REALTEK, 0x8167}, 342 {PCI_VENDOR_ID_REALTEK, 0x8168}, 343 {PCI_VENDOR_ID_REALTEK, 0x8169}, 344 {} 345 }; 346 347 void mdio_write(int RegAddr, int value) 348 { 349 int i; 350 351 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value); 352 udelay(1000); 353 354 for (i = 2000; i > 0; i--) { 355 /* Check if the RTL8169 has completed writing to the specified MII register */ 356 if (!(RTL_R32(PHYAR) & 0x80000000)) { 357 break; 358 } else { 359 udelay(100); 360 } 361 } 362 } 363 364 int mdio_read(int RegAddr) 365 { 366 int i, value = -1; 367 368 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16); 369 udelay(1000); 370 371 for (i = 2000; i > 0; i--) { 372 /* Check if the RTL8169 has completed retrieving data from the specified MII register */ 373 if (RTL_R32(PHYAR) & 0x80000000) { 374 value = (int) (RTL_R32(PHYAR) & 0xFFFF); 375 break; 376 } else { 377 udelay(100); 378 } 379 } 380 return value; 381 } 382 383 static int rtl8169_init_board(struct eth_device *dev) 384 { 385 int i; 386 u32 tmp; 387 388 #ifdef DEBUG_RTL8169 389 printf ("%s\n", __FUNCTION__); 390 #endif 391 ioaddr = dev->iobase; 392 393 /* Soft reset the chip. */ 394 RTL_W8(ChipCmd, CmdReset); 395 396 /* Check that the chip has finished the reset. */ 397 for (i = 1000; i > 0; i--) 398 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 399 break; 400 else 401 udelay(10); 402 403 /* identify chip attached to board */ 404 tmp = RTL_R32(TxConfig); 405 tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24; 406 407 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--){ 408 if (tmp == rtl_chip_info[i].version) { 409 tpc->chipset = i; 410 goto match; 411 } 412 } 413 414 /* if unknown chip, assume array element #0, original RTL-8169 in this case */ 415 printf("PCI device %s: unknown chip version, assuming RTL-8169\n", dev->name); 416 printf("PCI device: TxConfig = 0x%lX\n", (unsigned long) RTL_R32(TxConfig)); 417 tpc->chipset = 0; 418 419 match: 420 return 0; 421 } 422 423 /* 424 * TX and RX descriptors are 16 bytes. This causes problems with the cache 425 * maintenance on CPUs where the cache-line size exceeds the size of these 426 * descriptors. What will happen is that when the driver receives a packet 427 * it will be immediately requeued for the hardware to reuse. The CPU will 428 * therefore need to flush the cache-line containing the descriptor, which 429 * will cause all other descriptors in the same cache-line to be flushed 430 * along with it. If one of those descriptors had been written to by the 431 * device those changes (and the associated packet) will be lost. 432 * 433 * To work around this, we make use of non-cached memory if available. If 434 * descriptors are mapped uncached there's no need to manually flush them 435 * or invalidate them. 436 * 437 * Note that this only applies to descriptors. The packet data buffers do 438 * not have the same constraints since they are 1536 bytes large, so they 439 * are unlikely to share cache-lines. 440 */ 441 static void *rtl_alloc_descs(unsigned int num) 442 { 443 size_t size = num * RTL8169_DESC_SIZE; 444 445 #ifdef CONFIG_SYS_NONCACHED_MEMORY 446 return (void *)noncached_alloc(size, RTL8169_ALIGN); 447 #else 448 return memalign(RTL8169_ALIGN, size); 449 #endif 450 } 451 452 /* 453 * Cache maintenance functions. These are simple wrappers around the more 454 * general purpose flush_cache() and invalidate_dcache_range() functions. 455 */ 456 457 static void rtl_inval_rx_desc(struct RxDesc *desc) 458 { 459 #ifndef CONFIG_SYS_NONCACHED_MEMORY 460 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 461 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 462 463 invalidate_dcache_range(start, end); 464 #endif 465 } 466 467 static void rtl_flush_rx_desc(struct RxDesc *desc) 468 { 469 #ifndef CONFIG_SYS_NONCACHED_MEMORY 470 flush_cache((unsigned long)desc, sizeof(*desc)); 471 #endif 472 } 473 474 static void rtl_inval_tx_desc(struct TxDesc *desc) 475 { 476 #ifndef CONFIG_SYS_NONCACHED_MEMORY 477 unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); 478 unsigned long end = ALIGN(start + sizeof(*desc), ARCH_DMA_MINALIGN); 479 480 invalidate_dcache_range(start, end); 481 #endif 482 } 483 484 static void rtl_flush_tx_desc(struct TxDesc *desc) 485 { 486 #ifndef CONFIG_SYS_NONCACHED_MEMORY 487 flush_cache((unsigned long)desc, sizeof(*desc)); 488 #endif 489 } 490 491 static void rtl_inval_buffer(void *buf, size_t size) 492 { 493 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); 494 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); 495 496 invalidate_dcache_range(start, end); 497 } 498 499 static void rtl_flush_buffer(void *buf, size_t size) 500 { 501 flush_cache((unsigned long)buf, size); 502 } 503 504 /************************************************************************** 505 RECV - Receive a frame 506 ***************************************************************************/ 507 static int rtl_recv(struct eth_device *dev) 508 { 509 /* return true if there's an ethernet packet ready to read */ 510 /* nic->packet should contain data on return */ 511 /* nic->packetlen should contain length of data */ 512 int cur_rx; 513 int length = 0; 514 515 #ifdef DEBUG_RTL8169_RX 516 printf ("%s\n", __FUNCTION__); 517 #endif 518 ioaddr = dev->iobase; 519 520 cur_rx = tpc->cur_rx; 521 522 rtl_inval_rx_desc(&tpc->RxDescArray[cur_rx]); 523 524 if ((le32_to_cpu(tpc->RxDescArray[cur_rx].status) & OWNbit) == 0) { 525 if (!(le32_to_cpu(tpc->RxDescArray[cur_rx].status) & RxRES)) { 526 unsigned char rxdata[RX_BUF_LEN]; 527 length = (int) (le32_to_cpu(tpc->RxDescArray[cur_rx]. 528 status) & 0x00001FFF) - 4; 529 530 rtl_inval_buffer(tpc->RxBufferRing[cur_rx], length); 531 memcpy(rxdata, tpc->RxBufferRing[cur_rx], length); 532 533 if (cur_rx == NUM_RX_DESC - 1) 534 tpc->RxDescArray[cur_rx].status = 535 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 536 else 537 tpc->RxDescArray[cur_rx].status = 538 cpu_to_le32(OWNbit + RX_BUF_SIZE); 539 tpc->RxDescArray[cur_rx].buf_addr = 540 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[cur_rx])); 541 rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]); 542 543 net_process_received_packet(rxdata, length); 544 } else { 545 puts("Error Rx"); 546 } 547 cur_rx = (cur_rx + 1) % NUM_RX_DESC; 548 tpc->cur_rx = cur_rx; 549 return 1; 550 551 } else { 552 ushort sts = RTL_R8(IntrStatus); 553 RTL_W8(IntrStatus, sts & ~(TxErr | RxErr | SYSErr)); 554 udelay(100); /* wait */ 555 } 556 tpc->cur_rx = cur_rx; 557 return (0); /* initially as this is called to flush the input */ 558 } 559 560 #define HZ 1000 561 /************************************************************************** 562 SEND - Transmit a frame 563 ***************************************************************************/ 564 static int rtl_send(struct eth_device *dev, void *packet, int length) 565 { 566 /* send the packet to destination */ 567 568 u32 to; 569 u8 *ptxb; 570 int entry = tpc->cur_tx % NUM_TX_DESC; 571 u32 len = length; 572 int ret; 573 574 #ifdef DEBUG_RTL8169_TX 575 int stime = currticks(); 576 printf ("%s\n", __FUNCTION__); 577 printf("sending %d bytes\n", len); 578 #endif 579 580 ioaddr = dev->iobase; 581 582 /* point to the current txb incase multiple tx_rings are used */ 583 ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE]; 584 memcpy(ptxb, (char *)packet, (int)length); 585 rtl_flush_buffer(ptxb, length); 586 587 while (len < ETH_ZLEN) 588 ptxb[len++] = '\0'; 589 590 tpc->TxDescArray[entry].buf_Haddr = 0; 591 tpc->TxDescArray[entry].buf_addr = cpu_to_le32(bus_to_phys(ptxb)); 592 if (entry != (NUM_TX_DESC - 1)) { 593 tpc->TxDescArray[entry].status = 594 cpu_to_le32((OWNbit | FSbit | LSbit) | 595 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 596 } else { 597 tpc->TxDescArray[entry].status = 598 cpu_to_le32((OWNbit | EORbit | FSbit | LSbit) | 599 ((len > ETH_ZLEN) ? len : ETH_ZLEN)); 600 } 601 rtl_flush_tx_desc(&tpc->TxDescArray[entry]); 602 RTL_W8(TxPoll, 0x40); /* set polling bit */ 603 604 tpc->cur_tx++; 605 to = currticks() + TX_TIMEOUT; 606 do { 607 rtl_inval_tx_desc(&tpc->TxDescArray[entry]); 608 } while ((le32_to_cpu(tpc->TxDescArray[entry].status) & OWNbit) 609 && (currticks() < to)); /* wait */ 610 611 if (currticks() >= to) { 612 #ifdef DEBUG_RTL8169_TX 613 puts("tx timeout/error\n"); 614 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 615 #endif 616 ret = 0; 617 } else { 618 #ifdef DEBUG_RTL8169_TX 619 puts("tx done\n"); 620 #endif 621 ret = length; 622 } 623 /* Delay to make net console (nc) work properly */ 624 udelay(20); 625 return ret; 626 } 627 628 static void rtl8169_set_rx_mode(struct eth_device *dev) 629 { 630 u32 mc_filter[2]; /* Multicast hash filter */ 631 int rx_mode; 632 u32 tmp = 0; 633 634 #ifdef DEBUG_RTL8169 635 printf ("%s\n", __FUNCTION__); 636 #endif 637 638 /* IFF_ALLMULTI */ 639 /* Too many to filter perfectly -- accept all multicasts. */ 640 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 641 mc_filter[1] = mc_filter[0] = 0xffffffff; 642 643 tmp = rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) & 644 rtl_chip_info[tpc->chipset].RxConfigMask); 645 646 RTL_W32(RxConfig, tmp); 647 RTL_W32(MAR0 + 0, mc_filter[0]); 648 RTL_W32(MAR0 + 4, mc_filter[1]); 649 } 650 651 static void rtl8169_hw_start(struct eth_device *dev) 652 { 653 u32 i; 654 655 #ifdef DEBUG_RTL8169 656 int stime = currticks(); 657 printf ("%s\n", __FUNCTION__); 658 #endif 659 660 #if 0 661 /* Soft reset the chip. */ 662 RTL_W8(ChipCmd, CmdReset); 663 664 /* Check that the chip has finished the reset. */ 665 for (i = 1000; i > 0; i--) { 666 if ((RTL_R8(ChipCmd) & CmdReset) == 0) 667 break; 668 else 669 udelay(10); 670 } 671 #endif 672 673 RTL_W8(Cfg9346, Cfg9346_Unlock); 674 675 /* RTL-8169sb/8110sb or previous version */ 676 if (tpc->chipset <= 5) 677 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 678 679 RTL_W8(EarlyTxThres, EarlyTxThld); 680 681 /* For gigabit rtl8169 */ 682 RTL_W16(RxMaxSize, RxPacketMaxSize); 683 684 /* Set Rx Config register */ 685 i = rtl8169_rx_config | (RTL_R32(RxConfig) & 686 rtl_chip_info[tpc->chipset].RxConfigMask); 687 RTL_W32(RxConfig, i); 688 689 /* Set DMA burst size and Interframe Gap Time */ 690 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | 691 (InterFrameGap << TxInterFrameGapShift)); 692 693 694 tpc->cur_rx = 0; 695 696 RTL_W32(TxDescStartAddrLow, bus_to_phys(tpc->TxDescArray)); 697 RTL_W32(TxDescStartAddrHigh, (unsigned long)0); 698 RTL_W32(RxDescStartAddrLow, bus_to_phys(tpc->RxDescArray)); 699 RTL_W32(RxDescStartAddrHigh, (unsigned long)0); 700 701 /* RTL-8169sc/8110sc or later version */ 702 if (tpc->chipset > 5) 703 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); 704 705 RTL_W8(Cfg9346, Cfg9346_Lock); 706 udelay(10); 707 708 RTL_W32(RxMissed, 0); 709 710 rtl8169_set_rx_mode(dev); 711 712 /* no early-rx interrupts */ 713 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); 714 715 #ifdef DEBUG_RTL8169 716 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 717 #endif 718 } 719 720 static void rtl8169_init_ring(struct eth_device *dev) 721 { 722 int i; 723 724 #ifdef DEBUG_RTL8169 725 int stime = currticks(); 726 printf ("%s\n", __FUNCTION__); 727 #endif 728 729 tpc->cur_rx = 0; 730 tpc->cur_tx = 0; 731 tpc->dirty_tx = 0; 732 memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc)); 733 memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc)); 734 735 for (i = 0; i < NUM_TX_DESC; i++) { 736 tpc->Tx_skbuff[i] = &txb[i]; 737 } 738 739 for (i = 0; i < NUM_RX_DESC; i++) { 740 if (i == (NUM_RX_DESC - 1)) 741 tpc->RxDescArray[i].status = 742 cpu_to_le32((OWNbit | EORbit) + RX_BUF_SIZE); 743 else 744 tpc->RxDescArray[i].status = 745 cpu_to_le32(OWNbit + RX_BUF_SIZE); 746 747 tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE]; 748 tpc->RxDescArray[i].buf_addr = 749 cpu_to_le32(bus_to_phys(tpc->RxBufferRing[i])); 750 rtl_flush_rx_desc(&tpc->RxDescArray[i]); 751 } 752 753 #ifdef DEBUG_RTL8169 754 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 755 #endif 756 } 757 758 /************************************************************************** 759 RESET - Finish setting up the ethernet interface 760 ***************************************************************************/ 761 static int rtl_reset(struct eth_device *dev, bd_t *bis) 762 { 763 int i; 764 765 #ifdef DEBUG_RTL8169 766 int stime = currticks(); 767 printf ("%s\n", __FUNCTION__); 768 #endif 769 770 rtl8169_init_ring(dev); 771 rtl8169_hw_start(dev); 772 /* Construct a perfect filter frame with the mac address as first match 773 * and broadcast for all others */ 774 for (i = 0; i < 192; i++) 775 txb[i] = 0xFF; 776 777 txb[0] = dev->enetaddr[0]; 778 txb[1] = dev->enetaddr[1]; 779 txb[2] = dev->enetaddr[2]; 780 txb[3] = dev->enetaddr[3]; 781 txb[4] = dev->enetaddr[4]; 782 txb[5] = dev->enetaddr[5]; 783 784 #ifdef DEBUG_RTL8169 785 printf("%s elapsed time : %lu\n", __func__, currticks()-stime); 786 #endif 787 return 0; 788 } 789 790 /************************************************************************** 791 HALT - Turn off ethernet interface 792 ***************************************************************************/ 793 static void rtl_halt(struct eth_device *dev) 794 { 795 int i; 796 797 #ifdef DEBUG_RTL8169 798 printf ("%s\n", __FUNCTION__); 799 #endif 800 801 ioaddr = dev->iobase; 802 803 /* Stop the chip's Tx and Rx DMA processes. */ 804 RTL_W8(ChipCmd, 0x00); 805 806 /* Disable interrupts by clearing the interrupt mask. */ 807 RTL_W16(IntrMask, 0x0000); 808 809 RTL_W32(RxMissed, 0); 810 811 for (i = 0; i < NUM_RX_DESC; i++) { 812 tpc->RxBufferRing[i] = NULL; 813 } 814 } 815 816 /************************************************************************** 817 INIT - Look for an adapter, this routine's visible to the outside 818 ***************************************************************************/ 819 820 #define board_found 1 821 #define valid_link 0 822 static int rtl_init(struct eth_device *dev, bd_t *bis) 823 { 824 static int board_idx = -1; 825 int i, rc; 826 int option = -1, Cap10_100 = 0, Cap1000 = 0; 827 828 #ifdef DEBUG_RTL8169 829 printf ("%s\n", __FUNCTION__); 830 #endif 831 832 ioaddr = dev->iobase; 833 834 board_idx++; 835 836 /* point to private storage */ 837 tpc = &tpx; 838 839 rc = rtl8169_init_board(dev); 840 if (rc) 841 return rc; 842 843 /* Get MAC address. FIXME: read EEPROM */ 844 for (i = 0; i < MAC_ADDR_LEN; i++) 845 dev->enetaddr[i] = RTL_R8(MAC0 + i); 846 847 #ifdef DEBUG_RTL8169 848 printf("chipset = %d\n", tpc->chipset); 849 printf("MAC Address"); 850 for (i = 0; i < MAC_ADDR_LEN; i++) 851 printf(":%02x", dev->enetaddr[i]); 852 putc('\n'); 853 #endif 854 855 #ifdef DEBUG_RTL8169 856 /* Print out some hardware info */ 857 printf("%s: at ioaddr 0x%lx\n", dev->name, ioaddr); 858 #endif 859 860 /* if TBI is not endbled */ 861 if (!(RTL_R8(PHYstatus) & TBI_Enable)) { 862 int val = mdio_read(PHY_AUTO_NEGO_REG); 863 864 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx]; 865 /* Force RTL8169 in 10/100/1000 Full/Half mode. */ 866 if (option > 0) { 867 #ifdef DEBUG_RTL8169 868 printf("%s: Force-mode Enabled.\n", dev->name); 869 #endif 870 Cap10_100 = 0, Cap1000 = 0; 871 switch (option) { 872 case _10_Half: 873 Cap10_100 = PHY_Cap_10_Half; 874 Cap1000 = PHY_Cap_Null; 875 break; 876 case _10_Full: 877 Cap10_100 = PHY_Cap_10_Full; 878 Cap1000 = PHY_Cap_Null; 879 break; 880 case _100_Half: 881 Cap10_100 = PHY_Cap_100_Half; 882 Cap1000 = PHY_Cap_Null; 883 break; 884 case _100_Full: 885 Cap10_100 = PHY_Cap_100_Full; 886 Cap1000 = PHY_Cap_Null; 887 break; 888 case _1000_Full: 889 Cap10_100 = PHY_Cap_Null; 890 Cap1000 = PHY_Cap_1000_Full; 891 break; 892 default: 893 break; 894 } 895 mdio_write(PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0x1F)); /* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 896 mdio_write(PHY_1000_CTRL_REG, Cap1000); 897 } else { 898 #ifdef DEBUG_RTL8169 899 printf("%s: Auto-negotiation Enabled.\n", 900 dev->name); 901 #endif 902 /* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */ 903 mdio_write(PHY_AUTO_NEGO_REG, 904 PHY_Cap_10_Half | PHY_Cap_10_Full | 905 PHY_Cap_100_Half | PHY_Cap_100_Full | 906 (val & 0x1F)); 907 908 /* enable 1000 Full Mode */ 909 mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full); 910 911 } 912 913 /* Enable auto-negotiation and restart auto-nigotiation */ 914 mdio_write(PHY_CTRL_REG, 915 PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego); 916 udelay(100); 917 918 /* wait for auto-negotiation process */ 919 for (i = 10000; i > 0; i--) { 920 /* check if auto-negotiation complete */ 921 if (mdio_read(PHY_STAT_REG) & PHY_Auto_Nego_Comp) { 922 udelay(100); 923 option = RTL_R8(PHYstatus); 924 if (option & _1000bpsF) { 925 #ifdef DEBUG_RTL8169 926 printf("%s: 1000Mbps Full-duplex operation.\n", 927 dev->name); 928 #endif 929 } else { 930 #ifdef DEBUG_RTL8169 931 printf("%s: %sMbps %s-duplex operation.\n", 932 dev->name, 933 (option & _100bps) ? "100" : 934 "10", 935 (option & FullDup) ? "Full" : 936 "Half"); 937 #endif 938 } 939 break; 940 } else { 941 udelay(100); 942 } 943 } /* end for-loop to wait for auto-negotiation process */ 944 945 } else { 946 udelay(100); 947 #ifdef DEBUG_RTL8169 948 printf 949 ("%s: 1000Mbps Full-duplex operation, TBI Link %s!\n", 950 dev->name, 951 (RTL_R32(TBICSR) & TBILinkOK) ? "OK" : "Failed"); 952 #endif 953 } 954 955 956 tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC); 957 if (!tpc->RxDescArray) 958 return -ENOMEM; 959 960 tpc->TxDescArray = rtl_alloc_descs(NUM_TX_DESC); 961 if (!tpc->TxDescArray) 962 return -ENOMEM; 963 964 return 0; 965 } 966 967 int rtl8169_initialize(bd_t *bis) 968 { 969 pci_dev_t devno; 970 int card_number = 0; 971 struct eth_device *dev; 972 u32 iobase; 973 int idx=0; 974 975 while(1){ 976 unsigned int region; 977 u16 device; 978 int err; 979 980 /* Find RTL8169 */ 981 if ((devno = pci_find_devices(supported, idx++)) < 0) 982 break; 983 984 pci_read_config_word(devno, PCI_DEVICE_ID, &device); 985 switch (device) { 986 case 0x8168: 987 region = 2; 988 break; 989 990 default: 991 region = 1; 992 break; 993 } 994 995 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase); 996 iobase &= ~0xf; 997 998 debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase); 999 1000 dev = (struct eth_device *)malloc(sizeof *dev); 1001 if (!dev) { 1002 printf("Can not allocate memory of rtl8169\n"); 1003 break; 1004 } 1005 1006 memset(dev, 0, sizeof(*dev)); 1007 sprintf (dev->name, "RTL8169#%d", card_number); 1008 1009 dev->priv = (void *)(unsigned long)devno; 1010 dev->iobase = (int)pci_mem_to_phys(devno, iobase); 1011 1012 dev->init = rtl_reset; 1013 dev->halt = rtl_halt; 1014 dev->send = rtl_send; 1015 dev->recv = rtl_recv; 1016 1017 err = rtl_init(dev, bis); 1018 if (err < 0) { 1019 printf(pr_fmt("failed to initialize card: %d\n"), err); 1020 free(dev); 1021 continue; 1022 } 1023 1024 eth_register (dev); 1025 1026 card_number++; 1027 } 1028 return card_number; 1029 } 1030