xref: /openbmc/u-boot/drivers/net/rtl8139.c (revision a6ac775b)
1 /*
2  * rtl8139.c : U-Boot driver for the RealTek RTL8139
3  *
4  * Masami Komiya (mkomiya@sonare.it)
5  *
6  * Most part is taken from rtl8139.c of etherboot
7  *
8  */
9 
10 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset
11 
12   ported from the linux driver written by Donald Becker
13   by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
14 
15   This software may be used and distributed according to the terms
16   of the GNU Public License, incorporated herein by reference.
17 
18   changes to the original driver:
19   - removed support for interrupts, switching to polling mode (yuck!)
20   - removed support for the 8129 chip (external MII)
21 
22 */
23 
24 /*********************************************************************/
25 /* Revision History						     */
26 /*********************************************************************/
27 
28 /*
29   28 Dec 2002	ken_yap@users.sourceforge.net (Ken Yap)
30      Put in virt_to_bus calls to allow Etherboot relocation.
31 
32   06 Apr 2001	ken_yap@users.sourceforge.net (Ken Yap)
33      Following email from Hyun-Joon Cha, added a disable routine, otherwise
34      NIC remains live and can crash the kernel later.
35 
36   4 Feb 2000	espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
37      Shuffled things around, removed the leftovers from the 8129 support
38      that was in the Linux driver and added a bit more 8139 definitions.
39      Moved the 8K receive buffer to a fixed, available address outside the
40      0x98000-0x9ffff range.  This is a bit of a hack, but currently the only
41      way to make room for the Etherboot features that need substantial amounts
42      of code like the ANSI console support.  Currently the buffer is just below
43      0x10000, so this even conforms to the tagged boot image specification,
44      which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000.  My
45      interpretation of this "reserved" is that Etherboot may do whatever it
46      likes, as long as its environment is kept intact (like the BIOS
47      variables).  Hopefully fixed rtl_poll() once and for all.	The symptoms
48      were that if Etherboot was left at the boot menu for several minutes, the
49      first eth_poll failed.  Seems like I am the only person who does this.
50      First of all I fixed the debugging code and then set out for a long bug
51      hunting session.  It took me about a week full time work - poking around
52      various places in the driver, reading Don Becker's and Jeff Garzik's Linux
53      driver and even the FreeBSD driver (what a piece of crap!) - and
54      eventually spotted the nasty thing: the transmit routine was acknowledging
55      each and every interrupt pending, including the RxOverrun and RxFIFIOver
56      interrupts.  This confused the RTL8139 thoroughly.	 It destroyed the
57      Rx ring contents by dumping the 2K FIFO contents right where we wanted to
58      get the next packet.  Oh well, what fun.
59 
60   18 Jan 2000	mdc@thinguin.org (Marty Connor)
61      Drastically simplified error handling.  Basically, if any error
62      in transmission or reception occurs, the card is reset.
63      Also, pointed all transmit descriptors to the same buffer to
64      save buffer space.	 This should decrease driver size and avoid
65      corruption because of exceeding 32K during runtime.
66 
67   28 Jul 1999	(Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
68      rtl_poll was quite broken: it used the RxOK interrupt flag instead
69      of the RxBufferEmpty flag which often resulted in very bad
70      transmission performace - below 1kBytes/s.
71 
72 */
73 
74 #include <common.h>
75 #include <malloc.h>
76 #include <net.h>
77 #include <netdev.h>
78 #include <asm/io.h>
79 #include <pci.h>
80 
81 #define RTL_TIMEOUT	100000
82 
83 /* PCI Tuning Parameters
84    Threshold is bytes transferred to chip before transmission starts. */
85 #define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */
86 #define RX_FIFO_THRESH	4	/* Rx buffer level before first PCI xfer.  */
87 #define RX_DMA_BURST	4	/* Maximum PCI burst, '4' is 256 bytes */
88 #define TX_DMA_BURST	4	/* Calculate as 16<<val. */
89 #define NUM_TX_DESC	4	/* Number of Tx descriptor registers. */
90 #define TX_BUF_SIZE	ETH_FRAME_LEN	/* FCS is added by the chip */
91 #define RX_BUF_LEN_IDX 0	/* 0, 1, 2 is allowed - 8,16,32K rx buffer */
92 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
93 
94 #define DEBUG_TX	0	/* set to 1 to enable debug code */
95 #define DEBUG_RX	0	/* set to 1 to enable debug code */
96 
97 #define bus_to_phys(a)	pci_mem_to_phys((pci_dev_t)dev->priv, a)
98 #define phys_to_bus(a)	pci_phys_to_mem((pci_dev_t)dev->priv, a)
99 
100 /* Symbolic offsets to registers. */
101 enum RTL8139_registers {
102 	MAC0=0,			/* Ethernet hardware address. */
103 	MAR0=8,			/* Multicast filter. */
104 	TxStatus0=0x10,		/* Transmit status (four 32bit registers). */
105 	TxAddr0=0x20,		/* Tx descriptors (also four 32bit). */
106 	RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
107 	ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
108 	IntrMask=0x3C, IntrStatus=0x3E,
109 	TxConfig=0x40, RxConfig=0x44,
110 	Timer=0x48,		/* general-purpose counter. */
111 	RxMissed=0x4C,		/* 24 bits valid, write clears. */
112 	Cfg9346=0x50, Config0=0x51, Config1=0x52,
113 	TimerIntrReg=0x54,	/* intr if gp counter reaches this value */
114 	MediaStatus=0x58,
115 	Config3=0x59,
116 	MultiIntr=0x5C,
117 	RevisionID=0x5E,	/* revision of the RTL8139 chip */
118 	TxSummary=0x60,
119 	MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
120 	NWayExpansion=0x6A,
121 	DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
122 	NWayTestReg=0x70,
123 	RxCnt=0x72,		/* packet received counter */
124 	CSCR=0x74,		/* chip status and configuration register */
125 	PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80,	/* undocumented */
126 	/* from 0x84 onwards are a number of power management/wakeup frame
127 	 * definitions we will probably never need to know about.  */
128 };
129 
130 enum ChipCmdBits {
131 	CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
132 
133 /* Interrupt register bits, using my own meaningful names. */
134 enum IntrStatusBits {
135 	PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
136 	RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
137 	TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
138 };
139 enum TxStatusBits {
140 	TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
141 	TxOutOfWindow=0x20000000, TxAborted=0x40000000,
142 	TxCarrierLost=0x80000000,
143 };
144 enum RxStatusBits {
145 	RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
146 	RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
147 	RxBadAlign=0x0002, RxStatusOK=0x0001,
148 };
149 
150 enum MediaStatusBits {
151 	MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
152 	MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
153 };
154 
155 enum MIIBMCRBits {
156 	BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
157 	BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
158 };
159 
160 enum CSCRBits {
161 	CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
162 	CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
163 	CSCR_LinkDownCmd=0x0f3c0,
164 };
165 
166 /* Bits in RxConfig. */
167 enum rx_mode_bits {
168 	RxCfgWrap=0x80,
169 	AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
170 	AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
171 };
172 
173 static int ioaddr;
174 static unsigned int cur_rx,cur_tx;
175 
176 /* The RTL8139 can only transmit from a contiguous, aligned memory block.  */
177 static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
178 static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
179 
180 static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
181 static int read_eeprom(int location, int addr_len);
182 static void rtl_reset(struct eth_device *dev);
183 static int rtl_transmit(struct eth_device *dev, void *packet, int length);
184 static int rtl_poll(struct eth_device *dev);
185 static void rtl_disable(struct eth_device *dev);
186 static int rtl_bcast_addr(struct eth_device *dev, const u8 *bcast_mac, int join)
187 {
188 	return (0);
189 }
190 
191 static struct pci_device_id supported[] = {
192        {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
193        {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
194        {}
195 };
196 
197 int rtl8139_initialize(bd_t *bis)
198 {
199 	pci_dev_t devno;
200 	int card_number = 0;
201 	struct eth_device *dev;
202 	u32 iobase;
203 	int idx=0;
204 
205 	while(1){
206 		/* Find RTL8139 */
207 		if ((devno = pci_find_devices(supported, idx++)) < 0)
208 			break;
209 
210 		pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
211 		iobase &= ~0xf;
212 
213 		debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
214 
215 		dev = (struct eth_device *)malloc(sizeof *dev);
216 		if (!dev) {
217 			printf("Can not allocate memory of rtl8139\n");
218 			break;
219 		}
220 		memset(dev, 0, sizeof(*dev));
221 
222 		sprintf (dev->name, "RTL8139#%d", card_number);
223 
224 		dev->priv = (void *) devno;
225 		dev->iobase = (int)bus_to_phys(iobase);
226 		dev->init = rtl8139_probe;
227 		dev->halt = rtl_disable;
228 		dev->send = rtl_transmit;
229 		dev->recv = rtl_poll;
230 		dev->mcast = rtl_bcast_addr;
231 
232 		eth_register (dev);
233 
234 		card_number++;
235 
236 		pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
237 
238 		udelay (10 * 1000);
239 	}
240 
241 	return card_number;
242 }
243 
244 static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
245 {
246 	int i;
247 	int addr_len;
248 	unsigned short *ap = (unsigned short *)dev->enetaddr;
249 
250 	ioaddr = dev->iobase;
251 
252 	/* Bring the chip out of low-power mode. */
253 	outb(0x00, ioaddr + Config1);
254 
255 	addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
256 	for (i = 0; i < 3; i++)
257 		*ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
258 
259 	rtl_reset(dev);
260 
261 	if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
262 		printf("Cable not connected or other link failure\n");
263 		return -1 ;
264 	}
265 
266 	return 0;
267 }
268 
269 /* Serial EEPROM section. */
270 
271 /*  EEPROM_Ctrl bits. */
272 #define EE_SHIFT_CLK	0x04	/* EEPROM shift clock. */
273 #define EE_CS		0x08	/* EEPROM chip select. */
274 #define EE_DATA_WRITE	0x02	/* EEPROM chip data in. */
275 #define EE_WRITE_0	0x00
276 #define EE_WRITE_1	0x02
277 #define EE_DATA_READ	0x01	/* EEPROM chip data out. */
278 #define EE_ENB		(0x80 | EE_CS)
279 
280 /*
281 	Delay between EEPROM clock transitions.
282 	No extra delay is needed with 33MHz PCI, but 66MHz may change this.
283 */
284 
285 #define eeprom_delay()	inl(ee_addr)
286 
287 /* The EEPROM commands include the alway-set leading bit. */
288 #define EE_WRITE_CMD	(5)
289 #define EE_READ_CMD	(6)
290 #define EE_ERASE_CMD	(7)
291 
292 static int read_eeprom(int location, int addr_len)
293 {
294 	int i;
295 	unsigned int retval = 0;
296 	long ee_addr = ioaddr + Cfg9346;
297 	int read_cmd = location | (EE_READ_CMD << addr_len);
298 
299 	outb(EE_ENB & ~EE_CS, ee_addr);
300 	outb(EE_ENB, ee_addr);
301 	eeprom_delay();
302 
303 	/* Shift the read command bits out. */
304 	for (i = 4 + addr_len; i >= 0; i--) {
305 		int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
306 		outb(EE_ENB | dataval, ee_addr);
307 		eeprom_delay();
308 		outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
309 		eeprom_delay();
310 	}
311 	outb(EE_ENB, ee_addr);
312 	eeprom_delay();
313 
314 	for (i = 16; i > 0; i--) {
315 		outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
316 		eeprom_delay();
317 		retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
318 		outb(EE_ENB, ee_addr);
319 		eeprom_delay();
320 	}
321 
322 	/* Terminate the EEPROM access. */
323 	outb(~EE_CS, ee_addr);
324 	eeprom_delay();
325 	return retval;
326 }
327 
328 static const unsigned int rtl8139_rx_config =
329 	(RX_BUF_LEN_IDX << 11) |
330 	(RX_FIFO_THRESH << 13) |
331 	(RX_DMA_BURST << 8);
332 
333 static void set_rx_mode(struct eth_device *dev) {
334 	unsigned int mc_filter[2];
335 	int rx_mode;
336 	/* !IFF_PROMISC */
337 	rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
338 	mc_filter[1] = mc_filter[0] = 0xffffffff;
339 
340 	outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
341 
342 	outl(mc_filter[0], ioaddr + MAR0 + 0);
343 	outl(mc_filter[1], ioaddr + MAR0 + 4);
344 }
345 
346 static void rtl_reset(struct eth_device *dev)
347 {
348 	int i;
349 
350 	outb(CmdReset, ioaddr + ChipCmd);
351 
352 	cur_rx = 0;
353 	cur_tx = 0;
354 
355 	/* Give the chip 10ms to finish the reset. */
356 	for (i=0; i<100; ++i){
357 		if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
358 		udelay (100); /* wait 100us */
359 	}
360 
361 
362 	for (i = 0; i < ETH_ALEN; i++)
363 		outb(dev->enetaddr[i], ioaddr + MAC0 + i);
364 
365 	/* Must enable Tx/Rx before setting transfer thresholds! */
366 	outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
367 	outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
368 		ioaddr + RxConfig);		/* accept no frames yet!  */
369 	outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
370 
371 	/* The Linux driver changes Config1 here to use a different LED pattern
372 	 * for half duplex or full/autodetect duplex (for full/autodetect, the
373 	 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
374 	 * TX/RX, Link100, Link10).  This is messy, because it doesn't match
375 	 * the inscription on the mounting bracket.  It should not be changed
376 	 * from the configuration EEPROM default, because the card manufacturer
377 	 * should have set that to match the card.  */
378 
379 	debug_cond(DEBUG_RX,
380 		"rx ring address is %lX\n",(unsigned long)rx_ring);
381 	flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
382 	outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
383 
384 	/* If we add multicast support, the MAR0 register would have to be
385 	 * initialized to 0xffffffffffffffff (two 32 bit accesses).  Etherboot
386 	 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast.	*/
387 
388 	outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
389 
390 	outl(rtl8139_rx_config, ioaddr + RxConfig);
391 
392 	/* Start the chip's Tx and Rx process. */
393 	outl(0, ioaddr + RxMissed);
394 
395 	/* set_rx_mode */
396 	set_rx_mode(dev);
397 
398 	/* Disable all known interrupts by setting the interrupt mask. */
399 	outw(0, ioaddr + IntrMask);
400 }
401 
402 static int rtl_transmit(struct eth_device *dev, void *packet, int length)
403 {
404 	unsigned int status;
405 	unsigned long txstatus;
406 	unsigned int len = length;
407 	int i = 0;
408 
409 	ioaddr = dev->iobase;
410 
411 	memcpy((char *)tx_buffer, (char *)packet, (int)length);
412 
413 	debug_cond(DEBUG_TX, "sending %d bytes\n", len);
414 
415 	/* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
416 	 * bytes are sent automatically for the FCS, totalling to 64 bytes). */
417 	while (len < ETH_ZLEN) {
418 		tx_buffer[len++] = '\0';
419 	}
420 
421 	flush_cache((unsigned long)tx_buffer, length);
422 	outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
423 	outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
424 		ioaddr + TxStatus0 + cur_tx*4);
425 
426 	do {
427 		status = inw(ioaddr + IntrStatus);
428 		/* Only acknlowledge interrupt sources we can properly handle
429 		 * here - the RxOverflow/RxFIFOOver MUST be handled in the
430 		 * rtl_poll() function.	 */
431 		outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
432 		if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
433 		udelay(10);
434 	} while (i++ < RTL_TIMEOUT);
435 
436 	txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
437 
438 	if (status & TxOK) {
439 		cur_tx = (cur_tx + 1) % NUM_TX_DESC;
440 
441 		debug_cond(DEBUG_TX,
442 			"tx done, status %hX txstatus %lX\n",
443 			status, txstatus);
444 
445 		return length;
446 	} else {
447 
448 		debug_cond(DEBUG_TX,
449 			"tx timeout/error (%d usecs), status %hX txstatus %lX\n",
450 			10*i, status, txstatus);
451 
452 		rtl_reset(dev);
453 
454 		return 0;
455 	}
456 }
457 
458 static int rtl_poll(struct eth_device *dev)
459 {
460 	unsigned int status;
461 	unsigned int ring_offs;
462 	unsigned int rx_size, rx_status;
463 	int length=0;
464 
465 	ioaddr = dev->iobase;
466 
467 	if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
468 		return 0;
469 	}
470 
471 	status = inw(ioaddr + IntrStatus);
472 	/* See below for the rest of the interrupt acknowledges.  */
473 	outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
474 
475 	debug_cond(DEBUG_RX, "rtl_poll: int %hX ", status);
476 
477 	ring_offs = cur_rx % RX_BUF_LEN;
478 	/* ring_offs is guaranteed being 4-byte aligned */
479 	rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
480 	rx_size = rx_status >> 16;
481 	rx_status &= 0xffff;
482 
483 	if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
484 	    (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
485 		printf("rx error %hX\n", rx_status);
486 		rtl_reset(dev); /* this clears all interrupts still pending */
487 		return 0;
488 	}
489 
490 	/* Received a good packet */
491 	length = rx_size - 4;	/* no one cares about the FCS */
492 	if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
493 		int semi_count = RX_BUF_LEN - ring_offs - 4;
494 		unsigned char rxdata[RX_BUF_LEN];
495 
496 		memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
497 		memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
498 
499 		net_process_received_packet(rxdata, length);
500 		debug_cond(DEBUG_RX, "rx packet %d+%d bytes",
501 			semi_count, rx_size-4-semi_count);
502 	} else {
503 		net_process_received_packet(rx_ring + ring_offs + 4, length);
504 		debug_cond(DEBUG_RX, "rx packet %d bytes", rx_size-4);
505 	}
506 	flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
507 
508 	cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
509 	outw(cur_rx - 16, ioaddr + RxBufPtr);
510 	/* See RTL8139 Programming Guide V0.1 for the official handling of
511 	 * Rx overflow situations.  The document itself contains basically no
512 	 * usable information, except for a few exception handling rules.  */
513 	outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
514 	return length;
515 }
516 
517 static void rtl_disable(struct eth_device *dev)
518 {
519 	int i;
520 
521 	ioaddr = dev->iobase;
522 
523 	/* reset the chip */
524 	outb(CmdReset, ioaddr + ChipCmd);
525 
526 	/* Give the chip 10ms to finish the reset. */
527 	for (i=0; i<100; ++i){
528 		if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
529 		udelay (100); /* wait 100us */
530 	}
531 }
532