1 /* 2 * rtl8139.c : U-Boot driver for the RealTek RTL8139 3 * 4 * Masami Komiya (mkomiya@sonare.it) 5 * 6 * Most part is taken from rtl8139.c of etherboot 7 * 8 */ 9 10 /* rtl8139.c - etherboot driver for the Realtek 8139 chipset 11 12 ported from the linux driver written by Donald Becker 13 by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999 14 15 This software may be used and distributed according to the terms 16 of the GNU Public License, incorporated herein by reference. 17 18 changes to the original driver: 19 - removed support for interrupts, switching to polling mode (yuck!) 20 - removed support for the 8129 chip (external MII) 21 22 */ 23 24 /*********************************************************************/ 25 /* Revision History */ 26 /*********************************************************************/ 27 28 /* 29 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap) 30 Put in virt_to_bus calls to allow Etherboot relocation. 31 32 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap) 33 Following email from Hyun-Joon Cha, added a disable routine, otherwise 34 NIC remains live and can crash the kernel later. 35 36 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub) 37 Shuffled things around, removed the leftovers from the 8129 support 38 that was in the Linux driver and added a bit more 8139 definitions. 39 Moved the 8K receive buffer to a fixed, available address outside the 40 0x98000-0x9ffff range. This is a bit of a hack, but currently the only 41 way to make room for the Etherboot features that need substantial amounts 42 of code like the ANSI console support. Currently the buffer is just below 43 0x10000, so this even conforms to the tagged boot image specification, 44 which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My 45 interpretation of this "reserved" is that Etherboot may do whatever it 46 likes, as long as its environment is kept intact (like the BIOS 47 variables). Hopefully fixed rtl_poll() once and for all. The symptoms 48 were that if Etherboot was left at the boot menu for several minutes, the 49 first eth_poll failed. Seems like I am the only person who does this. 50 First of all I fixed the debugging code and then set out for a long bug 51 hunting session. It took me about a week full time work - poking around 52 various places in the driver, reading Don Becker's and Jeff Garzik's Linux 53 driver and even the FreeBSD driver (what a piece of crap!) - and 54 eventually spotted the nasty thing: the transmit routine was acknowledging 55 each and every interrupt pending, including the RxOverrun and RxFIFIOver 56 interrupts. This confused the RTL8139 thoroughly. It destroyed the 57 Rx ring contents by dumping the 2K FIFO contents right where we wanted to 58 get the next packet. Oh well, what fun. 59 60 18 Jan 2000 mdc@thinguin.org (Marty Connor) 61 Drastically simplified error handling. Basically, if any error 62 in transmission or reception occurs, the card is reset. 63 Also, pointed all transmit descriptors to the same buffer to 64 save buffer space. This should decrease driver size and avoid 65 corruption because of exceeding 32K during runtime. 66 67 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de) 68 rtl_poll was quite broken: it used the RxOK interrupt flag instead 69 of the RxBufferEmpty flag which often resulted in very bad 70 transmission performace - below 1kBytes/s. 71 72 */ 73 74 #include <common.h> 75 #include <malloc.h> 76 #include <net.h> 77 #include <asm/io.h> 78 #include <pci.h> 79 80 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ 81 defined(CONFIG_RTL8139) 82 83 #define TICKS_PER_SEC CFG_HZ 84 #define TICKS_PER_MS (TICKS_PER_SEC/1000) 85 86 #define RTL_TIMEOUT (1*TICKS_PER_SEC) 87 88 #define ETH_FRAME_LEN 1514 89 #define ETH_ALEN 6 90 #define ETH_ZLEN 60 91 92 /* PCI Tuning Parameters 93 Threshold is bytes transferred to chip before transmission starts. */ 94 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */ 95 #define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */ 96 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */ 97 #define TX_DMA_BURST 4 /* Calculate as 16<<val. */ 98 #define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */ 99 #define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */ 100 #define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */ 101 #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX) 102 103 #undef DEBUG_TX 104 #undef DEBUG_RX 105 106 #define currticks() get_timer(0) 107 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) 108 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 109 110 /* Symbolic offsets to registers. */ 111 enum RTL8139_registers { 112 MAC0=0, /* Ethernet hardware address. */ 113 MAR0=8, /* Multicast filter. */ 114 TxStatus0=0x10, /* Transmit status (four 32bit registers). */ 115 TxAddr0=0x20, /* Tx descriptors (also four 32bit). */ 116 RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36, 117 ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A, 118 IntrMask=0x3C, IntrStatus=0x3E, 119 TxConfig=0x40, RxConfig=0x44, 120 Timer=0x48, /* general-purpose counter. */ 121 RxMissed=0x4C, /* 24 bits valid, write clears. */ 122 Cfg9346=0x50, Config0=0x51, Config1=0x52, 123 TimerIntrReg=0x54, /* intr if gp counter reaches this value */ 124 MediaStatus=0x58, 125 Config3=0x59, 126 MultiIntr=0x5C, 127 RevisionID=0x5E, /* revision of the RTL8139 chip */ 128 TxSummary=0x60, 129 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68, 130 NWayExpansion=0x6A, 131 DisconnectCnt=0x6C, FalseCarrierCnt=0x6E, 132 NWayTestReg=0x70, 133 RxCnt=0x72, /* packet received counter */ 134 CSCR=0x74, /* chip status and configuration register */ 135 PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */ 136 /* from 0x84 onwards are a number of power management/wakeup frame 137 * definitions we will probably never need to know about. */ 138 }; 139 140 enum ChipCmdBits { 141 CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, }; 142 143 /* Interrupt register bits, using my own meaningful names. */ 144 enum IntrStatusBits { 145 PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000, 146 RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10, 147 TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01, 148 }; 149 enum TxStatusBits { 150 TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000, 151 TxOutOfWindow=0x20000000, TxAborted=0x40000000, 152 TxCarrierLost=0x80000000, 153 }; 154 enum RxStatusBits { 155 RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000, 156 RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004, 157 RxBadAlign=0x0002, RxStatusOK=0x0001, 158 }; 159 160 enum MediaStatusBits { 161 MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08, 162 MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01, 163 }; 164 165 enum MIIBMCRBits { 166 BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000, 167 BMCRRestartNWay=0x0200, BMCRDuplex=0x0100, 168 }; 169 170 enum CSCRBits { 171 CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800, 172 CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0, 173 CSCR_LinkDownCmd=0x0f3c0, 174 }; 175 176 /* Bits in RxConfig. */ 177 enum rx_mode_bits { 178 RxCfgWrap=0x80, 179 AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08, 180 AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01, 181 }; 182 183 static int ioaddr; 184 static unsigned int cur_rx,cur_tx; 185 186 /* The RTL8139 can only transmit from a contiguous, aligned memory block. */ 187 static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4))); 188 static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4))); 189 190 static int rtl8139_probe(struct eth_device *dev, bd_t *bis); 191 static int read_eeprom(int location, int addr_len); 192 static void rtl_reset(struct eth_device *dev); 193 static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length); 194 static int rtl_poll(struct eth_device *dev); 195 static void rtl_disable(struct eth_device *dev); 196 #ifdef CONFIG_MCAST_TFTP/* This driver already accepts all b/mcast */ 197 static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set) 198 { 199 return (0); 200 } 201 #endif 202 203 static struct pci_device_id supported[] = { 204 {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139}, 205 {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139}, 206 {} 207 }; 208 209 int rtl8139_initialize(bd_t *bis) 210 { 211 pci_dev_t devno; 212 int card_number = 0; 213 struct eth_device *dev; 214 u32 iobase; 215 int idx=0; 216 217 while(1){ 218 /* Find RTL8139 */ 219 if ((devno = pci_find_devices(supported, idx++)) < 0) 220 break; 221 222 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); 223 iobase &= ~0xf; 224 225 debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase); 226 227 dev = (struct eth_device *)malloc(sizeof *dev); 228 229 sprintf (dev->name, "RTL8139#%d", card_number); 230 231 dev->priv = (void *) devno; 232 dev->iobase = (int)bus_to_phys(iobase); 233 dev->init = rtl8139_probe; 234 dev->halt = rtl_disable; 235 dev->send = rtl_transmit; 236 dev->recv = rtl_poll; 237 #ifdef CONFIG_MCAST_TFTP 238 dev->mcast = rtl_bcast_addr; 239 #endif 240 241 eth_register (dev); 242 243 card_number++; 244 245 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20); 246 247 udelay (10 * 1000); 248 } 249 250 return card_number; 251 } 252 253 static int rtl8139_probe(struct eth_device *dev, bd_t *bis) 254 { 255 int i; 256 int speed10, fullduplex; 257 int addr_len; 258 unsigned short *ap = (unsigned short *)dev->enetaddr; 259 260 ioaddr = dev->iobase; 261 262 /* Bring the chip out of low-power mode. */ 263 outb(0x00, ioaddr + Config1); 264 265 addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6; 266 for (i = 0; i < 3; i++) 267 *ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len)); 268 269 speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10; 270 fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex; 271 272 rtl_reset(dev); 273 274 if (inb(ioaddr + MediaStatus) & MSRLinkFail) { 275 printf("Cable not connected or other link failure\n"); 276 return -1 ; 277 } 278 279 return 0; 280 } 281 282 /* Serial EEPROM section. */ 283 284 /* EEPROM_Ctrl bits. */ 285 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */ 286 #define EE_CS 0x08 /* EEPROM chip select. */ 287 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */ 288 #define EE_WRITE_0 0x00 289 #define EE_WRITE_1 0x02 290 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */ 291 #define EE_ENB (0x80 | EE_CS) 292 293 /* 294 Delay between EEPROM clock transitions. 295 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this. 296 */ 297 298 #define eeprom_delay() inl(ee_addr) 299 300 /* The EEPROM commands include the alway-set leading bit. */ 301 #define EE_WRITE_CMD (5) 302 #define EE_READ_CMD (6) 303 #define EE_ERASE_CMD (7) 304 305 static int read_eeprom(int location, int addr_len) 306 { 307 int i; 308 unsigned int retval = 0; 309 long ee_addr = ioaddr + Cfg9346; 310 int read_cmd = location | (EE_READ_CMD << addr_len); 311 312 outb(EE_ENB & ~EE_CS, ee_addr); 313 outb(EE_ENB, ee_addr); 314 eeprom_delay(); 315 316 /* Shift the read command bits out. */ 317 for (i = 4 + addr_len; i >= 0; i--) { 318 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 319 outb(EE_ENB | dataval, ee_addr); 320 eeprom_delay(); 321 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); 322 eeprom_delay(); 323 } 324 outb(EE_ENB, ee_addr); 325 eeprom_delay(); 326 327 for (i = 16; i > 0; i--) { 328 outb(EE_ENB | EE_SHIFT_CLK, ee_addr); 329 eeprom_delay(); 330 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0); 331 outb(EE_ENB, ee_addr); 332 eeprom_delay(); 333 } 334 335 /* Terminate the EEPROM access. */ 336 outb(~EE_CS, ee_addr); 337 eeprom_delay(); 338 return retval; 339 } 340 341 static const unsigned int rtl8139_rx_config = 342 (RX_BUF_LEN_IDX << 11) | 343 (RX_FIFO_THRESH << 13) | 344 (RX_DMA_BURST << 8); 345 346 static void set_rx_mode(struct eth_device *dev) { 347 unsigned int mc_filter[2]; 348 int rx_mode; 349 /* !IFF_PROMISC */ 350 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; 351 mc_filter[1] = mc_filter[0] = 0xffffffff; 352 353 outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig); 354 355 outl(mc_filter[0], ioaddr + MAR0 + 0); 356 outl(mc_filter[1], ioaddr + MAR0 + 4); 357 } 358 359 static void rtl_reset(struct eth_device *dev) 360 { 361 int i; 362 363 outb(CmdReset, ioaddr + ChipCmd); 364 365 cur_rx = 0; 366 cur_tx = 0; 367 368 /* Give the chip 10ms to finish the reset. */ 369 for (i=0; i<100; ++i){ 370 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; 371 udelay (100); /* wait 100us */ 372 } 373 374 375 for (i = 0; i < ETH_ALEN; i++) 376 outb(dev->enetaddr[i], ioaddr + MAC0 + i); 377 378 /* Must enable Tx/Rx before setting transfer thresholds! */ 379 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); 380 outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8), 381 ioaddr + RxConfig); /* accept no frames yet! */ 382 outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig); 383 384 /* The Linux driver changes Config1 here to use a different LED pattern 385 * for half duplex or full/autodetect duplex (for full/autodetect, the 386 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses 387 * TX/RX, Link100, Link10). This is messy, because it doesn't match 388 * the inscription on the mounting bracket. It should not be changed 389 * from the configuration EEPROM default, because the card manufacturer 390 * should have set that to match the card. */ 391 392 #ifdef DEBUG_RX 393 printf("rx ring address is %X\n",(unsigned long)rx_ring); 394 #endif 395 outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf); 396 397 /* If we add multicast support, the MAR0 register would have to be 398 * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot 399 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */ 400 401 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd); 402 403 outl(rtl8139_rx_config, ioaddr + RxConfig); 404 405 /* Start the chip's Tx and Rx process. */ 406 outl(0, ioaddr + RxMissed); 407 408 /* set_rx_mode */ 409 set_rx_mode(dev); 410 411 /* Disable all known interrupts by setting the interrupt mask. */ 412 outw(0, ioaddr + IntrMask); 413 } 414 415 static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length) 416 { 417 unsigned int status, to; 418 unsigned long txstatus; 419 unsigned int len = length; 420 421 ioaddr = dev->iobase; 422 423 memcpy((char *)tx_buffer, (char *)packet, (int)length); 424 425 #ifdef DEBUG_TX 426 printf("sending %d bytes\n", len); 427 #endif 428 429 /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4 430 * bytes are sent automatically for the FCS, totalling to 64 bytes). */ 431 while (len < ETH_ZLEN) { 432 tx_buffer[len++] = '\0'; 433 } 434 435 outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4); 436 outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len, 437 ioaddr + TxStatus0 + cur_tx*4); 438 439 to = currticks() + RTL_TIMEOUT; 440 441 do { 442 status = inw(ioaddr + IntrStatus); 443 /* Only acknlowledge interrupt sources we can properly handle 444 * here - the RxOverflow/RxFIFOOver MUST be handled in the 445 * rtl_poll() function. */ 446 outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus); 447 if ((status & (TxOK | TxErr | PCIErr)) != 0) break; 448 } while (currticks() < to); 449 450 txstatus = inl(ioaddr + TxStatus0 + cur_tx*4); 451 452 if (status & TxOK) { 453 cur_tx = (cur_tx + 1) % NUM_TX_DESC; 454 #ifdef DEBUG_TX 455 printf("tx done (%d ticks), status %hX txstatus %X\n", 456 to-currticks(), status, txstatus); 457 #endif 458 return length; 459 } else { 460 #ifdef DEBUG_TX 461 printf("tx timeout/error (%d ticks), status %hX txstatus %X\n", 462 currticks()-to, status, txstatus); 463 #endif 464 rtl_reset(dev); 465 466 return 0; 467 } 468 } 469 470 static int rtl_poll(struct eth_device *dev) 471 { 472 unsigned int status; 473 unsigned int ring_offs; 474 unsigned int rx_size, rx_status; 475 int length=0; 476 477 ioaddr = dev->iobase; 478 479 if (inb(ioaddr + ChipCmd) & RxBufEmpty) { 480 return 0; 481 } 482 483 status = inw(ioaddr + IntrStatus); 484 /* See below for the rest of the interrupt acknowledges. */ 485 outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); 486 487 #ifdef DEBUG_RX 488 printf("rtl_poll: int %hX ", status); 489 #endif 490 491 ring_offs = cur_rx % RX_BUF_LEN; 492 rx_status = *(unsigned int*)KSEG1ADDR((rx_ring + ring_offs)); 493 rx_size = rx_status >> 16; 494 rx_status &= 0xffff; 495 496 if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) || 497 (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) { 498 printf("rx error %hX\n", rx_status); 499 rtl_reset(dev); /* this clears all interrupts still pending */ 500 return 0; 501 } 502 503 /* Received a good packet */ 504 length = rx_size - 4; /* no one cares about the FCS */ 505 if (ring_offs+4+rx_size-4 > RX_BUF_LEN) { 506 int semi_count = RX_BUF_LEN - ring_offs - 4; 507 unsigned char rxdata[RX_BUF_LEN]; 508 509 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count); 510 memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count); 511 512 NetReceive(rxdata, length); 513 #ifdef DEBUG_RX 514 printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count); 515 #endif 516 } else { 517 NetReceive(rx_ring + ring_offs + 4, length); 518 #ifdef DEBUG_RX 519 printf("rx packet %d bytes", rx_size-4); 520 #endif 521 } 522 523 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3; 524 outw(cur_rx - 16, ioaddr + RxBufPtr); 525 /* See RTL8139 Programming Guide V0.1 for the official handling of 526 * Rx overflow situations. The document itself contains basically no 527 * usable information, except for a few exception handling rules. */ 528 outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus); 529 return length; 530 } 531 532 static void rtl_disable(struct eth_device *dev) 533 { 534 int i; 535 536 ioaddr = dev->iobase; 537 538 /* reset the chip */ 539 outb(CmdReset, ioaddr + ChipCmd); 540 541 /* Give the chip 10ms to finish the reset. */ 542 for (i=0; i<100; ++i){ 543 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break; 544 udelay (100); /* wait 100us */ 545 } 546 } 547 #endif 548