1 /* 2 * TI PHY drivers 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 * 6 */ 7 #include <common.h> 8 #include <phy.h> 9 #include <linux/compat.h> 10 #include <malloc.h> 11 12 #include <fdtdec.h> 13 #include <dm.h> 14 #include <dt-bindings/net/ti-dp83867.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 /* TI DP83867 */ 19 #define DP83867_DEVADDR 0x1f 20 21 #define MII_DP83867_PHYCTRL 0x10 22 #define MII_DP83867_MICR 0x12 23 #define MII_DP83867_CFG2 0x14 24 #define MII_DP83867_BISCR 0x16 25 #define DP83867_CTRL 0x1f 26 27 /* Extended Registers */ 28 #define DP83867_RGMIICTL 0x0032 29 #define DP83867_RGMIIDCTL 0x0086 30 31 #define DP83867_SW_RESET BIT(15) 32 #define DP83867_SW_RESTART BIT(14) 33 34 /* MICR Interrupt bits */ 35 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 36 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 37 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 38 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 39 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 40 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 41 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 42 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 43 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 44 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 45 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 46 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 47 48 /* RGMIICTL bits */ 49 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 50 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 51 52 /* PHY CTRL bits */ 53 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 54 #define DP83867_MDI_CROSSOVER 5 55 #define DP83867_MDI_CROSSOVER_AUTO 2 56 #define DP83867_MDI_CROSSOVER_MDIX 2 57 #define DP83867_PHYCTRL_SGMIIEN 0x0800 58 #define DP83867_PHYCTRL_RXFIFO_SHIFT 12 59 #define DP83867_PHYCTRL_TXFIFO_SHIFT 14 60 61 /* RGMIIDCTL bits */ 62 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 63 64 /* CFG2 bits */ 65 #define MII_DP83867_CFG2_SPEEDOPT_10EN 0x0040 66 #define MII_DP83867_CFG2_SGMII_AUTONEGEN 0x0080 67 #define MII_DP83867_CFG2_SPEEDOPT_ENH 0x0100 68 #define MII_DP83867_CFG2_SPEEDOPT_CNT 0x0800 69 #define MII_DP83867_CFG2_SPEEDOPT_INTLOW 0x2000 70 #define MII_DP83867_CFG2_MASK 0x003F 71 72 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ 73 #define MII_MMD_DATA 0x0e /* MMD Access Data Register */ 74 75 /* MMD Access Control register fields */ 76 #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ 77 #define MII_MMD_CTRL_ADDR 0x0000 /* Address */ 78 #define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ 79 #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ 80 #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ 81 82 /* User setting - can be taken from DTS */ 83 #define DEFAULT_RX_ID_DELAY DP83867_RGMIIDCTL_2_25_NS 84 #define DEFAULT_TX_ID_DELAY DP83867_RGMIIDCTL_2_75_NS 85 #define DEFAULT_FIFO_DEPTH DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 86 87 struct dp83867_private { 88 int rx_id_delay; 89 int tx_id_delay; 90 int fifo_depth; 91 }; 92 93 /** 94 * phy_read_mmd_indirect - reads data from the MMD registers 95 * @phydev: The PHY device bus 96 * @prtad: MMD Address 97 * @devad: MMD DEVAD 98 * @addr: PHY address on the MII bus 99 * 100 * Description: it reads data from the MMD registers (clause 22 to access to 101 * clause 45) of the specified phy address. 102 * To read these registers we have: 103 * 1) Write reg 13 // DEVAD 104 * 2) Write reg 14 // MMD Address 105 * 3) Write reg 13 // MMD Data Command for MMD DEVAD 106 * 3) Read reg 14 // Read MMD data 107 */ 108 int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, 109 int devad, int addr) 110 { 111 int value = -1; 112 113 /* Write the desired MMD Devad */ 114 phy_write(phydev, addr, MII_MMD_CTRL, devad); 115 116 /* Write the desired MMD register address */ 117 phy_write(phydev, addr, MII_MMD_DATA, prtad); 118 119 /* Select the Function : DATA with no post increment */ 120 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 121 122 /* Read the content of the MMD's selected register */ 123 value = phy_read(phydev, addr, MII_MMD_DATA); 124 return value; 125 } 126 127 /** 128 * phy_write_mmd_indirect - writes data to the MMD registers 129 * @phydev: The PHY device 130 * @prtad: MMD Address 131 * @devad: MMD DEVAD 132 * @addr: PHY address on the MII bus 133 * @data: data to write in the MMD register 134 * 135 * Description: Write data from the MMD registers of the specified 136 * phy address. 137 * To write these registers we have: 138 * 1) Write reg 13 // DEVAD 139 * 2) Write reg 14 // MMD Address 140 * 3) Write reg 13 // MMD Data Command for MMD DEVAD 141 * 3) Write reg 14 // Write MMD data 142 */ 143 void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, 144 int devad, int addr, u32 data) 145 { 146 /* Write the desired MMD Devad */ 147 phy_write(phydev, addr, MII_MMD_CTRL, devad); 148 149 /* Write the desired MMD register address */ 150 phy_write(phydev, addr, MII_MMD_DATA, prtad); 151 152 /* Select the Function : DATA with no post increment */ 153 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 154 155 /* Write the data into MMD's selected register */ 156 phy_write(phydev, addr, MII_MMD_DATA, data); 157 } 158 159 #if defined(CONFIG_DM_ETH) 160 /** 161 * dp83867_data_init - Convenience function for setting PHY specific data 162 * 163 * @phydev: the phy_device struct 164 */ 165 static int dp83867_of_init(struct phy_device *phydev) 166 { 167 struct dp83867_private *dp83867 = phydev->priv; 168 struct udevice *dev = phydev->dev; 169 170 dp83867->rx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, 171 "ti,rx-internal-delay", -1); 172 173 dp83867->tx_id_delay = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, 174 "ti,tx-internal-delay", -1); 175 176 dp83867->fifo_depth = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, 177 "ti,fifo-depth", -1); 178 179 return 0; 180 } 181 #else 182 static int dp83867_of_init(struct phy_device *phydev) 183 { 184 struct dp83867_private *dp83867 = phydev->priv; 185 186 dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY; 187 dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY; 188 dp83867->fifo_depth = DEFAULT_FIFO_DEPTH; 189 190 return 0; 191 } 192 #endif 193 194 static int dp83867_config(struct phy_device *phydev) 195 { 196 struct dp83867_private *dp83867; 197 unsigned int val, delay, cfg2; 198 int ret; 199 200 if (!phydev->priv) { 201 dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL); 202 if (!dp83867) 203 return -ENOMEM; 204 205 phydev->priv = dp83867; 206 ret = dp83867_of_init(phydev); 207 if (ret) 208 goto err_out; 209 } else { 210 dp83867 = (struct dp83867_private *)phydev->priv; 211 } 212 213 /* Restart the PHY. */ 214 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); 215 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, 216 val | DP83867_SW_RESTART); 217 218 if (phy_interface_is_rgmii(phydev)) { 219 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, 220 (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) | 221 (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); 222 if (ret) 223 goto err_out; 224 } else if (phy_interface_is_sgmii(phydev)) { 225 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, 226 (BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_SPEED1000)); 227 228 cfg2 = phy_read(phydev, phydev->addr, MII_DP83867_CFG2); 229 cfg2 &= MII_DP83867_CFG2_MASK; 230 cfg2 |= (MII_DP83867_CFG2_SPEEDOPT_10EN | 231 MII_DP83867_CFG2_SGMII_AUTONEGEN | 232 MII_DP83867_CFG2_SPEEDOPT_ENH | 233 MII_DP83867_CFG2_SPEEDOPT_CNT | 234 MII_DP83867_CFG2_SPEEDOPT_INTLOW); 235 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_CFG2, cfg2); 236 237 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, 238 DP83867_DEVADDR, phydev->addr, 0x0); 239 240 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, 241 DP83867_PHYCTRL_SGMIIEN | 242 (DP83867_MDI_CROSSOVER_MDIX << 243 DP83867_MDI_CROSSOVER) | 244 (dp83867->fifo_depth << DP83867_PHYCTRL_RXFIFO_SHIFT) | 245 (dp83867->fifo_depth << DP83867_PHYCTRL_TXFIFO_SHIFT)); 246 phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_BISCR, 0x0); 247 } 248 249 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && 250 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { 251 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, 252 DP83867_DEVADDR, phydev->addr); 253 254 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 255 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | 256 DP83867_RGMII_RX_CLK_DELAY_EN); 257 258 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 259 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 260 261 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 262 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 263 264 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, 265 DP83867_DEVADDR, phydev->addr, val); 266 267 delay = (dp83867->rx_id_delay | 268 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); 269 270 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, 271 DP83867_DEVADDR, phydev->addr, delay); 272 } 273 274 genphy_config_aneg(phydev); 275 return 0; 276 277 err_out: 278 kfree(dp83867); 279 return ret; 280 } 281 282 static struct phy_driver DP83867_driver = { 283 .name = "TI DP83867", 284 .uid = 0x2000a231, 285 .mask = 0xfffffff0, 286 .features = PHY_GBIT_FEATURES, 287 .config = &dp83867_config, 288 .startup = &genphy_startup, 289 .shutdown = &genphy_shutdown, 290 }; 291 292 int phy_ti_init(void) 293 { 294 phy_register(&DP83867_driver); 295 return 0; 296 } 297