1 /* 2 * TI PHY drivers 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 * 6 */ 7 #include <common.h> 8 #include <phy.h> 9 10 /* TI DP83867 */ 11 #define DP83867_DEVADDR 0x1f 12 13 #define MII_DP83867_PHYCTRL 0x10 14 #define MII_DP83867_MICR 0x12 15 #define DP83867_CTRL 0x1f 16 17 /* Extended Registers */ 18 #define DP83867_RGMIICTL 0x0032 19 #define DP83867_RGMIIDCTL 0x0086 20 21 #define DP83867_SW_RESET BIT(15) 22 #define DP83867_SW_RESTART BIT(14) 23 24 /* MICR Interrupt bits */ 25 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 26 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 27 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 28 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 29 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 30 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 31 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 32 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 33 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 34 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 35 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 36 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 37 38 /* RGMIICTL bits */ 39 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 40 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 41 42 /* PHY CTRL bits */ 43 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 44 45 /* RGMIIDCTL bits */ 46 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 47 48 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ 49 #define MII_MMD_DATA 0x0e /* MMD Access Data Register */ 50 51 /* MMD Access Control register fields */ 52 #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ 53 #define MII_MMD_CTRL_ADDR 0x0000 /* Address */ 54 #define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ 55 #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ 56 #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ 57 58 /** 59 * phy_read_mmd_indirect - reads data from the MMD registers 60 * @phydev: The PHY device bus 61 * @prtad: MMD Address 62 * @devad: MMD DEVAD 63 * @addr: PHY address on the MII bus 64 * 65 * Description: it reads data from the MMD registers (clause 22 to access to 66 * clause 45) of the specified phy address. 67 * To read these registers we have: 68 * 1) Write reg 13 // DEVAD 69 * 2) Write reg 14 // MMD Address 70 * 3) Write reg 13 // MMD Data Command for MMD DEVAD 71 * 3) Read reg 14 // Read MMD data 72 */ 73 int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, 74 int devad, int addr) 75 { 76 int value = -1; 77 78 /* Write the desired MMD Devad */ 79 phy_write(phydev, addr, MII_MMD_CTRL, devad); 80 81 /* Write the desired MMD register address */ 82 phy_write(phydev, addr, MII_MMD_DATA, prtad); 83 84 /* Select the Function : DATA with no post increment */ 85 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 86 87 /* Read the content of the MMD's selected register */ 88 value = phy_read(phydev, addr, MII_MMD_DATA); 89 return value; 90 } 91 92 /** 93 * phy_write_mmd_indirect - writes data to the MMD registers 94 * @phydev: The PHY device 95 * @prtad: MMD Address 96 * @devad: MMD DEVAD 97 * @addr: PHY address on the MII bus 98 * @data: data to write in the MMD register 99 * 100 * Description: Write data from the MMD registers of the specified 101 * phy address. 102 * To write these registers we have: 103 * 1) Write reg 13 // DEVAD 104 * 2) Write reg 14 // MMD Address 105 * 3) Write reg 13 // MMD Data Command for MMD DEVAD 106 * 3) Write reg 14 // Write MMD data 107 */ 108 void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, 109 int devad, int addr, u32 data) 110 { 111 /* Write the desired MMD Devad */ 112 phy_write(phydev, addr, MII_MMD_CTRL, devad); 113 114 /* Write the desired MMD register address */ 115 phy_write(phydev, addr, MII_MMD_DATA, prtad); 116 117 /* Select the Function : DATA with no post increment */ 118 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 119 120 /* Write the data into MMD's selected register */ 121 phy_write(phydev, addr, MII_MMD_DATA, data); 122 } 123 124 /** 125 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface 126 * is RGMII (all variants) 127 * @phydev: the phy_device struct 128 */ 129 static inline bool phy_interface_is_rgmii(struct phy_device *phydev) 130 { 131 return phydev->interface >= PHY_INTERFACE_MODE_RGMII && 132 phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; 133 } 134 135 /* User setting - can be taken from DTS */ 136 #define RX_ID_DELAY 8 137 #define TX_ID_DELAY 0xa 138 #define FIFO_DEPTH 1 139 140 static int dp83867_config(struct phy_device *phydev) 141 { 142 unsigned int val, delay; 143 int ret; 144 145 /* Restart the PHY. */ 146 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); 147 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, 148 val | DP83867_SW_RESTART); 149 150 if (phy_interface_is_rgmii(phydev)) { 151 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, 152 (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); 153 if (ret) 154 return ret; 155 } 156 157 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && 158 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { 159 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, 160 DP83867_DEVADDR, phydev->addr); 161 162 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 163 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | 164 DP83867_RGMII_RX_CLK_DELAY_EN); 165 166 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 167 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 168 169 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 170 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 171 172 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, 173 DP83867_DEVADDR, phydev->addr, val); 174 175 delay = (RX_ID_DELAY | 176 (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); 177 178 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, 179 DP83867_DEVADDR, phydev->addr, delay); 180 } 181 182 genphy_config_aneg(phydev); 183 return 0; 184 } 185 186 static struct phy_driver DP83867_driver = { 187 .name = "TI DP83867", 188 .uid = 0x2000a231, 189 .mask = 0xfffffff0, 190 .features = PHY_GBIT_FEATURES, 191 .config = &dp83867_config, 192 .startup = &genphy_startup, 193 .shutdown = &genphy_shutdown, 194 }; 195 196 int phy_ti_init(void) 197 { 198 phy_register(&DP83867_driver); 199 return 0; 200 } 201