1 /* 2 * TI PHY drivers 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 * 6 */ 7 #include <common.h> 8 #include <phy.h> 9 10 /* TI DP83867 */ 11 #define DP83867_DEVADDR 0x1f 12 13 #define MII_DP83867_PHYCTRL 0x10 14 #define MII_DP83867_MICR 0x12 15 #define DP83867_CTRL 0x1f 16 17 /* Extended Registers */ 18 #define DP83867_RGMIICTL 0x0032 19 #define DP83867_RGMIIDCTL 0x0086 20 21 #define DP83867_SW_RESET BIT(15) 22 #define DP83867_SW_RESTART BIT(14) 23 24 /* MICR Interrupt bits */ 25 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) 26 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) 27 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) 28 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) 29 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) 30 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) 31 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) 32 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) 33 #define MII_DP83867_MICR_WOL_INT_EN BIT(3) 34 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) 35 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) 36 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0) 37 38 /* RGMIICTL bits */ 39 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) 40 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) 41 42 /* PHY CTRL bits */ 43 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 44 #define DP83867_MDI_CROSSOVER 5 45 #define DP83867_MDI_CROSSOVER_AUTO 2 46 47 /* RGMIIDCTL bits */ 48 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 49 50 #define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ 51 #define MII_MMD_DATA 0x0e /* MMD Access Data Register */ 52 53 /* MMD Access Control register fields */ 54 #define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ 55 #define MII_MMD_CTRL_ADDR 0x0000 /* Address */ 56 #define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ 57 #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ 58 #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ 59 60 /** 61 * phy_read_mmd_indirect - reads data from the MMD registers 62 * @phydev: The PHY device bus 63 * @prtad: MMD Address 64 * @devad: MMD DEVAD 65 * @addr: PHY address on the MII bus 66 * 67 * Description: it reads data from the MMD registers (clause 22 to access to 68 * clause 45) of the specified phy address. 69 * To read these registers we have: 70 * 1) Write reg 13 // DEVAD 71 * 2) Write reg 14 // MMD Address 72 * 3) Write reg 13 // MMD Data Command for MMD DEVAD 73 * 3) Read reg 14 // Read MMD data 74 */ 75 int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, 76 int devad, int addr) 77 { 78 int value = -1; 79 80 /* Write the desired MMD Devad */ 81 phy_write(phydev, addr, MII_MMD_CTRL, devad); 82 83 /* Write the desired MMD register address */ 84 phy_write(phydev, addr, MII_MMD_DATA, prtad); 85 86 /* Select the Function : DATA with no post increment */ 87 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 88 89 /* Read the content of the MMD's selected register */ 90 value = phy_read(phydev, addr, MII_MMD_DATA); 91 return value; 92 } 93 94 /** 95 * phy_write_mmd_indirect - writes data to the MMD registers 96 * @phydev: The PHY device 97 * @prtad: MMD Address 98 * @devad: MMD DEVAD 99 * @addr: PHY address on the MII bus 100 * @data: data to write in the MMD register 101 * 102 * Description: Write data from the MMD registers of the specified 103 * phy address. 104 * To write these registers we have: 105 * 1) Write reg 13 // DEVAD 106 * 2) Write reg 14 // MMD Address 107 * 3) Write reg 13 // MMD Data Command for MMD DEVAD 108 * 3) Write reg 14 // Write MMD data 109 */ 110 void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, 111 int devad, int addr, u32 data) 112 { 113 /* Write the desired MMD Devad */ 114 phy_write(phydev, addr, MII_MMD_CTRL, devad); 115 116 /* Write the desired MMD register address */ 117 phy_write(phydev, addr, MII_MMD_DATA, prtad); 118 119 /* Select the Function : DATA with no post increment */ 120 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 121 122 /* Write the data into MMD's selected register */ 123 phy_write(phydev, addr, MII_MMD_DATA, data); 124 } 125 126 /** 127 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface 128 * is RGMII (all variants) 129 * @phydev: the phy_device struct 130 */ 131 static inline bool phy_interface_is_rgmii(struct phy_device *phydev) 132 { 133 return phydev->interface >= PHY_INTERFACE_MODE_RGMII && 134 phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; 135 } 136 137 /* User setting - can be taken from DTS */ 138 #define RX_ID_DELAY 8 139 #define TX_ID_DELAY 0xa 140 #define FIFO_DEPTH 1 141 142 static int dp83867_config(struct phy_device *phydev) 143 { 144 unsigned int val, delay; 145 int ret; 146 147 /* Restart the PHY. */ 148 val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); 149 phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, 150 val | DP83867_SW_RESTART); 151 152 if (phy_interface_is_rgmii(phydev)) { 153 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, 154 (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) | 155 (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); 156 if (ret) 157 return ret; 158 } 159 160 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && 161 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { 162 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, 163 DP83867_DEVADDR, phydev->addr); 164 165 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 166 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | 167 DP83867_RGMII_RX_CLK_DELAY_EN); 168 169 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 170 val |= DP83867_RGMII_TX_CLK_DELAY_EN; 171 172 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 173 val |= DP83867_RGMII_RX_CLK_DELAY_EN; 174 175 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, 176 DP83867_DEVADDR, phydev->addr, val); 177 178 delay = (RX_ID_DELAY | 179 (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); 180 181 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, 182 DP83867_DEVADDR, phydev->addr, delay); 183 } 184 185 genphy_config_aneg(phydev); 186 return 0; 187 } 188 189 static struct phy_driver DP83867_driver = { 190 .name = "TI DP83867", 191 .uid = 0x2000a231, 192 .mask = 0xfffffff0, 193 .features = PHY_GBIT_FEATURES, 194 .config = &dp83867_config, 195 .startup = &genphy_startup, 196 .shutdown = &genphy_shutdown, 197 }; 198 199 int phy_ti_init(void) 200 { 201 phy_register(&DP83867_driver); 202 return 0; 203 } 204