1 /* 2 * National Semiconductor PHY drivers 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 * 19 * Copyright 2010-2011 Freescale Semiconductor, Inc. 20 * author Andy Fleming 21 * 22 */ 23 #include <phy.h> 24 25 /* NatSemi DP83630 */ 26 27 #define DP83630_PHY_PAGESEL_REG 0x13 28 #define DP83630_PHY_PTP_COC_REG 0x14 29 #define DP83630_PHY_PTP_CLKOUT_EN (1<<15) 30 #define DP83630_PHY_RBR_REG 0x17 31 32 static int dp83630_config(struct phy_device *phydev) 33 { 34 int ptp_coc_reg; 35 36 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 37 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6); 38 ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE, 39 DP83630_PHY_PTP_COC_REG); 40 ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN; 41 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG, 42 ptp_coc_reg); 43 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0); 44 45 genphy_config_aneg(phydev); 46 47 return 0; 48 } 49 50 static struct phy_driver DP83630_driver = { 51 .name = "NatSemi DP83630", 52 .uid = 0x20005ce1, 53 .mask = 0xfffffff0, 54 .features = PHY_BASIC_FEATURES, 55 .config = &dp83630_config, 56 .startup = &genphy_startup, 57 .shutdown = &genphy_shutdown, 58 }; 59 60 61 /* DP83865 Link and Auto-Neg Status Register */ 62 #define MIIM_DP83865_LANR 0x11 63 #define MIIM_DP83865_SPD_MASK 0x0018 64 #define MIIM_DP83865_SPD_1000 0x0010 65 #define MIIM_DP83865_SPD_100 0x0008 66 #define MIIM_DP83865_DPX_FULL 0x0002 67 68 69 /* NatSemi DP83865 */ 70 static int dp83865_config(struct phy_device *phydev) 71 { 72 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 73 genphy_config_aneg(phydev); 74 75 return 0; 76 } 77 78 static int dp83865_parse_status(struct phy_device *phydev) 79 { 80 int mii_reg; 81 82 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR); 83 84 switch (mii_reg & MIIM_DP83865_SPD_MASK) { 85 86 case MIIM_DP83865_SPD_1000: 87 phydev->speed = SPEED_1000; 88 break; 89 90 case MIIM_DP83865_SPD_100: 91 phydev->speed = SPEED_100; 92 break; 93 94 default: 95 phydev->speed = SPEED_10; 96 break; 97 98 } 99 100 if (mii_reg & MIIM_DP83865_DPX_FULL) 101 phydev->duplex = DUPLEX_FULL; 102 else 103 phydev->duplex = DUPLEX_HALF; 104 105 return 0; 106 } 107 108 static int dp83865_startup(struct phy_device *phydev) 109 { 110 genphy_update_link(phydev); 111 dp83865_parse_status(phydev); 112 113 return 0; 114 } 115 116 117 static struct phy_driver DP83865_driver = { 118 .name = "NatSemi DP83865", 119 .uid = 0x20005c70, 120 .mask = 0xfffffff0, 121 .features = PHY_GBIT_FEATURES, 122 .config = &dp83865_config, 123 .startup = &dp83865_startup, 124 .shutdown = &genphy_shutdown, 125 }; 126 127 int phy_natsemi_init(void) 128 { 129 phy_register(&DP83630_driver); 130 phy_register(&DP83865_driver); 131 132 return 0; 133 } 134