1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2015 4 * Elecsys Corporation <www.elecsyscorp.com> 5 * Kevin Smith <kevin.smith@elecsyscorp.com> 6 * 7 * Original driver: 8 * (C) Copyright 2009 9 * Marvell Semiconductor <www.marvell.com> 10 * Prafulla Wadaskar <prafulla@marvell.com> 11 */ 12 13 /* 14 * PHY driver for mv88e61xx ethernet switches. 15 * 16 * This driver configures the mv88e61xx for basic use as a PHY. The switch 17 * supports a VLAN configuration that determines how traffic will be routed 18 * between the ports. This driver uses a simple configuration that routes 19 * traffic from each PHY port only to the CPU port, and from the CPU port to 20 * any PHY port. 21 * 22 * The configuration determines which PHY ports to activate using the 23 * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit 24 * 1 activates port 1, etc. Do not set the bit for the port the CPU is 25 * connected to unless it is connected over a PHY interface (not MII). 26 * 27 * This driver was written for and tested on the mv88e6176 with an SGMII 28 * connection. Other configurations should be supported, but some additions or 29 * changes may be required. 30 */ 31 32 #include <common.h> 33 34 #include <bitfield.h> 35 #include <errno.h> 36 #include <malloc.h> 37 #include <miiphy.h> 38 #include <netdev.h> 39 40 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 41 42 #define PORT_COUNT 11 43 #define PORT_MASK ((1 << PORT_COUNT) - 1) 44 45 /* Device addresses */ 46 #define DEVADDR_PHY(p) (p) 47 #define DEVADDR_PORT(p) (0x10 + (p)) 48 #define DEVADDR_SERDES 0x0F 49 #define DEVADDR_GLOBAL_1 0x1B 50 #define DEVADDR_GLOBAL_2 0x1C 51 52 /* SMI indirection registers for multichip addressing mode */ 53 #define SMI_CMD_REG 0x00 54 #define SMI_DATA_REG 0x01 55 56 /* Global registers */ 57 #define GLOBAL1_STATUS 0x00 58 #define GLOBAL1_CTRL 0x04 59 #define GLOBAL1_MON_CTRL 0x1A 60 61 /* Global 2 registers */ 62 #define GLOBAL2_REG_PHY_CMD 0x18 63 #define GLOBAL2_REG_PHY_DATA 0x19 64 65 /* Port registers */ 66 #define PORT_REG_STATUS 0x00 67 #define PORT_REG_PHYS_CTRL 0x01 68 #define PORT_REG_SWITCH_ID 0x03 69 #define PORT_REG_CTRL 0x04 70 #define PORT_REG_VLAN_MAP 0x06 71 #define PORT_REG_VLAN_ID 0x07 72 73 /* Phy registers */ 74 #define PHY_REG_CTRL1 0x10 75 #define PHY_REG_STATUS1 0x11 76 #define PHY_REG_PAGE 0x16 77 78 /* Serdes registers */ 79 #define SERDES_REG_CTRL_1 0x10 80 81 /* Phy page numbers */ 82 #define PHY_PAGE_COPPER 0 83 #define PHY_PAGE_SERDES 1 84 85 /* Register fields */ 86 #define GLOBAL1_CTRL_SWRESET BIT(15) 87 88 #define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4 89 #define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4 90 91 #define PORT_REG_STATUS_LINK BIT(11) 92 #define PORT_REG_STATUS_DUPLEX BIT(10) 93 94 #define PORT_REG_STATUS_SPEED_SHIFT 8 95 #define PORT_REG_STATUS_SPEED_WIDTH 2 96 #define PORT_REG_STATUS_SPEED_10 0 97 #define PORT_REG_STATUS_SPEED_100 1 98 #define PORT_REG_STATUS_SPEED_1000 2 99 100 #define PORT_REG_STATUS_CMODE_MASK 0xF 101 #define PORT_REG_STATUS_CMODE_100BASE_X 0x8 102 #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9 103 #define PORT_REG_STATUS_CMODE_SGMII 0xa 104 105 #define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10) 106 #define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9) 107 #define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7) 108 #define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6) 109 #define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5) 110 #define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4) 111 #define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3) 112 #define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2) 113 #define PORT_REG_PHYS_CTRL_SPD1000 BIT(1) 114 #define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0)) 115 116 #define PORT_REG_CTRL_PSTATE_SHIFT 0 117 #define PORT_REG_CTRL_PSTATE_WIDTH 2 118 119 #define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0 120 #define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12 121 122 #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0 123 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11 124 125 #define SERDES_REG_CTRL_1_FORCE_LINK BIT(10) 126 127 #define PHY_REG_CTRL1_ENERGY_DET_SHIFT 8 128 #define PHY_REG_CTRL1_ENERGY_DET_WIDTH 2 129 130 /* Field values */ 131 #define PORT_REG_CTRL_PSTATE_DISABLED 0 132 #define PORT_REG_CTRL_PSTATE_FORWARD 3 133 134 #define PHY_REG_CTRL1_ENERGY_DET_OFF 0 135 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2 136 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3 137 138 /* PHY Status Register */ 139 #define PHY_REG_STATUS1_SPEED 0xc000 140 #define PHY_REG_STATUS1_GBIT 0x8000 141 #define PHY_REG_STATUS1_100 0x4000 142 #define PHY_REG_STATUS1_DUPLEX 0x2000 143 #define PHY_REG_STATUS1_SPDDONE 0x0800 144 #define PHY_REG_STATUS1_LINK 0x0400 145 #define PHY_REG_STATUS1_ENERGY 0x0010 146 147 /* 148 * Macros for building commands for indirect addressing modes. These are valid 149 * for both the indirect multichip addressing mode and the PHY indirection 150 * required for the writes to any PHY register. 151 */ 152 #define SMI_BUSY BIT(15) 153 #define SMI_CMD_CLAUSE_22 BIT(12) 154 #define SMI_CMD_CLAUSE_22_OP_READ (2 << 10) 155 #define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10) 156 157 #define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \ 158 SMI_CMD_CLAUSE_22_OP_READ) 159 #define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \ 160 SMI_CMD_CLAUSE_22_OP_WRITE) 161 162 #define SMI_CMD_ADDR_SHIFT 5 163 #define SMI_CMD_ADDR_WIDTH 5 164 #define SMI_CMD_REG_SHIFT 0 165 #define SMI_CMD_REG_WIDTH 5 166 167 /* Check for required macros */ 168 #ifndef CONFIG_MV88E61XX_PHY_PORTS 169 #error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \ 170 to activate 171 #endif 172 #ifndef CONFIG_MV88E61XX_CPU_PORT 173 #error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to 174 #endif 175 176 /* 177 * These are ports without PHYs that may be wired directly 178 * to other serdes interfaces 179 */ 180 #ifndef CONFIG_MV88E61XX_FIXED_PORTS 181 #define CONFIG_MV88E61XX_FIXED_PORTS 0 182 #endif 183 184 /* ID register values for different switch models */ 185 #define PORT_SWITCH_ID_6096 0x0980 186 #define PORT_SWITCH_ID_6097 0x0990 187 #define PORT_SWITCH_ID_6172 0x1720 188 #define PORT_SWITCH_ID_6176 0x1760 189 #define PORT_SWITCH_ID_6240 0x2400 190 #define PORT_SWITCH_ID_6352 0x3520 191 192 struct mv88e61xx_phy_priv { 193 struct mii_dev *mdio_bus; 194 int smi_addr; 195 int id; 196 }; 197 198 static inline int smi_cmd(int cmd, int addr, int reg) 199 { 200 cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH, 201 addr); 202 cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg); 203 return cmd; 204 } 205 206 static inline int smi_cmd_read(int addr, int reg) 207 { 208 return smi_cmd(SMI_CMD_READ, addr, reg); 209 } 210 211 static inline int smi_cmd_write(int addr, int reg) 212 { 213 return smi_cmd(SMI_CMD_WRITE, addr, reg); 214 } 215 216 __weak int mv88e61xx_hw_reset(struct phy_device *phydev) 217 { 218 return 0; 219 } 220 221 /* Wait for the current SMI indirect command to complete */ 222 static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr) 223 { 224 int val; 225 u32 timeout = 100; 226 227 do { 228 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG); 229 if (val >= 0 && (val & SMI_BUSY) == 0) 230 return 0; 231 232 mdelay(1); 233 } while (--timeout); 234 235 puts("SMI busy timeout\n"); 236 return -ETIMEDOUT; 237 } 238 239 /* 240 * The mv88e61xx has three types of addresses: the smi bus address, the device 241 * address, and the register address. The smi bus address distinguishes it on 242 * the smi bus from other PHYs or switches. The device address determines 243 * which on-chip register set you are reading/writing (the various PHYs, their 244 * associated ports, or global configuration registers). The register address 245 * is the offset of the register you are reading/writing. 246 * 247 * When the mv88e61xx is hardware configured to have address zero, it behaves in 248 * single-chip addressing mode, where it responds to all SMI addresses, using 249 * the smi address as its device address. This obviously only works when this 250 * is the only chip on the SMI bus. This allows the driver to access device 251 * registers without using indirection. When the chip is configured to a 252 * non-zero address, it only responds to that SMI address and requires indirect 253 * writes to access the different device addresses. 254 */ 255 static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg) 256 { 257 struct mv88e61xx_phy_priv *priv = phydev->priv; 258 struct mii_dev *mdio_bus = priv->mdio_bus; 259 int smi_addr = priv->smi_addr; 260 int res; 261 262 /* In single-chip mode, the device can be addressed directly */ 263 if (smi_addr == 0) 264 return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg); 265 266 /* Wait for the bus to become free */ 267 res = mv88e61xx_smi_wait(mdio_bus, smi_addr); 268 if (res < 0) 269 return res; 270 271 /* Issue the read command */ 272 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG, 273 smi_cmd_read(dev, reg)); 274 if (res < 0) 275 return res; 276 277 /* Wait for the read command to complete */ 278 res = mv88e61xx_smi_wait(mdio_bus, smi_addr); 279 if (res < 0) 280 return res; 281 282 /* Read the data */ 283 res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG); 284 if (res < 0) 285 return res; 286 287 return bitfield_extract(res, 0, 16); 288 } 289 290 /* See the comment above mv88e61xx_reg_read */ 291 static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg, 292 u16 val) 293 { 294 struct mv88e61xx_phy_priv *priv = phydev->priv; 295 struct mii_dev *mdio_bus = priv->mdio_bus; 296 int smi_addr = priv->smi_addr; 297 int res; 298 299 /* In single-chip mode, the device can be addressed directly */ 300 if (smi_addr == 0) { 301 return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg, 302 val); 303 } 304 305 /* Wait for the bus to become free */ 306 res = mv88e61xx_smi_wait(mdio_bus, smi_addr); 307 if (res < 0) 308 return res; 309 310 /* Set the data to write */ 311 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, 312 SMI_DATA_REG, val); 313 if (res < 0) 314 return res; 315 316 /* Issue the write command */ 317 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG, 318 smi_cmd_write(dev, reg)); 319 if (res < 0) 320 return res; 321 322 /* Wait for the write command to complete */ 323 res = mv88e61xx_smi_wait(mdio_bus, smi_addr); 324 if (res < 0) 325 return res; 326 327 return 0; 328 } 329 330 static int mv88e61xx_phy_wait(struct phy_device *phydev) 331 { 332 int val; 333 u32 timeout = 100; 334 335 do { 336 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, 337 GLOBAL2_REG_PHY_CMD); 338 if (val >= 0 && (val & SMI_BUSY) == 0) 339 return 0; 340 341 mdelay(1); 342 } while (--timeout); 343 344 return -ETIMEDOUT; 345 } 346 347 static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev, 348 int devad, int reg) 349 { 350 struct phy_device *phydev; 351 int res; 352 353 phydev = (struct phy_device *)smi_wrapper->priv; 354 355 /* Issue command to read */ 356 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2, 357 GLOBAL2_REG_PHY_CMD, 358 smi_cmd_read(dev, reg)); 359 360 /* Wait for data to be read */ 361 res = mv88e61xx_phy_wait(phydev); 362 if (res < 0) 363 return res; 364 365 /* Read retrieved data */ 366 return mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, 367 GLOBAL2_REG_PHY_DATA); 368 } 369 370 static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev, 371 int devad, int reg, u16 data) 372 { 373 struct phy_device *phydev; 374 int res; 375 376 phydev = (struct phy_device *)smi_wrapper->priv; 377 378 /* Set the data to write */ 379 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2, 380 GLOBAL2_REG_PHY_DATA, data); 381 if (res < 0) 382 return res; 383 /* Issue the write command */ 384 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2, 385 GLOBAL2_REG_PHY_CMD, 386 smi_cmd_write(dev, reg)); 387 if (res < 0) 388 return res; 389 390 /* Wait for command to complete */ 391 return mv88e61xx_phy_wait(phydev); 392 } 393 394 /* Wrapper function to make calls to phy_read_indirect simpler */ 395 static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg) 396 { 397 return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy), 398 MDIO_DEVAD_NONE, reg); 399 } 400 401 /* Wrapper function to make calls to phy_read_indirect simpler */ 402 static int mv88e61xx_phy_write(struct phy_device *phydev, int phy, 403 int reg, u16 val) 404 { 405 return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy), 406 MDIO_DEVAD_NONE, reg, val); 407 } 408 409 static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg) 410 { 411 return mv88e61xx_reg_read(phydev, DEVADDR_PORT(port), reg); 412 } 413 414 static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg, 415 u16 val) 416 { 417 return mv88e61xx_reg_write(phydev, DEVADDR_PORT(port), reg, val); 418 } 419 420 static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page) 421 { 422 return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page); 423 } 424 425 static int mv88e61xx_get_switch_id(struct phy_device *phydev) 426 { 427 int res; 428 429 res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID); 430 if (res < 0) 431 return res; 432 return res & 0xfff0; 433 } 434 435 static bool mv88e61xx_6352_family(struct phy_device *phydev) 436 { 437 struct mv88e61xx_phy_priv *priv = phydev->priv; 438 439 switch (priv->id) { 440 case PORT_SWITCH_ID_6172: 441 case PORT_SWITCH_ID_6176: 442 case PORT_SWITCH_ID_6240: 443 case PORT_SWITCH_ID_6352: 444 return true; 445 } 446 return false; 447 } 448 449 static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port) 450 { 451 int res; 452 453 res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS); 454 if (res < 0) 455 return res; 456 return res & PORT_REG_STATUS_CMODE_MASK; 457 } 458 459 static int mv88e61xx_parse_status(struct phy_device *phydev) 460 { 461 unsigned int speed; 462 unsigned int mii_reg; 463 464 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1); 465 466 if ((mii_reg & PHY_REG_STATUS1_LINK) && 467 !(mii_reg & PHY_REG_STATUS1_SPDDONE)) { 468 int i = 0; 469 470 puts("Waiting for PHY realtime link"); 471 while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) { 472 /* Timeout reached ? */ 473 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 474 puts(" TIMEOUT !\n"); 475 phydev->link = 0; 476 break; 477 } 478 479 if ((i++ % 1000) == 0) 480 putc('.'); 481 udelay(1000); 482 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, 483 PHY_REG_STATUS1); 484 } 485 puts(" done\n"); 486 udelay(500000); /* another 500 ms (results in faster booting) */ 487 } else { 488 if (mii_reg & PHY_REG_STATUS1_LINK) 489 phydev->link = 1; 490 else 491 phydev->link = 0; 492 } 493 494 if (mii_reg & PHY_REG_STATUS1_DUPLEX) 495 phydev->duplex = DUPLEX_FULL; 496 else 497 phydev->duplex = DUPLEX_HALF; 498 499 speed = mii_reg & PHY_REG_STATUS1_SPEED; 500 501 switch (speed) { 502 case PHY_REG_STATUS1_GBIT: 503 phydev->speed = SPEED_1000; 504 break; 505 case PHY_REG_STATUS1_100: 506 phydev->speed = SPEED_100; 507 break; 508 default: 509 phydev->speed = SPEED_10; 510 break; 511 } 512 513 return 0; 514 } 515 516 static int mv88e61xx_switch_reset(struct phy_device *phydev) 517 { 518 int time; 519 int val; 520 u8 port; 521 522 /* Disable all ports */ 523 for (port = 0; port < PORT_COUNT; port++) { 524 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL); 525 if (val < 0) 526 return val; 527 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT, 528 PORT_REG_CTRL_PSTATE_WIDTH, 529 PORT_REG_CTRL_PSTATE_DISABLED); 530 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val); 531 if (val < 0) 532 return val; 533 } 534 535 /* Wait 2 ms for queues to drain */ 536 udelay(2000); 537 538 /* Reset switch */ 539 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_CTRL); 540 if (val < 0) 541 return val; 542 val |= GLOBAL1_CTRL_SWRESET; 543 val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1, 544 GLOBAL1_CTRL, val); 545 if (val < 0) 546 return val; 547 548 /* Wait up to 1 second for switch reset complete */ 549 for (time = 1000; time; time--) { 550 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, 551 GLOBAL1_CTRL); 552 if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0)) 553 break; 554 udelay(1000); 555 } 556 if (!time) 557 return -ETIMEDOUT; 558 559 return 0; 560 } 561 562 static int mv88e61xx_serdes_init(struct phy_device *phydev) 563 { 564 int val; 565 566 val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES); 567 if (val < 0) 568 return val; 569 570 /* Power up serdes module */ 571 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR); 572 if (val < 0) 573 return val; 574 val &= ~(BMCR_PDOWN); 575 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val); 576 if (val < 0) 577 return val; 578 579 return 0; 580 } 581 582 static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port) 583 { 584 int val; 585 586 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL); 587 if (val < 0) 588 return val; 589 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT, 590 PORT_REG_CTRL_PSTATE_WIDTH, 591 PORT_REG_CTRL_PSTATE_FORWARD); 592 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val); 593 if (val < 0) 594 return val; 595 596 return 0; 597 } 598 599 static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port, 600 u16 mask) 601 { 602 int val; 603 604 /* Set VID to port number plus one */ 605 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID); 606 if (val < 0) 607 return val; 608 val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT, 609 PORT_REG_VLAN_ID_DEF_VID_WIDTH, 610 port + 1); 611 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val); 612 if (val < 0) 613 return val; 614 615 /* Set VID mask */ 616 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP); 617 if (val < 0) 618 return val; 619 val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT, 620 PORT_REG_VLAN_MAP_TABLE_WIDTH, 621 mask); 622 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val); 623 if (val < 0) 624 return val; 625 626 return 0; 627 } 628 629 static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port) 630 { 631 int res; 632 int val; 633 bool forced = false; 634 635 val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS); 636 if (val < 0) 637 return val; 638 if (!(val & PORT_REG_STATUS_LINK)) { 639 /* Temporarily force link to read port configuration */ 640 u32 timeout = 100; 641 forced = true; 642 643 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); 644 if (val < 0) 645 return val; 646 val |= (PORT_REG_PHYS_CTRL_LINK_FORCE | 647 PORT_REG_PHYS_CTRL_LINK_VALUE); 648 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, 649 val); 650 if (val < 0) 651 return val; 652 653 /* Wait for status register to reflect forced link */ 654 do { 655 val = mv88e61xx_port_read(phydev, port, 656 PORT_REG_STATUS); 657 if (val < 0) { 658 res = -EIO; 659 goto unforce; 660 } 661 if (val & PORT_REG_STATUS_LINK) 662 break; 663 } while (--timeout); 664 665 if (timeout == 0) { 666 res = -ETIMEDOUT; 667 goto unforce; 668 } 669 } 670 671 if (val & PORT_REG_STATUS_DUPLEX) 672 phydev->duplex = DUPLEX_FULL; 673 else 674 phydev->duplex = DUPLEX_HALF; 675 676 val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT, 677 PORT_REG_STATUS_SPEED_WIDTH); 678 switch (val) { 679 case PORT_REG_STATUS_SPEED_1000: 680 phydev->speed = SPEED_1000; 681 break; 682 case PORT_REG_STATUS_SPEED_100: 683 phydev->speed = SPEED_100; 684 break; 685 default: 686 phydev->speed = SPEED_10; 687 break; 688 } 689 690 res = 0; 691 692 unforce: 693 if (forced) { 694 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); 695 if (val < 0) 696 return val; 697 val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE | 698 PORT_REG_PHYS_CTRL_LINK_VALUE); 699 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, 700 val); 701 if (val < 0) 702 return val; 703 } 704 705 return res; 706 } 707 708 static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port) 709 { 710 int val; 711 712 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL); 713 if (val < 0) 714 return val; 715 716 val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK | 717 PORT_REG_PHYS_CTRL_FC_VALUE); 718 val |= PORT_REG_PHYS_CTRL_PCS_AN_EN | 719 PORT_REG_PHYS_CTRL_PCS_AN_RST | 720 PORT_REG_PHYS_CTRL_FC_FORCE | 721 PORT_REG_PHYS_CTRL_DUPLEX_VALUE | 722 PORT_REG_PHYS_CTRL_DUPLEX_FORCE | 723 PORT_REG_PHYS_CTRL_SPD1000; 724 725 if (port == CONFIG_MV88E61XX_CPU_PORT) 726 val |= PORT_REG_PHYS_CTRL_LINK_VALUE | 727 PORT_REG_PHYS_CTRL_LINK_FORCE; 728 729 return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL, 730 val); 731 } 732 733 static int mv88e61xx_set_cpu_port(struct phy_device *phydev) 734 { 735 int val; 736 737 /* Set CPUDest */ 738 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_1, GLOBAL1_MON_CTRL); 739 if (val < 0) 740 return val; 741 val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT, 742 GLOBAL1_MON_CTRL_CPUDEST_WIDTH, 743 CONFIG_MV88E61XX_CPU_PORT); 744 val = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_1, 745 GLOBAL1_MON_CTRL, val); 746 if (val < 0) 747 return val; 748 749 /* Allow CPU to route to any port */ 750 val = PORT_MASK & ~(1 << CONFIG_MV88E61XX_CPU_PORT); 751 val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val); 752 if (val < 0) 753 return val; 754 755 /* Enable CPU port */ 756 val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT); 757 if (val < 0) 758 return val; 759 760 val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT); 761 if (val < 0) 762 return val; 763 764 /* If CPU is connected to serdes, initialize serdes */ 765 if (mv88e61xx_6352_family(phydev)) { 766 val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT); 767 if (val < 0) 768 return val; 769 if (val == PORT_REG_STATUS_CMODE_100BASE_X || 770 val == PORT_REG_STATUS_CMODE_1000BASE_X || 771 val == PORT_REG_STATUS_CMODE_SGMII) { 772 val = mv88e61xx_serdes_init(phydev); 773 if (val < 0) 774 return val; 775 } 776 } else { 777 val = mv88e61xx_fixed_port_setup(phydev, 778 CONFIG_MV88E61XX_CPU_PORT); 779 if (val < 0) 780 return val; 781 } 782 783 return 0; 784 } 785 786 static int mv88e61xx_switch_init(struct phy_device *phydev) 787 { 788 static int init; 789 int res; 790 791 if (init) 792 return 0; 793 794 res = mv88e61xx_switch_reset(phydev); 795 if (res < 0) 796 return res; 797 798 res = mv88e61xx_set_cpu_port(phydev); 799 if (res < 0) 800 return res; 801 802 init = 1; 803 804 return 0; 805 } 806 807 static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy) 808 { 809 int val; 810 811 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR); 812 if (val < 0) 813 return val; 814 val &= ~(BMCR_PDOWN); 815 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val); 816 if (val < 0) 817 return val; 818 819 return 0; 820 } 821 822 static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy) 823 { 824 int val; 825 826 /* 827 * Enable energy-detect sensing on PHY, used to determine when a PHY 828 * port is physically connected 829 */ 830 val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1); 831 if (val < 0) 832 return val; 833 val = bitfield_replace(val, PHY_REG_CTRL1_ENERGY_DET_SHIFT, 834 PHY_REG_CTRL1_ENERGY_DET_WIDTH, 835 PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT); 836 val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val); 837 if (val < 0) 838 return val; 839 840 return 0; 841 } 842 843 static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy) 844 { 845 int val; 846 847 val = mv88e61xx_port_enable(phydev, phy); 848 if (val < 0) 849 return val; 850 851 val = mv88e61xx_port_set_vlan(phydev, phy, 852 1 << CONFIG_MV88E61XX_CPU_PORT); 853 if (val < 0) 854 return val; 855 856 return 0; 857 } 858 859 static int mv88e61xx_probe(struct phy_device *phydev) 860 { 861 struct mii_dev *smi_wrapper; 862 struct mv88e61xx_phy_priv *priv; 863 int res; 864 865 res = mv88e61xx_hw_reset(phydev); 866 if (res < 0) 867 return res; 868 869 priv = malloc(sizeof(*priv)); 870 if (!priv) 871 return -ENOMEM; 872 873 memset(priv, 0, sizeof(*priv)); 874 875 /* 876 * This device requires indirect reads/writes to the PHY registers 877 * which the generic PHY code can't handle. Make a wrapper MII device 878 * to handle reads/writes 879 */ 880 smi_wrapper = mdio_alloc(); 881 if (!smi_wrapper) { 882 free(priv); 883 return -ENOMEM; 884 } 885 886 /* 887 * Store the mdio bus in the private data, as we are going to replace 888 * the bus with the wrapper bus 889 */ 890 priv->mdio_bus = phydev->bus; 891 892 /* 893 * Store the smi bus address in private data. This lets us use the 894 * phydev addr field for device address instead, as the genphy code 895 * expects. 896 */ 897 priv->smi_addr = phydev->addr; 898 899 /* 900 * Store the phy_device in the wrapper mii device. This lets us get it 901 * back when genphy functions call phy_read/phy_write. 902 */ 903 smi_wrapper->priv = phydev; 904 strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name)); 905 smi_wrapper->read = mv88e61xx_phy_read_indirect; 906 smi_wrapper->write = mv88e61xx_phy_write_indirect; 907 908 /* Replace the bus with the wrapper device */ 909 phydev->bus = smi_wrapper; 910 911 phydev->priv = priv; 912 913 priv->id = mv88e61xx_get_switch_id(phydev); 914 915 return 0; 916 } 917 918 static int mv88e61xx_phy_config(struct phy_device *phydev) 919 { 920 int res; 921 int i; 922 int ret = -1; 923 924 res = mv88e61xx_switch_init(phydev); 925 if (res < 0) 926 return res; 927 928 for (i = 0; i < PORT_COUNT; i++) { 929 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) { 930 phydev->addr = i; 931 932 res = mv88e61xx_phy_enable(phydev, i); 933 if (res < 0) { 934 printf("Error enabling PHY %i\n", i); 935 continue; 936 } 937 res = mv88e61xx_phy_setup(phydev, i); 938 if (res < 0) { 939 printf("Error setting up PHY %i\n", i); 940 continue; 941 } 942 res = mv88e61xx_phy_config_port(phydev, i); 943 if (res < 0) { 944 printf("Error configuring PHY %i\n", i); 945 continue; 946 } 947 948 res = genphy_config_aneg(phydev); 949 if (res < 0) { 950 printf("Error setting PHY %i autoneg\n", i); 951 continue; 952 } 953 res = phy_reset(phydev); 954 if (res < 0) { 955 printf("Error resetting PHY %i\n", i); 956 continue; 957 } 958 959 /* Return success if any PHY succeeds */ 960 ret = 0; 961 } else if ((1 << i) & CONFIG_MV88E61XX_FIXED_PORTS) { 962 res = mv88e61xx_fixed_port_setup(phydev, i); 963 if (res < 0) { 964 printf("Error configuring port %i\n", i); 965 continue; 966 } 967 } 968 } 969 970 return ret; 971 } 972 973 static int mv88e61xx_phy_is_connected(struct phy_device *phydev) 974 { 975 int val; 976 977 val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1); 978 if (val < 0) 979 return 0; 980 981 /* 982 * After reset, the energy detect signal remains high for a few seconds 983 * regardless of whether a cable is connected. This function will 984 * return false positives during this time. 985 */ 986 return (val & PHY_REG_STATUS1_ENERGY) == 0; 987 } 988 989 static int mv88e61xx_phy_startup(struct phy_device *phydev) 990 { 991 int i; 992 int link = 0; 993 int res; 994 int speed = phydev->speed; 995 int duplex = phydev->duplex; 996 997 for (i = 0; i < PORT_COUNT; i++) { 998 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) { 999 phydev->addr = i; 1000 if (!mv88e61xx_phy_is_connected(phydev)) 1001 continue; 1002 res = genphy_update_link(phydev); 1003 if (res < 0) 1004 continue; 1005 res = mv88e61xx_parse_status(phydev); 1006 if (res < 0) 1007 continue; 1008 link = (link || phydev->link); 1009 } 1010 } 1011 phydev->link = link; 1012 1013 /* Restore CPU interface speed and duplex after it was changed for 1014 * other ports */ 1015 phydev->speed = speed; 1016 phydev->duplex = duplex; 1017 1018 return 0; 1019 } 1020 1021 static struct phy_driver mv88e61xx_driver = { 1022 .name = "Marvell MV88E61xx", 1023 .uid = 0x01410eb1, 1024 .mask = 0xfffffff0, 1025 .features = PHY_GBIT_FEATURES, 1026 .probe = mv88e61xx_probe, 1027 .config = mv88e61xx_phy_config, 1028 .startup = mv88e61xx_phy_startup, 1029 .shutdown = &genphy_shutdown, 1030 }; 1031 1032 static struct phy_driver mv88e609x_driver = { 1033 .name = "Marvell MV88E609x", 1034 .uid = 0x1410c89, 1035 .mask = 0xfffffff0, 1036 .features = PHY_GBIT_FEATURES, 1037 .probe = mv88e61xx_probe, 1038 .config = mv88e61xx_phy_config, 1039 .startup = mv88e61xx_phy_startup, 1040 .shutdown = &genphy_shutdown, 1041 }; 1042 1043 int phy_mv88e61xx_init(void) 1044 { 1045 phy_register(&mv88e61xx_driver); 1046 phy_register(&mv88e609x_driver); 1047 1048 return 0; 1049 } 1050 1051 /* 1052 * Overload weak get_phy_id definition since we need non-standard functions 1053 * to read PHY registers 1054 */ 1055 int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id) 1056 { 1057 struct phy_device temp_phy; 1058 struct mv88e61xx_phy_priv temp_priv; 1059 struct mii_dev temp_mii; 1060 int val; 1061 1062 /* 1063 * Buid temporary data structures that the chip reading code needs to 1064 * read the ID 1065 */ 1066 temp_priv.mdio_bus = bus; 1067 temp_priv.smi_addr = smi_addr; 1068 temp_phy.priv = &temp_priv; 1069 temp_mii.priv = &temp_phy; 1070 1071 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1); 1072 if (val < 0) 1073 return -EIO; 1074 1075 *phy_id = val << 16; 1076 1077 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2); 1078 if (val < 0) 1079 return -EIO; 1080 1081 *phy_id |= (val & 0xffff); 1082 1083 return 0; 1084 } 1085