1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 */ 24 25 #include <common.h> 26 #include <netdev.h> 27 #include "mv88e61xx.h" 28 29 /* 30 * Uncomment either of the following line for local debug control; 31 * otherwise global debug control will apply. 32 */ 33 34 /* #undef DEBUG */ 35 /* #define DEBUG */ 36 37 #ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE 38 /* Chip Address mode 39 * The Switch support two modes of operation 40 * 1. single chip mode and 41 * 2. Multi-chip mode 42 * Refer section 9.2 &9.3 in chip datasheet-02 for more details 43 * 44 * By default single chip mode is configured 45 * multichip mode operation can be configured in board header 46 */ 47 static int mv88e61xx_busychk_multic(char *name, u32 devaddr) 48 { 49 u16 reg = 0; 50 u32 timeout = MV88E61XX_PHY_TIMEOUT; 51 52 /* Poll till SMIBusy bit is clear */ 53 do { 54 miiphy_read(name, devaddr, 0x0, ®); 55 if (timeout-- == 0) { 56 printf("SMI busy timeout\n"); 57 return -1; 58 } 59 } while (reg & (1 << 15)); 60 return 0; 61 } 62 63 static void mv88e61xx_switch_write(char *name, u32 phy_adr, 64 u32 reg_ofs, u16 data) 65 { 66 u16 mii_dev_addr; 67 68 /* command to read PHY dev address */ 69 if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { 70 printf("Error..could not read PHY dev address\n"); 71 return; 72 } 73 mv88e61xx_busychk_multic(name, mii_dev_addr); 74 /* Write data to Switch indirect data register */ 75 miiphy_write(name, mii_dev_addr, 0x1, data); 76 /* Write command to Switch indirect command register (write) */ 77 miiphy_write(name, mii_dev_addr, 0x0, 78 reg_ofs | (phy_adr << 5) | (1 << 10) | (1 << 12) | (1 << 79 15)); 80 } 81 82 static void mv88e61xx_switch_read(char *name, u32 phy_adr, 83 u32 reg_ofs, u16 *data) 84 { 85 u16 mii_dev_addr; 86 87 /* command to read PHY dev address */ 88 if (miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr)) { 89 printf("Error..could not read PHY dev address\n"); 90 return; 91 } 92 mv88e61xx_busychk_multic(name, mii_dev_addr); 93 /* Write command to Switch indirect command register (read) */ 94 miiphy_write(name, mii_dev_addr, 0x0, 95 reg_ofs | (phy_adr << 5) | (1 << 11) | (1 << 12) | (1 << 96 15)); 97 mv88e61xx_busychk_multic(name, mii_dev_addr); 98 /* Read data from Switch indirect data register */ 99 miiphy_read(name, mii_dev_addr, 0x1, data); 100 } 101 #endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ 102 103 /* 104 * Convenience macros for switch device/port reads/writes 105 * These macros output valid 'mv88e61xx' U_BOOT_CMDs 106 */ 107 108 #ifndef DEBUG 109 #define WR_SWITCH_REG wr_switch_reg 110 #define RD_SWITCH_REG rd_switch_reg 111 #define WR_SWITCH_PORT_REG(n, p, r, d) \ 112 WR_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) 113 #define RD_SWITCH_PORT_REG(n, p, r, d) \ 114 RD_SWITCH_REG(n, (MV88E61XX_PRT_OFST+p), r, d) 115 #else 116 static void WR_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 data) 117 { 118 printf("mv88e61xx %s dev %02x reg %02x write %04x\n", 119 name, dev_adr, reg_ofs, data); 120 wr_switch_reg(name, dev_adr, reg_ofs, data); 121 } 122 static void RD_SWITCH_REG(char *name, u32 dev_adr, u32 reg_ofs, u16 *data) 123 { 124 rd_switch_reg(name, dev_adr, reg_ofs, data); 125 printf("mv88e61xx %s dev %02x reg %02x read %04x\n", 126 name, dev_adr, reg_ofs, *data); 127 } 128 static void WR_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, 129 u16 data) 130 { 131 printf("mv88e61xx %s port %02x reg %02x write %04x\n", 132 name, prt_adr, reg_ofs, data); 133 wr_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); 134 } 135 static void RD_SWITCH_PORT_REG(char *name, u32 prt_adr, u32 reg_ofs, 136 u16 *data) 137 { 138 rd_switch_reg(name, (MV88E61XX_PRT_OFST+prt_adr), reg_ofs, data); 139 printf("mv88e61xx %s port %02x reg %02x read %04x\n", 140 name, prt_adr, reg_ofs, *data); 141 } 142 #endif 143 144 /* 145 * Local functions to read/write registers on the switch PHYs. 146 * NOTE! This goes through switch, not direct miiphy, writes and reads! 147 */ 148 149 /* 150 * Make sure SMIBusy bit cleared before another 151 * SMI operation can take place 152 */ 153 static int mv88e61xx_busychk(char *name) 154 { 155 u16 reg = 0; 156 u32 timeout = MV88E61XX_PHY_TIMEOUT; 157 do { 158 rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, 159 MV88E61XX_PHY_CMD, ®); 160 if (timeout-- == 0) { 161 printf("SMI busy timeout\n"); 162 return -1; 163 } 164 } while (reg & 1 << 15); /* busy mask */ 165 return 0; 166 } 167 168 static inline int mv88e61xx_switch_miiphy_write(char *name, u32 phy, 169 u32 reg, u16 data) 170 { 171 /* write switch data reg then cmd reg then check completion */ 172 wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, 173 data); 174 wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, 175 (MV88E61XX_PHY_WRITE_CMD | (phy << 5) | reg)); 176 return mv88e61xx_busychk(name); 177 } 178 179 static inline int mv88e61xx_switch_miiphy_read(char *name, u32 phy, 180 u32 reg, u16 *data) 181 { 182 /* write switch cmd reg, check for completion */ 183 wr_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_CMD, 184 (MV88E61XX_PHY_READ_CMD | (phy << 5) | reg)); 185 if (mv88e61xx_busychk(name)) 186 return -1; 187 /* read switch data reg and return success */ 188 rd_switch_reg(name, MV88E61XX_GLB2REG_DEVADR, MV88E61XX_PHY_DATA, data); 189 return 0; 190 } 191 192 /* 193 * Convenience macros for switch PHY reads/writes 194 */ 195 196 #ifndef DEBUG 197 #define WR_SWITCH_PHY_REG mv88e61xx_switch_miiphy_write 198 #define RD_SWITCH_PHY_REG mv88e61xx_switch_miiphy_read 199 #else 200 static inline int WR_SWITCH_PHY_REG(char *name, u32 phy_adr, 201 u32 reg_ofs, u16 data) 202 { 203 int r = mv88e61xx_switch_miiphy_write(name, phy_adr, reg_ofs, data); 204 if (r) 205 printf("** ERROR writing mv88e61xx %s phy %02x reg %02x\n", 206 name, phy_adr, reg_ofs); 207 else 208 printf("mv88e61xx %s phy %02x reg %02x write %04x\n", 209 name, phy_adr, reg_ofs, data); 210 return r; 211 } 212 static inline int RD_SWITCH_PHY_REG(char *name, u32 phy_adr, 213 u32 reg_ofs, u16 *data) 214 { 215 int r = mv88e61xx_switch_miiphy_read(name, phy_adr, reg_ofs, data); 216 if (r) 217 printf("** ERROR reading mv88e61xx %s phy %02x reg %02x\n", 218 name, phy_adr, reg_ofs); 219 else 220 printf("mv88e61xx %s phy %02x reg %02x read %04x\n", 221 name, phy_adr, reg_ofs, *data); 222 return r; 223 } 224 #endif 225 226 static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig) 227 { 228 u32 prt; 229 u16 reg; 230 char *name = swconfig->name; 231 u32 port_mask = swconfig->ports_enabled; 232 233 /* apply internal vlan config */ 234 for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { 235 /* only for enabled ports */ 236 if ((1 << prt) & port_mask) { 237 /* take vlan map from swconfig */ 238 u8 vlanmap = swconfig->vlancfg[prt]; 239 /* remove disabled ports from vlan map */ 240 vlanmap &= swconfig->ports_enabled; 241 /* apply vlan map to port */ 242 RD_SWITCH_PORT_REG(name, prt, 243 MV88E61XX_PRT_VMAP_REG, ®); 244 reg &= ~((1 << MV88E61XX_MAX_PORTS_NUM) - 1); 245 reg |= vlanmap; 246 WR_SWITCH_PORT_REG(name, prt, 247 MV88E61XX_PRT_VMAP_REG, reg); 248 } 249 } 250 } 251 252 /* 253 * Power up the specified port and reset PHY 254 */ 255 static int mv88361xx_powerup(struct mv88e61xx_config *swconfig, u32 phy) 256 { 257 char *name = swconfig->name; 258 259 /* Write Copper Specific control reg1 (0x10) for- 260 * Enable Phy power up 261 * Energy Detect on (sense&Xmit NLP Periodically 262 * reset other settings default 263 */ 264 if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x3360)) 265 return -1; 266 267 /* Write PHY ctrl reg (0x0) to apply 268 * Phy reset (set bit 15 low) 269 * reset other default values 270 */ 271 if (WR_SWITCH_PHY_REG(name, phy, 0x00, 0x9140)) 272 return -1; 273 274 return 0; 275 } 276 277 /* 278 * Default Setup for LED[0]_Control (ref: Table 46 Datasheet-3) 279 * is set to "On-1000Mb/s Link, Off Else" 280 * This function sets it to "On-Link, Blink-Activity, Off-NoLink" 281 * 282 * This is optional settings may be needed on some boards 283 * to setup PHY LEDs default configuration to detect 10/100/1000Mb/s 284 * Link status 285 */ 286 static int mv88361xx_led_init(struct mv88e61xx_config *swconfig, u32 phy) 287 { 288 char *name = swconfig->name; 289 290 if (swconfig->led_init != MV88E61XX_LED_INIT_EN) 291 return 0; 292 293 /* set page address to 3 */ 294 if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0003)) 295 return -1; 296 297 /* 298 * set LED Func Ctrl reg 299 * value 0x0001 = LED[0] On-Link, Blink-Activity, Off-NoLink 300 */ 301 if (WR_SWITCH_PHY_REG(name, phy, 0x10, 0x0001)) 302 return -1; 303 304 /* set page address to 0 */ 305 if (WR_SWITCH_PHY_REG(name, phy, 0x16, 0x0000)) 306 return -1; 307 308 return 0; 309 } 310 311 /* 312 * Reverse Transmit polarity for Media Dependent Interface 313 * Pins (MDIP) bits in Copper Specific Control Register 3 314 * (Page 0, Reg 20 for each phy (except cpu port) 315 * Reference: Section 1.1 Switch datasheet-3 316 * 317 * This is optional settings may be needed on some boards 318 * for PHY<->magnetics h/w tuning 319 */ 320 static int mv88361xx_reverse_mdipn(struct mv88e61xx_config *swconfig, u32 phy) 321 { 322 char *name = swconfig->name; 323 324 if (swconfig->mdip != MV88E61XX_MDIP_REVERSE) 325 return 0; 326 327 /*Reverse MDIP/N[3:0] bits */ 328 if (WR_SWITCH_PHY_REG(name, phy, 0x14, 0x000f)) 329 return -1; 330 331 return 0; 332 } 333 334 /* 335 * Marvell 88E61XX Switch initialization 336 */ 337 int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig) 338 { 339 u32 prt; 340 u16 reg; 341 char *idstr; 342 char *name = swconfig->name; 343 int time; 344 345 if (miiphy_set_current_dev(name)) { 346 printf("%s failed\n", __FUNCTION__); 347 return -1; 348 } 349 350 if (!(swconfig->cpuport & ((1 << 4) | (1 << 5)))) { 351 swconfig->cpuport = (1 << 5); 352 printf("Invalid cpu port config, using default port5\n"); 353 } 354 355 RD_SWITCH_PORT_REG(name, 0, MII_PHYSID2, ®); 356 switch (reg &= 0xfff0) { 357 case 0x1610: 358 idstr = "88E6161"; 359 break; 360 case 0x1650: 361 idstr = "88E6165"; 362 break; 363 case 0x1210: 364 idstr = "88E6123"; 365 /* ports 2,3,4 not available */ 366 swconfig->ports_enabled &= 0x023; 367 break; 368 default: 369 /* Could not detect switch id */ 370 idstr = "88E61??"; 371 break; 372 } 373 374 /* be sure all ports are disabled */ 375 for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { 376 RD_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, ®); 377 reg &= ~0x3; 378 WR_SWITCH_PORT_REG(name, prt, MV88E61XX_PRT_CTRL_REG, reg); 379 } 380 381 /* wait 2 ms for queues to drain */ 382 udelay(2000); 383 384 /* reset switch */ 385 RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, ®); 386 reg |= 0x8000; 387 WR_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGCR, reg); 388 389 /* wait up to 1 second for switch reset complete */ 390 for (time = 1000; time; time--) { 391 RD_SWITCH_REG(name, MV88E61XX_GLBREG_DEVADR, MV88E61XX_SGSR, 392 ®); 393 if ((reg & 0xc800) == 0xc800) 394 break; 395 udelay(1000); 396 } 397 if (!time) 398 return -1; 399 400 /* Port based VLANs configuration */ 401 mv88e61xx_port_vlan_config(swconfig); 402 403 if (swconfig->rgmii_delay == MV88E61XX_RGMII_DELAY_EN) { 404 /* 405 * Enable RGMII delay on Tx and Rx for CPU port 406 * Ref: sec 9.5 of chip datasheet-02 407 */ 408 /*Force port link down */ 409 WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x10); 410 /* configure port RGMII delay */ 411 WR_SWITCH_PORT_REG(name, 4, 412 MV88E61XX_RGMII_TIMECTRL_REG, 0x81e7); 413 RD_SWITCH_PORT_REG(name, 5, 414 MV88E61XX_RGMII_TIMECTRL_REG, ®); 415 WR_SWITCH_PORT_REG(name, 5, 416 MV88E61XX_RGMII_TIMECTRL_REG, reg | 0x18); 417 WR_SWITCH_PORT_REG(name, 4, 418 MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); 419 /* Force port to RGMII FDX 1000Base then up */ 420 WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x1e); 421 WR_SWITCH_PORT_REG(name, 5, MV88E61XX_PCS_CTRL_REG, 0x3e); 422 } 423 424 for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { 425 426 /* configure port's PHY */ 427 if (!((1 << prt) & swconfig->cpuport)) { 428 /* port 4 has phy 6, not 4 */ 429 int phy = (prt == 4) ? 6 : prt; 430 if (mv88361xx_powerup(swconfig, phy)) 431 return -1; 432 if (mv88361xx_reverse_mdipn(swconfig, phy)) 433 return -1; 434 if (mv88361xx_led_init(swconfig, phy)) 435 return -1; 436 } 437 438 /* set port VID to port+1 except for cpu port */ 439 if (!((1 << prt) & swconfig->cpuport)) { 440 RD_SWITCH_PORT_REG(name, prt, 441 MV88E61XX_PRT_VID_REG, ®); 442 WR_SWITCH_PORT_REG(name, prt, 443 MV88E61XX_PRT_VID_REG, 444 (reg & ~1023) | (prt+1)); 445 } 446 447 /*Program port state */ 448 RD_SWITCH_PORT_REG(name, prt, 449 MV88E61XX_PRT_CTRL_REG, ®); 450 WR_SWITCH_PORT_REG(name, prt, 451 MV88E61XX_PRT_CTRL_REG, 452 reg | (swconfig->portstate & 0x03)); 453 454 } 455 456 printf("%s Initialized on %s\n", idstr, name); 457 return 0; 458 } 459 460 #ifdef CONFIG_MV88E61XX_CMD 461 static int 462 do_switch(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 463 { 464 char *name, *endp; 465 int write = 0; 466 enum { dev, prt, phy } target = dev; 467 u32 addrlo, addrhi, addr; 468 u32 reglo, reghi, reg; 469 u16 data, rdata; 470 471 if (argc < 7) 472 return -1; 473 474 name = argv[1]; 475 476 if (strcmp(argv[2], "phy") == 0) 477 target = phy; 478 else if (strcmp(argv[2], "port") == 0) 479 target = prt; 480 else if (strcmp(argv[2], "dev") != 0) 481 return 1; 482 483 addrlo = simple_strtoul(argv[3], &endp, 16); 484 485 if (!*endp) { 486 addrhi = addrlo; 487 } else { 488 while (*endp < '0' || *endp > '9') 489 endp++; 490 addrhi = simple_strtoul(endp, NULL, 16); 491 } 492 493 reglo = simple_strtoul(argv[5], &endp, 16); 494 if (!*endp) { 495 reghi = reglo; 496 } else { 497 while (*endp < '0' || *endp > '9') 498 endp++; 499 reghi = simple_strtoul(endp, NULL, 16); 500 } 501 502 if (strcmp(argv[6], "write") == 0) 503 write = 1; 504 else if (strcmp(argv[6], "read") != 0) 505 return 1; 506 507 data = simple_strtoul(argv[7], NULL, 16); 508 509 for (addr = addrlo; addr <= addrhi; addr++) { 510 for (reg = reglo; reg <= reghi; reg++) { 511 if (write) { 512 if (target == phy) 513 mv88e61xx_switch_miiphy_write( 514 name, addr, reg, data); 515 else if (target == prt) 516 wr_switch_reg(name, 517 addr+MV88E61XX_PRT_OFST, 518 reg, data); 519 else 520 wr_switch_reg(name, addr, reg, data); 521 } else { 522 if (target == phy) 523 mv88e61xx_switch_miiphy_read( 524 name, addr, reg, &rdata); 525 else if (target == prt) 526 rd_switch_reg(name, 527 addr+MV88E61XX_PRT_OFST, 528 reg, &rdata); 529 else 530 rd_switch_reg(name, addr, reg, &rdata); 531 printf("%s %s %s %02x %s %02x %s %04x\n", 532 argv[0], argv[1], argv[2], addr, 533 argv[4], reg, argv[6], rdata); 534 if (write && argc == 7 && rdata != data) 535 return 1; 536 } 537 } 538 } 539 return 0; 540 } 541 542 U_BOOT_CMD(mv88e61xx, 8, 0, do_switch, 543 "Read or write mv88e61xx switch registers", 544 "<ethdevice> dev|port|phy <addr> reg <reg> write <data>\n" 545 "<ethdevice> dev|port|phy <addr> reg <reg> read [<data>]\n" 546 " - read/write switch device, port or phy at (addr,reg)\n" 547 " addr=0..0x1C for dev, 0..5 for port or phy.\n" 548 " reg=0..0x1F.\n" 549 " data=0..0xFFFF (tested if present against actual read).\n" 550 " All numeric parameters are assumed to be hex.\n" 551 " <addr> and <<reg> arguments can be ranges (x..y)" 552 ); 553 #endif /* CONFIG_MV88E61XX_CMD */ 554