1 /* 2 * Marvell PHY drivers 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Copyright 2010-2011 Freescale Semiconductor, Inc. 7 * author Andy Fleming 8 */ 9 #include <config.h> 10 #include <common.h> 11 #include <errno.h> 12 #include <phy.h> 13 14 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 15 16 /* 88E1011 PHY Status Register */ 17 #define MIIM_88E1xxx_PHY_STATUS 0x11 18 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 19 #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000 20 #define MIIM_88E1xxx_PHYSTAT_100 0x4000 21 #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000 22 #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800 23 #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400 24 25 #define MIIM_88E1xxx_PHY_SCR 0x10 26 #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060 27 28 /* 88E1111 PHY LED Control Register */ 29 #define MIIM_88E1111_PHY_LED_CONTROL 24 30 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100 31 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C 32 33 /* 88E1111 Extended PHY Specific Control Register */ 34 #define MIIM_88E1111_PHY_EXT_CR 0x14 35 #define MIIM_88E1111_RX_DELAY 0x80 36 #define MIIM_88E1111_TX_DELAY 0x2 37 38 /* 88E1111 Extended PHY Specific Status Register */ 39 #define MIIM_88E1111_PHY_EXT_SR 0x1b 40 #define MIIM_88E1111_HWCFG_MODE_MASK 0xf 41 #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb 42 #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3 43 #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4 44 #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9 45 #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000 46 #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000 47 48 #define MIIM_88E1111_COPPER 0 49 #define MIIM_88E1111_FIBER 1 50 51 /* 88E1118 PHY defines */ 52 #define MIIM_88E1118_PHY_PAGE 22 53 #define MIIM_88E1118_PHY_LED_PAGE 3 54 55 /* 88E1121 PHY LED Control Register */ 56 #define MIIM_88E1121_PHY_LED_CTRL 16 57 #define MIIM_88E1121_PHY_LED_PAGE 3 58 #define MIIM_88E1121_PHY_LED_DEF 0x0030 59 60 /* 88E1121 PHY IRQ Enable/Status Register */ 61 #define MIIM_88E1121_PHY_IRQ_EN 18 62 #define MIIM_88E1121_PHY_IRQ_STATUS 19 63 64 #define MIIM_88E1121_PHY_PAGE 22 65 66 /* 88E1145 Extended PHY Specific Control Register */ 67 #define MIIM_88E1145_PHY_EXT_CR 20 68 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 69 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 70 71 #define MIIM_88E1145_PHY_LED_CONTROL 24 72 #define MIIM_88E1145_PHY_LED_DIRECT 0x4100 73 74 #define MIIM_88E1145_PHY_PAGE 29 75 #define MIIM_88E1145_PHY_CAL_OV 30 76 77 #define MIIM_88E1149_PHY_PAGE 29 78 79 /* 88E1310 PHY defines */ 80 #define MIIM_88E1310_PHY_LED_CTRL 16 81 #define MIIM_88E1310_PHY_IRQ_EN 18 82 #define MIIM_88E1310_PHY_RGMII_CTRL 21 83 #define MIIM_88E1310_PHY_PAGE 22 84 85 /* Marvell 88E1011S */ 86 static int m88e1011s_config(struct phy_device *phydev) 87 { 88 /* Reset and configure the PHY */ 89 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 90 91 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 92 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); 93 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 94 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); 95 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 96 97 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 98 99 genphy_config_aneg(phydev); 100 101 return 0; 102 } 103 104 /* Parse the 88E1011's status register for speed and duplex 105 * information 106 */ 107 static int m88e1xxx_parse_status(struct phy_device *phydev) 108 { 109 unsigned int speed; 110 unsigned int mii_reg; 111 112 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); 113 114 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) && 115 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { 116 int i = 0; 117 118 puts("Waiting for PHY realtime link"); 119 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { 120 /* Timeout reached ? */ 121 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 122 puts(" TIMEOUT !\n"); 123 phydev->link = 0; 124 return -ETIMEDOUT; 125 } 126 127 if ((i++ % 1000) == 0) 128 putc('.'); 129 udelay(1000); 130 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, 131 MIIM_88E1xxx_PHY_STATUS); 132 } 133 puts(" done\n"); 134 udelay(500000); /* another 500 ms (results in faster booting) */ 135 } else { 136 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) 137 phydev->link = 1; 138 else 139 phydev->link = 0; 140 } 141 142 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX) 143 phydev->duplex = DUPLEX_FULL; 144 else 145 phydev->duplex = DUPLEX_HALF; 146 147 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED; 148 149 switch (speed) { 150 case MIIM_88E1xxx_PHYSTAT_GBIT: 151 phydev->speed = SPEED_1000; 152 break; 153 case MIIM_88E1xxx_PHYSTAT_100: 154 phydev->speed = SPEED_100; 155 break; 156 default: 157 phydev->speed = SPEED_10; 158 break; 159 } 160 161 return 0; 162 } 163 164 static int m88e1011s_startup(struct phy_device *phydev) 165 { 166 int ret; 167 168 ret = genphy_update_link(phydev); 169 if (ret) 170 return ret; 171 172 return m88e1xxx_parse_status(phydev); 173 } 174 175 /* Marvell 88E1111S */ 176 static int m88e1111s_config(struct phy_device *phydev) 177 { 178 int reg; 179 180 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || 181 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || 182 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || 183 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 184 reg = phy_read(phydev, 185 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); 186 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || 187 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { 188 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); 189 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 190 reg &= ~MIIM_88E1111_TX_DELAY; 191 reg |= MIIM_88E1111_RX_DELAY; 192 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 193 reg &= ~MIIM_88E1111_RX_DELAY; 194 reg |= MIIM_88E1111_TX_DELAY; 195 } 196 197 phy_write(phydev, 198 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); 199 200 reg = phy_read(phydev, 201 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); 202 203 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); 204 205 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES) 206 reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII; 207 else 208 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII; 209 210 phy_write(phydev, 211 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg); 212 } 213 214 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 215 reg = phy_read(phydev, 216 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); 217 218 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); 219 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; 220 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 221 222 phy_write(phydev, MDIO_DEVAD_NONE, 223 MIIM_88E1111_PHY_EXT_SR, reg); 224 } 225 226 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { 227 reg = phy_read(phydev, 228 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); 229 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); 230 phy_write(phydev, 231 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); 232 233 reg = phy_read(phydev, MDIO_DEVAD_NONE, 234 MIIM_88E1111_PHY_EXT_SR); 235 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | 236 MIIM_88E1111_HWCFG_FIBER_COPPER_RES); 237 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 238 phy_write(phydev, MDIO_DEVAD_NONE, 239 MIIM_88E1111_PHY_EXT_SR, reg); 240 241 /* soft reset */ 242 phy_reset(phydev); 243 244 reg = phy_read(phydev, MDIO_DEVAD_NONE, 245 MIIM_88E1111_PHY_EXT_SR); 246 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | 247 MIIM_88E1111_HWCFG_FIBER_COPPER_RES); 248 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | 249 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 250 phy_write(phydev, MDIO_DEVAD_NONE, 251 MIIM_88E1111_PHY_EXT_SR, reg); 252 } 253 254 /* soft reset */ 255 phy_reset(phydev); 256 257 genphy_config_aneg(phydev); 258 genphy_restart_aneg(phydev); 259 260 return 0; 261 } 262 263 /** 264 * m88e1518_phy_writebits - write bits to a register 265 */ 266 void m88e1518_phy_writebits(struct phy_device *phydev, 267 u8 reg_num, u16 offset, u16 len, u16 data) 268 { 269 u16 reg, mask; 270 271 if ((len + offset) >= 16) 272 mask = 0 - (1 << offset); 273 else 274 mask = (1 << (len + offset)) - (1 << offset); 275 276 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); 277 278 reg &= ~mask; 279 reg |= data << offset; 280 281 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); 282 } 283 284 static int m88e1518_config(struct phy_device *phydev) 285 { 286 /* 287 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 288 * /88E1514 Rev A0, Errata Section 3.1 289 */ 290 291 /* EEE initialization */ 292 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); 293 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); 294 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); 295 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); 296 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146); 297 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233); 298 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); 299 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); 300 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); 301 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); 302 303 /* SGMII-to-Copper mode initialization */ 304 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 305 /* Select page 18 */ 306 phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); 307 308 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */ 309 m88e1518_phy_writebits(phydev, 20, 0, 3, 1); 310 311 /* PHY reset is necessary after changing MODE[2:0] */ 312 m88e1518_phy_writebits(phydev, 20, 15, 1, 1); 313 314 /* Reset page selection */ 315 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); 316 317 udelay(100); 318 } 319 320 return m88e1111s_config(phydev); 321 } 322 323 /* Marvell 88E1510 */ 324 static int m88e1510_config(struct phy_device *phydev) 325 { 326 /* Select page 3 */ 327 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); 328 329 /* Enable INTn output on LED[2] */ 330 m88e1518_phy_writebits(phydev, 18, 7, 1, 1); 331 332 /* Configure LEDs */ 333 m88e1518_phy_writebits(phydev, 16, 0, 4, 3); /* LED[0]:0011 (ACT) */ 334 m88e1518_phy_writebits(phydev, 16, 4, 4, 6); /* LED[1]:0110 (LINK) */ 335 336 /* Reset page selection */ 337 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); 338 339 return m88e1518_config(phydev); 340 } 341 342 /* Marvell 88E1118 */ 343 static int m88e1118_config(struct phy_device *phydev) 344 { 345 /* Change Page Number */ 346 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002); 347 /* Delay RGMII TX and RX */ 348 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070); 349 /* Change Page Number */ 350 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003); 351 /* Adjust LED control */ 352 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e); 353 /* Change Page Number */ 354 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 355 356 return genphy_config_aneg(phydev); 357 } 358 359 static int m88e1118_startup(struct phy_device *phydev) 360 { 361 int ret; 362 363 /* Change Page Number */ 364 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 365 366 ret = genphy_update_link(phydev); 367 if (ret) 368 return ret; 369 370 return m88e1xxx_parse_status(phydev); 371 } 372 373 /* Marvell 88E1121R */ 374 static int m88e1121_config(struct phy_device *phydev) 375 { 376 int pg; 377 378 /* Configure the PHY */ 379 genphy_config_aneg(phydev); 380 381 /* Switch the page to access the led register */ 382 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE); 383 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, 384 MIIM_88E1121_PHY_LED_PAGE); 385 /* Configure leds */ 386 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL, 387 MIIM_88E1121_PHY_LED_DEF); 388 /* Restore the page pointer */ 389 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg); 390 391 /* Disable IRQs and de-assert interrupt */ 392 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0); 393 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS); 394 395 return 0; 396 } 397 398 /* Marvell 88E1145 */ 399 static int m88e1145_config(struct phy_device *phydev) 400 { 401 int reg; 402 403 /* Errata E0, E1 */ 404 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b); 405 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f); 406 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016); 407 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da); 408 409 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR, 410 MIIM_88E1xxx_PHY_MDI_X_AUTO); 411 412 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR); 413 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 414 reg |= MIIM_M88E1145_RGMII_RX_DELAY | 415 MIIM_M88E1145_RGMII_TX_DELAY; 416 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg); 417 418 genphy_config_aneg(phydev); 419 420 phy_reset(phydev); 421 422 return 0; 423 } 424 425 static int m88e1145_startup(struct phy_device *phydev) 426 { 427 int ret; 428 429 ret = genphy_update_link(phydev); 430 if (ret) 431 return ret; 432 433 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, 434 MIIM_88E1145_PHY_LED_DIRECT); 435 return m88e1xxx_parse_status(phydev); 436 } 437 438 /* Marvell 88E1149S */ 439 static int m88e1149_config(struct phy_device *phydev) 440 { 441 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f); 442 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); 443 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5); 444 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0); 445 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 446 447 genphy_config_aneg(phydev); 448 449 phy_reset(phydev); 450 451 return 0; 452 } 453 454 /* Marvell 88E1310 */ 455 static int m88e1310_config(struct phy_device *phydev) 456 { 457 u16 reg; 458 459 /* LED link and activity */ 460 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); 461 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL); 462 reg = (reg & ~0xf) | 0x1; 463 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg); 464 465 /* Set LED2/INT to INT mode, low active */ 466 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); 467 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN); 468 reg = (reg & 0x77ff) | 0x0880; 469 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg); 470 471 /* Set RGMII delay */ 472 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002); 473 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL); 474 reg |= 0x0030; 475 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg); 476 477 /* Ensure to return to page 0 */ 478 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000); 479 480 return genphy_config_aneg(phydev); 481 } 482 483 static struct phy_driver M88E1011S_driver = { 484 .name = "Marvell 88E1011S", 485 .uid = 0x1410c60, 486 .mask = 0xffffff0, 487 .features = PHY_GBIT_FEATURES, 488 .config = &m88e1011s_config, 489 .startup = &m88e1011s_startup, 490 .shutdown = &genphy_shutdown, 491 }; 492 493 static struct phy_driver M88E1111S_driver = { 494 .name = "Marvell 88E1111S", 495 .uid = 0x1410cc0, 496 .mask = 0xffffff0, 497 .features = PHY_GBIT_FEATURES, 498 .config = &m88e1111s_config, 499 .startup = &m88e1011s_startup, 500 .shutdown = &genphy_shutdown, 501 }; 502 503 static struct phy_driver M88E1118_driver = { 504 .name = "Marvell 88E1118", 505 .uid = 0x1410e10, 506 .mask = 0xffffff0, 507 .features = PHY_GBIT_FEATURES, 508 .config = &m88e1118_config, 509 .startup = &m88e1118_startup, 510 .shutdown = &genphy_shutdown, 511 }; 512 513 static struct phy_driver M88E1118R_driver = { 514 .name = "Marvell 88E1118R", 515 .uid = 0x1410e40, 516 .mask = 0xffffff0, 517 .features = PHY_GBIT_FEATURES, 518 .config = &m88e1118_config, 519 .startup = &m88e1118_startup, 520 .shutdown = &genphy_shutdown, 521 }; 522 523 static struct phy_driver M88E1121R_driver = { 524 .name = "Marvell 88E1121R", 525 .uid = 0x1410cb0, 526 .mask = 0xffffff0, 527 .features = PHY_GBIT_FEATURES, 528 .config = &m88e1121_config, 529 .startup = &genphy_startup, 530 .shutdown = &genphy_shutdown, 531 }; 532 533 static struct phy_driver M88E1145_driver = { 534 .name = "Marvell 88E1145", 535 .uid = 0x1410cd0, 536 .mask = 0xffffff0, 537 .features = PHY_GBIT_FEATURES, 538 .config = &m88e1145_config, 539 .startup = &m88e1145_startup, 540 .shutdown = &genphy_shutdown, 541 }; 542 543 static struct phy_driver M88E1149S_driver = { 544 .name = "Marvell 88E1149S", 545 .uid = 0x1410ca0, 546 .mask = 0xffffff0, 547 .features = PHY_GBIT_FEATURES, 548 .config = &m88e1149_config, 549 .startup = &m88e1011s_startup, 550 .shutdown = &genphy_shutdown, 551 }; 552 553 static struct phy_driver M88E1510_driver = { 554 .name = "Marvell 88E1510", 555 .uid = 0x1410dd0, 556 .mask = 0xffffff0, 557 .features = PHY_GBIT_FEATURES, 558 .config = &m88e1510_config, 559 .startup = &m88e1011s_startup, 560 .shutdown = &genphy_shutdown, 561 }; 562 563 static struct phy_driver M88E1518_driver = { 564 .name = "Marvell 88E1518", 565 .uid = 0x1410dd1, 566 .mask = 0xffffff0, 567 .features = PHY_GBIT_FEATURES, 568 .config = &m88e1518_config, 569 .startup = &m88e1011s_startup, 570 .shutdown = &genphy_shutdown, 571 }; 572 573 static struct phy_driver M88E1310_driver = { 574 .name = "Marvell 88E1310", 575 .uid = 0x01410e90, 576 .mask = 0xffffff0, 577 .features = PHY_GBIT_FEATURES, 578 .config = &m88e1310_config, 579 .startup = &m88e1011s_startup, 580 .shutdown = &genphy_shutdown, 581 }; 582 583 int phy_marvell_init(void) 584 { 585 phy_register(&M88E1310_driver); 586 phy_register(&M88E1149S_driver); 587 phy_register(&M88E1145_driver); 588 phy_register(&M88E1121R_driver); 589 phy_register(&M88E1118_driver); 590 phy_register(&M88E1118R_driver); 591 phy_register(&M88E1111S_driver); 592 phy_register(&M88E1011S_driver); 593 phy_register(&M88E1510_driver); 594 phy_register(&M88E1518_driver); 595 596 return 0; 597 } 598