1 /* 2 * Marvell PHY drivers 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Copyright 2010-2011 Freescale Semiconductor, Inc. 7 * author Andy Fleming 8 */ 9 #include <config.h> 10 #include <common.h> 11 #include <errno.h> 12 #include <phy.h> 13 14 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 15 16 #define MII_MARVELL_PHY_PAGE 22 17 18 /* 88E1011 PHY Status Register */ 19 #define MIIM_88E1xxx_PHY_STATUS 0x11 20 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 21 #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000 22 #define MIIM_88E1xxx_PHYSTAT_100 0x4000 23 #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000 24 #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800 25 #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400 26 27 #define MIIM_88E1xxx_PHY_SCR 0x10 28 #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060 29 30 /* 88E1111 PHY LED Control Register */ 31 #define MIIM_88E1111_PHY_LED_CONTROL 24 32 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100 33 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C 34 35 /* 88E1111 Extended PHY Specific Control Register */ 36 #define MIIM_88E1111_PHY_EXT_CR 0x14 37 #define MIIM_88E1111_RX_DELAY 0x80 38 #define MIIM_88E1111_TX_DELAY 0x2 39 40 /* 88E1111 Extended PHY Specific Status Register */ 41 #define MIIM_88E1111_PHY_EXT_SR 0x1b 42 #define MIIM_88E1111_HWCFG_MODE_MASK 0xf 43 #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb 44 #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3 45 #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4 46 #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9 47 #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000 48 #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000 49 50 #define MIIM_88E1111_COPPER 0 51 #define MIIM_88E1111_FIBER 1 52 53 /* 88E1118 PHY defines */ 54 #define MIIM_88E1118_PHY_PAGE 22 55 #define MIIM_88E1118_PHY_LED_PAGE 3 56 57 /* 88E1121 PHY LED Control Register */ 58 #define MIIM_88E1121_PHY_LED_CTRL 16 59 #define MIIM_88E1121_PHY_LED_PAGE 3 60 #define MIIM_88E1121_PHY_LED_DEF 0x0030 61 62 /* 88E1121 PHY IRQ Enable/Status Register */ 63 #define MIIM_88E1121_PHY_IRQ_EN 18 64 #define MIIM_88E1121_PHY_IRQ_STATUS 19 65 66 #define MIIM_88E1121_PHY_PAGE 22 67 68 /* 88E1145 Extended PHY Specific Control Register */ 69 #define MIIM_88E1145_PHY_EXT_CR 20 70 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 71 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 72 73 #define MIIM_88E1145_PHY_LED_CONTROL 24 74 #define MIIM_88E1145_PHY_LED_DIRECT 0x4100 75 76 #define MIIM_88E1145_PHY_PAGE 29 77 #define MIIM_88E1145_PHY_CAL_OV 30 78 79 #define MIIM_88E1149_PHY_PAGE 29 80 81 /* 88E1310 PHY defines */ 82 #define MIIM_88E1310_PHY_LED_CTRL 16 83 #define MIIM_88E1310_PHY_IRQ_EN 18 84 #define MIIM_88E1310_PHY_RGMII_CTRL 21 85 #define MIIM_88E1310_PHY_PAGE 22 86 87 /* 88E151x PHY defines */ 88 /* Page 2 registers */ 89 #define MIIM_88E151x_PHY_MSCR 21 90 #define MIIM_88E151x_RGMII_RX_DELAY BIT(5) 91 #define MIIM_88E151x_RGMII_TX_DELAY BIT(4) 92 #define MIIM_88E151x_RGMII_RXTX_DELAY (BIT(5) | BIT(4)) 93 /* Page 3 registers */ 94 #define MIIM_88E151x_LED_FUNC_CTRL 16 95 #define MIIM_88E151x_LED_FLD_SZ 4 96 #define MIIM_88E151x_LED0_OFFS (0 * MIIM_88E151x_LED_FLD_SZ) 97 #define MIIM_88E151x_LED1_OFFS (1 * MIIM_88E151x_LED_FLD_SZ) 98 #define MIIM_88E151x_LED0_ACT 3 99 #define MIIM_88E151x_LED1_100_1000_LINK 6 100 #define MIIM_88E151x_LED_TIMER_CTRL 18 101 #define MIIM_88E151x_INT_EN_OFFS 7 102 /* Page 18 registers */ 103 #define MIIM_88E151x_GENERAL_CTRL 20 104 #define MIIM_88E151x_MODE_SGMII 1 105 #define MIIM_88E151x_RESET_OFFS 15 106 107 static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr, 108 int devaddr, int regnum) 109 { 110 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); 111 int val; 112 113 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); 114 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); 115 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); 116 117 return val; 118 } 119 120 static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr, 121 int devaddr, int regnum, u16 val) 122 { 123 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); 124 125 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); 126 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); 127 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); 128 129 return 0; 130 } 131 132 /* Marvell 88E1011S */ 133 static int m88e1011s_config(struct phy_device *phydev) 134 { 135 /* Reset and configure the PHY */ 136 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 137 138 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 139 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); 140 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 141 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); 142 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 143 144 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 145 146 genphy_config_aneg(phydev); 147 148 return 0; 149 } 150 151 /* Parse the 88E1011's status register for speed and duplex 152 * information 153 */ 154 static int m88e1xxx_parse_status(struct phy_device *phydev) 155 { 156 unsigned int speed; 157 unsigned int mii_reg; 158 159 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); 160 161 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) && 162 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { 163 int i = 0; 164 165 puts("Waiting for PHY realtime link"); 166 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { 167 /* Timeout reached ? */ 168 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 169 puts(" TIMEOUT !\n"); 170 phydev->link = 0; 171 return -ETIMEDOUT; 172 } 173 174 if ((i++ % 1000) == 0) 175 putc('.'); 176 udelay(1000); 177 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, 178 MIIM_88E1xxx_PHY_STATUS); 179 } 180 puts(" done\n"); 181 mdelay(500); /* another 500 ms (results in faster booting) */ 182 } else { 183 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) 184 phydev->link = 1; 185 else 186 phydev->link = 0; 187 } 188 189 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX) 190 phydev->duplex = DUPLEX_FULL; 191 else 192 phydev->duplex = DUPLEX_HALF; 193 194 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED; 195 196 switch (speed) { 197 case MIIM_88E1xxx_PHYSTAT_GBIT: 198 phydev->speed = SPEED_1000; 199 break; 200 case MIIM_88E1xxx_PHYSTAT_100: 201 phydev->speed = SPEED_100; 202 break; 203 default: 204 phydev->speed = SPEED_10; 205 break; 206 } 207 208 return 0; 209 } 210 211 static int m88e1011s_startup(struct phy_device *phydev) 212 { 213 int ret; 214 215 ret = genphy_update_link(phydev); 216 if (ret) 217 return ret; 218 219 return m88e1xxx_parse_status(phydev); 220 } 221 222 /* Marvell 88E1111S */ 223 static int m88e1111s_config(struct phy_device *phydev) 224 { 225 int reg; 226 227 if (phy_interface_is_rgmii(phydev)) { 228 reg = phy_read(phydev, 229 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); 230 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || 231 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { 232 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); 233 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 234 reg &= ~MIIM_88E1111_TX_DELAY; 235 reg |= MIIM_88E1111_RX_DELAY; 236 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 237 reg &= ~MIIM_88E1111_RX_DELAY; 238 reg |= MIIM_88E1111_TX_DELAY; 239 } 240 241 phy_write(phydev, 242 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); 243 244 reg = phy_read(phydev, 245 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); 246 247 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); 248 249 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES) 250 reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII; 251 else 252 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII; 253 254 phy_write(phydev, 255 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg); 256 } 257 258 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 259 reg = phy_read(phydev, 260 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); 261 262 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); 263 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; 264 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 265 266 phy_write(phydev, MDIO_DEVAD_NONE, 267 MIIM_88E1111_PHY_EXT_SR, reg); 268 } 269 270 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { 271 reg = phy_read(phydev, 272 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); 273 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); 274 phy_write(phydev, 275 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); 276 277 reg = phy_read(phydev, MDIO_DEVAD_NONE, 278 MIIM_88E1111_PHY_EXT_SR); 279 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | 280 MIIM_88E1111_HWCFG_FIBER_COPPER_RES); 281 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 282 phy_write(phydev, MDIO_DEVAD_NONE, 283 MIIM_88E1111_PHY_EXT_SR, reg); 284 285 /* soft reset */ 286 phy_reset(phydev); 287 288 reg = phy_read(phydev, MDIO_DEVAD_NONE, 289 MIIM_88E1111_PHY_EXT_SR); 290 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | 291 MIIM_88E1111_HWCFG_FIBER_COPPER_RES); 292 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | 293 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 294 phy_write(phydev, MDIO_DEVAD_NONE, 295 MIIM_88E1111_PHY_EXT_SR, reg); 296 } 297 298 /* soft reset */ 299 phy_reset(phydev); 300 301 genphy_config_aneg(phydev); 302 genphy_restart_aneg(phydev); 303 304 return 0; 305 } 306 307 /** 308 * m88e1518_phy_writebits - write bits to a register 309 */ 310 void m88e1518_phy_writebits(struct phy_device *phydev, 311 u8 reg_num, u16 offset, u16 len, u16 data) 312 { 313 u16 reg, mask; 314 315 if ((len + offset) >= 16) 316 mask = 0 - (1 << offset); 317 else 318 mask = (1 << (len + offset)) - (1 << offset); 319 320 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); 321 322 reg &= ~mask; 323 reg |= data << offset; 324 325 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); 326 } 327 328 static int m88e1518_config(struct phy_device *phydev) 329 { 330 u16 reg; 331 332 /* 333 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 334 * /88E1514 Rev A0, Errata Section 3.1 335 */ 336 337 /* EEE initialization */ 338 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); 339 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); 340 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); 341 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); 342 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146); 343 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233); 344 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); 345 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); 346 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); 347 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 348 349 /* SGMII-to-Copper mode initialization */ 350 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 351 /* Select page 18 */ 352 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18); 353 354 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */ 355 m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, 356 0, 3, MIIM_88E151x_MODE_SGMII); 357 358 /* PHY reset is necessary after changing MODE[2:0] */ 359 m88e1518_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, 360 MIIM_88E151x_RESET_OFFS, 1, 1); 361 362 /* Reset page selection */ 363 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0); 364 365 udelay(100); 366 } 367 368 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 369 reg = phy_read(phydev, MDIO_DEVAD_NONE, 370 MIIM_88E1111_PHY_EXT_SR); 371 372 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); 373 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; 374 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 375 376 phy_write(phydev, MDIO_DEVAD_NONE, 377 MIIM_88E1111_PHY_EXT_SR, reg); 378 } 379 380 if (phy_interface_is_rgmii(phydev)) { 381 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2); 382 383 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR); 384 reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY; 385 if (phydev->interface == PHY_INTERFACE_MODE_RGMII || 386 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 387 reg |= MIIM_88E151x_RGMII_RXTX_DELAY; 388 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 389 reg |= MIIM_88E151x_RGMII_RX_DELAY; 390 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 391 reg |= MIIM_88E151x_RGMII_TX_DELAY; 392 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg); 393 394 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0); 395 } 396 397 /* soft reset */ 398 phy_reset(phydev); 399 400 genphy_config_aneg(phydev); 401 genphy_restart_aneg(phydev); 402 403 return 0; 404 } 405 406 /* Marvell 88E1510 */ 407 static int m88e1510_config(struct phy_device *phydev) 408 { 409 /* Select page 3 */ 410 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 411 MIIM_88E1118_PHY_LED_PAGE); 412 413 /* Enable INTn output on LED[2] */ 414 m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_TIMER_CTRL, 415 MIIM_88E151x_INT_EN_OFFS, 1, 1); 416 417 /* Configure LEDs */ 418 /* LED[0]:0011 (ACT) */ 419 m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL, 420 MIIM_88E151x_LED0_OFFS, MIIM_88E151x_LED_FLD_SZ, 421 MIIM_88E151x_LED0_ACT); 422 /* LED[1]:0110 (LINK 100/1000 Mbps) */ 423 m88e1518_phy_writebits(phydev, MIIM_88E151x_LED_FUNC_CTRL, 424 MIIM_88E151x_LED1_OFFS, MIIM_88E151x_LED_FLD_SZ, 425 MIIM_88E151x_LED1_100_1000_LINK); 426 427 /* Reset page selection */ 428 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0); 429 430 return m88e1518_config(phydev); 431 } 432 433 /* Marvell 88E1118 */ 434 static int m88e1118_config(struct phy_device *phydev) 435 { 436 /* Change Page Number */ 437 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002); 438 /* Delay RGMII TX and RX */ 439 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070); 440 /* Change Page Number */ 441 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003); 442 /* Adjust LED control */ 443 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e); 444 /* Change Page Number */ 445 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 446 447 return genphy_config_aneg(phydev); 448 } 449 450 static int m88e1118_startup(struct phy_device *phydev) 451 { 452 int ret; 453 454 /* Change Page Number */ 455 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 456 457 ret = genphy_update_link(phydev); 458 if (ret) 459 return ret; 460 461 return m88e1xxx_parse_status(phydev); 462 } 463 464 /* Marvell 88E1121R */ 465 static int m88e1121_config(struct phy_device *phydev) 466 { 467 int pg; 468 469 /* Configure the PHY */ 470 genphy_config_aneg(phydev); 471 472 /* Switch the page to access the led register */ 473 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE); 474 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, 475 MIIM_88E1121_PHY_LED_PAGE); 476 /* Configure leds */ 477 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL, 478 MIIM_88E1121_PHY_LED_DEF); 479 /* Restore the page pointer */ 480 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg); 481 482 /* Disable IRQs and de-assert interrupt */ 483 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0); 484 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS); 485 486 return 0; 487 } 488 489 /* Marvell 88E1145 */ 490 static int m88e1145_config(struct phy_device *phydev) 491 { 492 int reg; 493 494 /* Errata E0, E1 */ 495 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b); 496 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f); 497 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016); 498 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da); 499 500 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR, 501 MIIM_88E1xxx_PHY_MDI_X_AUTO); 502 503 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR); 504 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 505 reg |= MIIM_M88E1145_RGMII_RX_DELAY | 506 MIIM_M88E1145_RGMII_TX_DELAY; 507 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg); 508 509 genphy_config_aneg(phydev); 510 511 /* soft reset */ 512 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 513 reg |= BMCR_RESET; 514 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); 515 516 return 0; 517 } 518 519 static int m88e1145_startup(struct phy_device *phydev) 520 { 521 int ret; 522 523 ret = genphy_update_link(phydev); 524 if (ret) 525 return ret; 526 527 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, 528 MIIM_88E1145_PHY_LED_DIRECT); 529 return m88e1xxx_parse_status(phydev); 530 } 531 532 /* Marvell 88E1149S */ 533 static int m88e1149_config(struct phy_device *phydev) 534 { 535 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f); 536 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); 537 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5); 538 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0); 539 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 540 541 genphy_config_aneg(phydev); 542 543 phy_reset(phydev); 544 545 return 0; 546 } 547 548 /* Marvell 88E1310 */ 549 static int m88e1310_config(struct phy_device *phydev) 550 { 551 u16 reg; 552 553 /* LED link and activity */ 554 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); 555 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL); 556 reg = (reg & ~0xf) | 0x1; 557 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg); 558 559 /* Set LED2/INT to INT mode, low active */ 560 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); 561 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN); 562 reg = (reg & 0x77ff) | 0x0880; 563 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg); 564 565 /* Set RGMII delay */ 566 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002); 567 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL); 568 reg |= 0x0030; 569 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg); 570 571 /* Ensure to return to page 0 */ 572 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000); 573 574 return genphy_config_aneg(phydev); 575 } 576 577 static int m88e1680_config(struct phy_device *phydev) 578 { 579 /* 580 * As per Marvell Release Notes - Alaska V 88E1680 Rev A2 581 * Errata Section 4.1 582 */ 583 u16 reg; 584 int res; 585 586 /* Matrix LED mode (not neede if single LED mode is used */ 587 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004); 588 reg = phy_read(phydev, MDIO_DEVAD_NONE, 27); 589 reg |= (1 << 5); 590 phy_write(phydev, MDIO_DEVAD_NONE, 27, reg); 591 592 /* QSGMII TX amplitude change */ 593 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd); 594 phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53); 595 phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d); 596 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 597 598 /* EEE initialization */ 599 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); 600 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030); 601 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c); 602 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc); 603 phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c); 604 phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c); 605 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 606 phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); 607 608 res = genphy_config_aneg(phydev); 609 if (res < 0) 610 return res; 611 612 /* soft reset */ 613 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 614 reg |= BMCR_RESET; 615 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); 616 617 return 0; 618 } 619 620 static struct phy_driver M88E1011S_driver = { 621 .name = "Marvell 88E1011S", 622 .uid = 0x1410c60, 623 .mask = 0xffffff0, 624 .features = PHY_GBIT_FEATURES, 625 .config = &m88e1011s_config, 626 .startup = &m88e1011s_startup, 627 .shutdown = &genphy_shutdown, 628 }; 629 630 static struct phy_driver M88E1111S_driver = { 631 .name = "Marvell 88E1111S", 632 .uid = 0x1410cc0, 633 .mask = 0xffffff0, 634 .features = PHY_GBIT_FEATURES, 635 .config = &m88e1111s_config, 636 .startup = &m88e1011s_startup, 637 .shutdown = &genphy_shutdown, 638 }; 639 640 static struct phy_driver M88E1118_driver = { 641 .name = "Marvell 88E1118", 642 .uid = 0x1410e10, 643 .mask = 0xffffff0, 644 .features = PHY_GBIT_FEATURES, 645 .config = &m88e1118_config, 646 .startup = &m88e1118_startup, 647 .shutdown = &genphy_shutdown, 648 }; 649 650 static struct phy_driver M88E1118R_driver = { 651 .name = "Marvell 88E1118R", 652 .uid = 0x1410e40, 653 .mask = 0xffffff0, 654 .features = PHY_GBIT_FEATURES, 655 .config = &m88e1118_config, 656 .startup = &m88e1118_startup, 657 .shutdown = &genphy_shutdown, 658 }; 659 660 static struct phy_driver M88E1121R_driver = { 661 .name = "Marvell 88E1121R", 662 .uid = 0x1410cb0, 663 .mask = 0xffffff0, 664 .features = PHY_GBIT_FEATURES, 665 .config = &m88e1121_config, 666 .startup = &genphy_startup, 667 .shutdown = &genphy_shutdown, 668 }; 669 670 static struct phy_driver M88E1145_driver = { 671 .name = "Marvell 88E1145", 672 .uid = 0x1410cd0, 673 .mask = 0xffffff0, 674 .features = PHY_GBIT_FEATURES, 675 .config = &m88e1145_config, 676 .startup = &m88e1145_startup, 677 .shutdown = &genphy_shutdown, 678 }; 679 680 static struct phy_driver M88E1149S_driver = { 681 .name = "Marvell 88E1149S", 682 .uid = 0x1410ca0, 683 .mask = 0xffffff0, 684 .features = PHY_GBIT_FEATURES, 685 .config = &m88e1149_config, 686 .startup = &m88e1011s_startup, 687 .shutdown = &genphy_shutdown, 688 }; 689 690 static struct phy_driver M88E1510_driver = { 691 .name = "Marvell 88E1510", 692 .uid = 0x1410dd0, 693 .mask = 0xfffffff, 694 .features = PHY_GBIT_FEATURES, 695 .config = &m88e1510_config, 696 .startup = &m88e1011s_startup, 697 .shutdown = &genphy_shutdown, 698 .readext = &m88e1xxx_phy_extread, 699 .writeext = &m88e1xxx_phy_extwrite, 700 }; 701 702 /* 703 * This supports: 704 * 88E1518, uid 0x1410dd1 705 * 88E1512, uid 0x1410dd4 706 */ 707 static struct phy_driver M88E1518_driver = { 708 .name = "Marvell 88E1518", 709 .uid = 0x1410dd0, 710 .mask = 0xffffffa, 711 .features = PHY_GBIT_FEATURES, 712 .config = &m88e1518_config, 713 .startup = &m88e1011s_startup, 714 .shutdown = &genphy_shutdown, 715 .readext = &m88e1xxx_phy_extread, 716 .writeext = &m88e1xxx_phy_extwrite, 717 }; 718 719 static struct phy_driver M88E1310_driver = { 720 .name = "Marvell 88E1310", 721 .uid = 0x01410e90, 722 .mask = 0xffffff0, 723 .features = PHY_GBIT_FEATURES, 724 .config = &m88e1310_config, 725 .startup = &m88e1011s_startup, 726 .shutdown = &genphy_shutdown, 727 }; 728 729 static struct phy_driver M88E1680_driver = { 730 .name = "Marvell 88E1680", 731 .uid = 0x1410ed0, 732 .mask = 0xffffff0, 733 .features = PHY_GBIT_FEATURES, 734 .config = &m88e1680_config, 735 .startup = &genphy_startup, 736 .shutdown = &genphy_shutdown, 737 }; 738 739 int phy_marvell_init(void) 740 { 741 phy_register(&M88E1310_driver); 742 phy_register(&M88E1149S_driver); 743 phy_register(&M88E1145_driver); 744 phy_register(&M88E1121R_driver); 745 phy_register(&M88E1118_driver); 746 phy_register(&M88E1118R_driver); 747 phy_register(&M88E1111S_driver); 748 phy_register(&M88E1011S_driver); 749 phy_register(&M88E1510_driver); 750 phy_register(&M88E1518_driver); 751 phy_register(&M88E1680_driver); 752 753 return 0; 754 } 755