1 /* 2 * Marvell PHY drivers 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Copyright 2010-2011 Freescale Semiconductor, Inc. 7 * author Andy Fleming 8 */ 9 #include <config.h> 10 #include <common.h> 11 #include <phy.h> 12 13 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 14 15 /* 88E1011 PHY Status Register */ 16 #define MIIM_88E1xxx_PHY_STATUS 0x11 17 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 18 #define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000 19 #define MIIM_88E1xxx_PHYSTAT_100 0x4000 20 #define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000 21 #define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800 22 #define MIIM_88E1xxx_PHYSTAT_LINK 0x0400 23 24 #define MIIM_88E1xxx_PHY_SCR 0x10 25 #define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060 26 27 /* 88E1111 PHY LED Control Register */ 28 #define MIIM_88E1111_PHY_LED_CONTROL 24 29 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100 30 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C 31 32 /* 88E1111 Extended PHY Specific Control Register */ 33 #define MIIM_88E1111_PHY_EXT_CR 0x14 34 #define MIIM_88E1111_RX_DELAY 0x80 35 #define MIIM_88E1111_TX_DELAY 0x2 36 37 /* 88E1111 Extended PHY Specific Status Register */ 38 #define MIIM_88E1111_PHY_EXT_SR 0x1b 39 #define MIIM_88E1111_HWCFG_MODE_MASK 0xf 40 #define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb 41 #define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3 42 #define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4 43 #define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9 44 #define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000 45 #define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000 46 47 #define MIIM_88E1111_COPPER 0 48 #define MIIM_88E1111_FIBER 1 49 50 /* 88E1118 PHY defines */ 51 #define MIIM_88E1118_PHY_PAGE 22 52 #define MIIM_88E1118_PHY_LED_PAGE 3 53 54 /* 88E1121 PHY LED Control Register */ 55 #define MIIM_88E1121_PHY_LED_CTRL 16 56 #define MIIM_88E1121_PHY_LED_PAGE 3 57 #define MIIM_88E1121_PHY_LED_DEF 0x0030 58 59 /* 88E1121 PHY IRQ Enable/Status Register */ 60 #define MIIM_88E1121_PHY_IRQ_EN 18 61 #define MIIM_88E1121_PHY_IRQ_STATUS 19 62 63 #define MIIM_88E1121_PHY_PAGE 22 64 65 /* 88E1145 Extended PHY Specific Control Register */ 66 #define MIIM_88E1145_PHY_EXT_CR 20 67 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 68 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 69 70 #define MIIM_88E1145_PHY_LED_CONTROL 24 71 #define MIIM_88E1145_PHY_LED_DIRECT 0x4100 72 73 #define MIIM_88E1145_PHY_PAGE 29 74 #define MIIM_88E1145_PHY_CAL_OV 30 75 76 #define MIIM_88E1149_PHY_PAGE 29 77 78 /* 88E1310 PHY defines */ 79 #define MIIM_88E1310_PHY_LED_CTRL 16 80 #define MIIM_88E1310_PHY_IRQ_EN 18 81 #define MIIM_88E1310_PHY_RGMII_CTRL 21 82 #define MIIM_88E1310_PHY_PAGE 22 83 84 /* Marvell 88E1011S */ 85 static int m88e1011s_config(struct phy_device *phydev) 86 { 87 /* Reset and configure the PHY */ 88 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 89 90 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); 91 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); 92 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 93 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0); 94 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 95 96 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 97 98 genphy_config_aneg(phydev); 99 100 return 0; 101 } 102 103 /* Parse the 88E1011's status register for speed and duplex 104 * information 105 */ 106 static uint m88e1xxx_parse_status(struct phy_device *phydev) 107 { 108 unsigned int speed; 109 unsigned int mii_reg; 110 111 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); 112 113 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) && 114 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { 115 int i = 0; 116 117 puts("Waiting for PHY realtime link"); 118 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { 119 /* Timeout reached ? */ 120 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 121 puts(" TIMEOUT !\n"); 122 phydev->link = 0; 123 break; 124 } 125 126 if ((i++ % 1000) == 0) 127 putc('.'); 128 udelay(1000); 129 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, 130 MIIM_88E1xxx_PHY_STATUS); 131 } 132 puts(" done\n"); 133 udelay(500000); /* another 500 ms (results in faster booting) */ 134 } else { 135 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) 136 phydev->link = 1; 137 else 138 phydev->link = 0; 139 } 140 141 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX) 142 phydev->duplex = DUPLEX_FULL; 143 else 144 phydev->duplex = DUPLEX_HALF; 145 146 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED; 147 148 switch (speed) { 149 case MIIM_88E1xxx_PHYSTAT_GBIT: 150 phydev->speed = SPEED_1000; 151 break; 152 case MIIM_88E1xxx_PHYSTAT_100: 153 phydev->speed = SPEED_100; 154 break; 155 default: 156 phydev->speed = SPEED_10; 157 break; 158 } 159 160 return 0; 161 } 162 163 static int m88e1011s_startup(struct phy_device *phydev) 164 { 165 genphy_update_link(phydev); 166 m88e1xxx_parse_status(phydev); 167 168 return 0; 169 } 170 171 /* Marvell 88E1111S */ 172 static int m88e1111s_config(struct phy_device *phydev) 173 { 174 int reg; 175 int timeout; 176 177 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || 178 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || 179 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || 180 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 181 reg = phy_read(phydev, 182 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); 183 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || 184 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { 185 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); 186 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { 187 reg &= ~MIIM_88E1111_TX_DELAY; 188 reg |= MIIM_88E1111_RX_DELAY; 189 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { 190 reg &= ~MIIM_88E1111_RX_DELAY; 191 reg |= MIIM_88E1111_TX_DELAY; 192 } 193 194 phy_write(phydev, 195 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); 196 197 reg = phy_read(phydev, 198 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); 199 200 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); 201 202 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES) 203 reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII; 204 else 205 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII; 206 207 phy_write(phydev, 208 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg); 209 } 210 211 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 212 reg = phy_read(phydev, 213 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); 214 215 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); 216 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; 217 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 218 219 phy_write(phydev, MDIO_DEVAD_NONE, 220 MIIM_88E1111_PHY_EXT_SR, reg); 221 } 222 223 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { 224 reg = phy_read(phydev, 225 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); 226 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); 227 phy_write(phydev, 228 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); 229 230 reg = phy_read(phydev, MDIO_DEVAD_NONE, 231 MIIM_88E1111_PHY_EXT_SR); 232 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | 233 MIIM_88E1111_HWCFG_FIBER_COPPER_RES); 234 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 235 phy_write(phydev, MDIO_DEVAD_NONE, 236 MIIM_88E1111_PHY_EXT_SR, reg); 237 238 /* soft reset */ 239 timeout = 1000; 240 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 241 udelay(1000); 242 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 243 while ((reg & BMCR_RESET) && --timeout) { 244 udelay(1000); 245 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 246 } 247 if (!timeout) 248 printf("%s: phy soft reset timeout\n", __func__); 249 250 reg = phy_read(phydev, MDIO_DEVAD_NONE, 251 MIIM_88E1111_PHY_EXT_SR); 252 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | 253 MIIM_88E1111_HWCFG_FIBER_COPPER_RES); 254 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | 255 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; 256 phy_write(phydev, MDIO_DEVAD_NONE, 257 MIIM_88E1111_PHY_EXT_SR, reg); 258 } 259 260 /* soft reset */ 261 timeout = 1000; 262 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); 263 udelay(1000); 264 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 265 while ((reg & BMCR_RESET) && --timeout) { 266 udelay(1000); 267 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 268 } 269 if (!timeout) 270 printf("%s: phy soft reset timeout\n", __func__); 271 272 genphy_config_aneg(phydev); 273 274 phy_reset(phydev); 275 276 return 0; 277 } 278 279 /** 280 * m88e1518_phy_writebits - write bits to a register 281 */ 282 void m88e1518_phy_writebits(struct phy_device *phydev, 283 u8 reg_num, u16 offset, u16 len, u16 data) 284 { 285 u16 reg, mask; 286 287 if ((len + offset) >= 16) 288 mask = 0 - (1 << offset); 289 else 290 mask = (1 << (len + offset)) - (1 << offset); 291 292 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); 293 294 reg &= ~mask; 295 reg |= data << offset; 296 297 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); 298 } 299 300 static int m88e1518_config(struct phy_device *phydev) 301 { 302 /* 303 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 304 * /88E1514 Rev A0, Errata Section 3.1 305 */ 306 307 /* EEE initialization */ 308 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); 309 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); 310 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); 311 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); 312 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146); 313 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233); 314 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); 315 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); 316 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); 317 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); 318 319 /* SGMII-to-Copper mode initialization */ 320 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 321 /* Select page 18 */ 322 phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); 323 324 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */ 325 m88e1518_phy_writebits(phydev, 20, 0, 3, 1); 326 327 /* PHY reset is necessary after changing MODE[2:0] */ 328 m88e1518_phy_writebits(phydev, 20, 15, 1, 1); 329 330 /* Reset page selection */ 331 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); 332 333 udelay(100); 334 } 335 336 return m88e1111s_config(phydev); 337 } 338 339 /* Marvell 88E1510 */ 340 static int m88e1510_config(struct phy_device *phydev) 341 { 342 /* Select page 3 */ 343 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); 344 345 /* Enable INTn output on LED[2] */ 346 m88e1518_phy_writebits(phydev, 18, 7, 1, 1); 347 348 /* Configure LEDs */ 349 m88e1518_phy_writebits(phydev, 16, 0, 4, 3); /* LED[0]:0011 (ACT) */ 350 m88e1518_phy_writebits(phydev, 16, 4, 4, 6); /* LED[1]:0110 (LINK) */ 351 352 /* Reset page selection */ 353 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); 354 355 return m88e1518_config(phydev); 356 } 357 358 /* Marvell 88E1118 */ 359 static int m88e1118_config(struct phy_device *phydev) 360 { 361 /* Change Page Number */ 362 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002); 363 /* Delay RGMII TX and RX */ 364 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070); 365 /* Change Page Number */ 366 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003); 367 /* Adjust LED control */ 368 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e); 369 /* Change Page Number */ 370 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 371 372 genphy_config_aneg(phydev); 373 374 phy_reset(phydev); 375 376 return 0; 377 } 378 379 static int m88e1118_startup(struct phy_device *phydev) 380 { 381 /* Change Page Number */ 382 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); 383 384 genphy_update_link(phydev); 385 m88e1xxx_parse_status(phydev); 386 387 return 0; 388 } 389 390 /* Marvell 88E1121R */ 391 static int m88e1121_config(struct phy_device *phydev) 392 { 393 int pg; 394 395 /* Configure the PHY */ 396 genphy_config_aneg(phydev); 397 398 /* Switch the page to access the led register */ 399 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE); 400 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, 401 MIIM_88E1121_PHY_LED_PAGE); 402 /* Configure leds */ 403 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL, 404 MIIM_88E1121_PHY_LED_DEF); 405 /* Restore the page pointer */ 406 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg); 407 408 /* Disable IRQs and de-assert interrupt */ 409 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0); 410 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS); 411 412 return 0; 413 } 414 415 /* Marvell 88E1145 */ 416 static int m88e1145_config(struct phy_device *phydev) 417 { 418 int reg; 419 420 /* Errata E0, E1 */ 421 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b); 422 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f); 423 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016); 424 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da); 425 426 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR, 427 MIIM_88E1xxx_PHY_MDI_X_AUTO); 428 429 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR); 430 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 431 reg |= MIIM_M88E1145_RGMII_RX_DELAY | 432 MIIM_M88E1145_RGMII_TX_DELAY; 433 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg); 434 435 genphy_config_aneg(phydev); 436 437 phy_reset(phydev); 438 439 return 0; 440 } 441 442 static int m88e1145_startup(struct phy_device *phydev) 443 { 444 genphy_update_link(phydev); 445 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, 446 MIIM_88E1145_PHY_LED_DIRECT); 447 m88e1xxx_parse_status(phydev); 448 449 return 0; 450 } 451 452 /* Marvell 88E1149S */ 453 static int m88e1149_config(struct phy_device *phydev) 454 { 455 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f); 456 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c); 457 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5); 458 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0); 459 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); 460 461 genphy_config_aneg(phydev); 462 463 phy_reset(phydev); 464 465 return 0; 466 } 467 468 /* Marvell 88E1310 */ 469 static int m88e1310_config(struct phy_device *phydev) 470 { 471 u16 reg; 472 473 /* LED link and activity */ 474 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); 475 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL); 476 reg = (reg & ~0xf) | 0x1; 477 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg); 478 479 /* Set LED2/INT to INT mode, low active */ 480 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003); 481 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN); 482 reg = (reg & 0x77ff) | 0x0880; 483 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg); 484 485 /* Set RGMII delay */ 486 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002); 487 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL); 488 reg |= 0x0030; 489 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg); 490 491 /* Ensure to return to page 0 */ 492 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000); 493 494 genphy_config_aneg(phydev); 495 phy_reset(phydev); 496 497 return 0; 498 } 499 500 static struct phy_driver M88E1011S_driver = { 501 .name = "Marvell 88E1011S", 502 .uid = 0x1410c60, 503 .mask = 0xffffff0, 504 .features = PHY_GBIT_FEATURES, 505 .config = &m88e1011s_config, 506 .startup = &m88e1011s_startup, 507 .shutdown = &genphy_shutdown, 508 }; 509 510 static struct phy_driver M88E1111S_driver = { 511 .name = "Marvell 88E1111S", 512 .uid = 0x1410cc0, 513 .mask = 0xffffff0, 514 .features = PHY_GBIT_FEATURES, 515 .config = &m88e1111s_config, 516 .startup = &m88e1011s_startup, 517 .shutdown = &genphy_shutdown, 518 }; 519 520 static struct phy_driver M88E1118_driver = { 521 .name = "Marvell 88E1118", 522 .uid = 0x1410e10, 523 .mask = 0xffffff0, 524 .features = PHY_GBIT_FEATURES, 525 .config = &m88e1118_config, 526 .startup = &m88e1118_startup, 527 .shutdown = &genphy_shutdown, 528 }; 529 530 static struct phy_driver M88E1118R_driver = { 531 .name = "Marvell 88E1118R", 532 .uid = 0x1410e40, 533 .mask = 0xffffff0, 534 .features = PHY_GBIT_FEATURES, 535 .config = &m88e1118_config, 536 .startup = &m88e1118_startup, 537 .shutdown = &genphy_shutdown, 538 }; 539 540 static struct phy_driver M88E1121R_driver = { 541 .name = "Marvell 88E1121R", 542 .uid = 0x1410cb0, 543 .mask = 0xffffff0, 544 .features = PHY_GBIT_FEATURES, 545 .config = &m88e1121_config, 546 .startup = &genphy_startup, 547 .shutdown = &genphy_shutdown, 548 }; 549 550 static struct phy_driver M88E1145_driver = { 551 .name = "Marvell 88E1145", 552 .uid = 0x1410cd0, 553 .mask = 0xffffff0, 554 .features = PHY_GBIT_FEATURES, 555 .config = &m88e1145_config, 556 .startup = &m88e1145_startup, 557 .shutdown = &genphy_shutdown, 558 }; 559 560 static struct phy_driver M88E1149S_driver = { 561 .name = "Marvell 88E1149S", 562 .uid = 0x1410ca0, 563 .mask = 0xffffff0, 564 .features = PHY_GBIT_FEATURES, 565 .config = &m88e1149_config, 566 .startup = &m88e1011s_startup, 567 .shutdown = &genphy_shutdown, 568 }; 569 570 static struct phy_driver M88E1510_driver = { 571 .name = "Marvell 88E1510", 572 .uid = 0x1410dd0, 573 .mask = 0xffffff0, 574 .features = PHY_GBIT_FEATURES, 575 .config = &m88e1510_config, 576 .startup = &m88e1011s_startup, 577 .shutdown = &genphy_shutdown, 578 }; 579 580 static struct phy_driver M88E1518_driver = { 581 .name = "Marvell 88E1518", 582 .uid = 0x1410dd1, 583 .mask = 0xffffff0, 584 .features = PHY_GBIT_FEATURES, 585 .config = &m88e1518_config, 586 .startup = &m88e1011s_startup, 587 .shutdown = &genphy_shutdown, 588 }; 589 590 static struct phy_driver M88E1310_driver = { 591 .name = "Marvell 88E1310", 592 .uid = 0x01410e90, 593 .mask = 0xffffff0, 594 .features = PHY_GBIT_FEATURES, 595 .config = &m88e1310_config, 596 .startup = &m88e1011s_startup, 597 .shutdown = &genphy_shutdown, 598 }; 599 600 int phy_marvell_init(void) 601 { 602 phy_register(&M88E1310_driver); 603 phy_register(&M88E1149S_driver); 604 phy_register(&M88E1145_driver); 605 phy_register(&M88E1121R_driver); 606 phy_register(&M88E1118_driver); 607 phy_register(&M88E1118R_driver); 608 phy_register(&M88E1111S_driver); 609 phy_register(&M88E1011S_driver); 610 phy_register(&M88E1510_driver); 611 phy_register(&M88E1518_driver); 612 613 return 0; 614 } 615