1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Broadcom PHY drivers 4 * 5 * Copyright 2010-2011 Freescale Semiconductor, Inc. 6 * author Andy Fleming 7 */ 8 #include <common.h> 9 #include <phy.h> 10 11 /* Broadcom BCM54xx -- taken from linux sungem_phy */ 12 #define MIIM_BCM54xx_AUXCNTL 0x18 13 #define MIIM_BCM54xx_AUXCNTL_ENCODE(val) (((val & 0x7) << 12)|(val & 0x7)) 14 #define MIIM_BCM54xx_AUXSTATUS 0x19 15 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 16 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 17 18 #define MIIM_BCM54XX_SHD 0x1c 19 #define MIIM_BCM54XX_SHD_WRITE 0x8000 20 #define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) 21 #define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) 22 #define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \ 23 (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \ 24 MIIM_BCM54XX_SHD_DATA(data)) 25 26 #define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ 27 #define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ 28 #define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ 29 #define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ 30 31 #define MIIM_BCM_AUXCNTL_SHDWSEL_MISC 0x0007 32 #define MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN 0x0800 33 34 #define MIIM_BCM_CHANNEL_WIDTH 0x2000 35 36 static void bcm_phy_write_misc(struct phy_device *phydev, 37 u16 reg, u16 chl, u16 value) 38 { 39 int reg_val; 40 41 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, 42 MIIM_BCM_AUXCNTL_SHDWSEL_MISC); 43 44 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); 45 reg_val |= MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN; 46 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val); 47 48 reg_val = (chl * MIIM_BCM_CHANNEL_WIDTH) | reg; 49 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val); 50 51 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value); 52 } 53 54 /* Broadcom BCM5461S */ 55 static int bcm5461_config(struct phy_device *phydev) 56 { 57 unsigned int mii_reg = 0; 58 genphy_config_aneg(phydev); 59 60 phy_reset(phydev); 61 62 if(phydev->drv->uid == 0x03625d12) { 63 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x0) & ~BIT(10); 64 phy_write(phydev, MDIO_DEVAD_NONE, 0x0, mii_reg); 65 66 //disable skew 67 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, 0x7007); 68 mii_reg = (phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL) & 0x0af0) | 0xf007; 69 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, mii_reg); 70 71 //disable delay 72 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, 0xc00); 73 mii_reg = 0x8c00; 74 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, mii_reg); 75 } else if (phydev->drv->uid == 0x03625e6a) { 76 /* Disable RGMII RXD to RXC Skew */ 77 phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, 0x8c00); 78 79 /* First Switch shadow register selector */ 80 phy_write(phydev, MDIO_DEVAD_NONE, 0x18, 0xf0e7); 81 } 82 83 return 0; 84 } 85 86 static int bcm54xx_parse_status(struct phy_device *phydev) 87 { 88 unsigned int mii_reg; 89 90 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS); 91 92 switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> 93 MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) { 94 case 1: 95 phydev->duplex = DUPLEX_HALF; 96 phydev->speed = SPEED_10; 97 break; 98 case 2: 99 phydev->duplex = DUPLEX_FULL; 100 phydev->speed = SPEED_10; 101 break; 102 case 3: 103 phydev->duplex = DUPLEX_HALF; 104 phydev->speed = SPEED_100; 105 break; 106 case 5: 107 phydev->duplex = DUPLEX_FULL; 108 phydev->speed = SPEED_100; 109 break; 110 case 6: 111 phydev->duplex = DUPLEX_HALF; 112 phydev->speed = SPEED_1000; 113 break; 114 case 7: 115 phydev->duplex = DUPLEX_FULL; 116 phydev->speed = SPEED_1000; 117 break; 118 default: 119 printf("Auto-neg error, defaulting to 10BT/HD\n"); 120 phydev->duplex = DUPLEX_HALF; 121 phydev->speed = SPEED_10; 122 break; 123 } 124 125 return 0; 126 } 127 128 static int bcm54xx_startup(struct phy_device *phydev) 129 { 130 int ret; 131 132 /* Read the Status (2x to make sure link is right) */ 133 ret = genphy_update_link(phydev); 134 if (ret) 135 return ret; 136 137 return bcm54xx_parse_status(phydev); 138 } 139 140 /* Broadcom BCM5482S */ 141 /* 142 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain 143 * circumstances. eg a gigabit TSEC connected to a gigabit switch with 144 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't 145 * link. "Ethernet@Wirespeed" reduces advertised speed until link 146 * can be achieved. 147 */ 148 static u32 bcm5482_read_wirespeed(struct phy_device *phydev, u32 reg) 149 { 150 return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010; 151 } 152 153 static int bcm5482_config(struct phy_device *phydev) 154 { 155 unsigned int reg; 156 157 /* reset the PHY */ 158 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 159 reg |= BMCR_RESET; 160 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); 161 162 /* Setup read from auxilary control shadow register 7 */ 163 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, 164 MIIM_BCM54xx_AUXCNTL_ENCODE(7)); 165 /* Read Misc Control register and or in Ethernet@Wirespeed */ 166 reg = bcm5482_read_wirespeed(phydev, MIIM_BCM54xx_AUXCNTL); 167 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg); 168 169 /* Initial config/enable of secondary SerDes interface */ 170 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, 171 MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf)); 172 /* Write intial value to secondary SerDes Contol */ 173 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, 174 MIIM_BCM54XX_EXP_SEL_SSD | 0); 175 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, 176 BMCR_ANRESTART); 177 /* Enable copper/fiber auto-detect */ 178 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, 179 MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201)); 180 181 genphy_config_aneg(phydev); 182 183 return 0; 184 } 185 186 static int bcm_cygnus_startup(struct phy_device *phydev) 187 { 188 int ret; 189 190 /* Read the Status (2x to make sure link is right) */ 191 ret = genphy_update_link(phydev); 192 if (ret) 193 return ret; 194 195 return genphy_parse_link(phydev); 196 } 197 198 static void bcm_cygnus_afe(struct phy_device *phydev) 199 { 200 /* ensures smdspclk is enabled */ 201 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, 0x0c30); 202 203 /* AFE_VDAC_ICTRL_0 bit 7:4 Iq=1100 for 1g 10bt, normal modes */ 204 bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8); 205 206 /* AFE_HPF_TRIM_OTHERS bit11=1, short cascode for all modes*/ 207 bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803); 208 209 /* AFE_TX_CONFIG_1 bit 7:4 Iq=1100 for test modes */ 210 bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740); 211 212 /* AFE TEMPSEN_OTHERS rcal_HT, rcal_LT 10000 */ 213 bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400); 214 215 /* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */ 216 bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004); 217 218 /* Adjust bias current trim to overcome digital offSet */ 219 phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x02); 220 221 /* make rcal=100, since rdb default is 000 */ 222 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B1); 223 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010); 224 225 /* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */ 226 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0); 227 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010); 228 229 /* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */ 230 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0); 231 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0000); 232 } 233 234 static int bcm_cygnus_config(struct phy_device *phydev) 235 { 236 genphy_config_aneg(phydev); 237 phy_reset(phydev); 238 /* AFE settings for PHY stability */ 239 bcm_cygnus_afe(phydev); 240 /* Forcing aneg after applying the AFE settings */ 241 genphy_restart_aneg(phydev); 242 243 return 0; 244 } 245 246 /* 247 * Find out if PHY is in copper or serdes mode by looking at Expansion Reg 248 * 0x42 - "Operating Mode Status Register" 249 */ 250 static int bcm5482_is_serdes(struct phy_device *phydev) 251 { 252 u16 val; 253 int serdes = 0; 254 255 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, 256 MIIM_BCM54XX_EXP_SEL_ER | 0x42); 257 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); 258 259 switch (val & 0x1f) { 260 case 0x0d: /* RGMII-to-100Base-FX */ 261 case 0x0e: /* RGMII-to-SGMII */ 262 case 0x0f: /* RGMII-to-SerDes */ 263 case 0x12: /* SGMII-to-SerDes */ 264 case 0x13: /* SGMII-to-100Base-FX */ 265 case 0x16: /* SerDes-to-Serdes */ 266 serdes = 1; 267 break; 268 case 0x6: /* RGMII-to-Copper */ 269 case 0x14: /* SGMII-to-Copper */ 270 case 0x17: /* SerDes-to-Copper */ 271 break; 272 default: 273 printf("ERROR, invalid PHY mode (0x%x\n)", val); 274 break; 275 } 276 277 return serdes; 278 } 279 280 /* 281 * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating 282 * Mode Status Register" 283 */ 284 static u32 bcm5482_parse_serdes_sr(struct phy_device *phydev) 285 { 286 u16 val; 287 int i = 0; 288 289 /* Wait 1s for link - Clause 37 autonegotiation happens very fast */ 290 while (1) { 291 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, 292 MIIM_BCM54XX_EXP_SEL_ER | 0x42); 293 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); 294 295 if (val & 0x8000) 296 break; 297 298 if (i++ > 1000) { 299 phydev->link = 0; 300 return 1; 301 } 302 303 udelay(1000); /* 1 ms */ 304 } 305 306 phydev->link = 1; 307 switch ((val >> 13) & 0x3) { 308 case (0x00): 309 phydev->speed = 10; 310 break; 311 case (0x01): 312 phydev->speed = 100; 313 break; 314 case (0x02): 315 phydev->speed = 1000; 316 break; 317 } 318 319 phydev->duplex = (val & 0x1000) == 0x1000; 320 321 return 0; 322 } 323 324 /* 325 * Figure out if BCM5482 is in serdes or copper mode and determine link 326 * configuration accordingly 327 */ 328 static int bcm5482_startup(struct phy_device *phydev) 329 { 330 int ret; 331 332 if (bcm5482_is_serdes(phydev)) { 333 bcm5482_parse_serdes_sr(phydev); 334 phydev->port = PORT_FIBRE; 335 return 0; 336 } 337 338 /* Wait for auto-negotiation to complete or fail */ 339 ret = genphy_update_link(phydev); 340 if (ret) 341 return ret; 342 343 /* Parse BCM54xx copper aux status register */ 344 return bcm54xx_parse_status(phydev); 345 } 346 347 static struct phy_driver BCM54616S_driver = { 348 .name = "Broadcom BCM54616S", 349 .uid = 0x03625d12, 350 .mask = 0xffffffff, 351 .features = PHY_GBIT_FEATURES, 352 .config = &bcm5461_config, 353 .startup = &bcm54xx_startup, 354 .shutdown = &genphy_shutdown, 355 }; 356 357 static struct phy_driver BCM54612_driver = { 358 .name = "Broadcom BCM54612", 359 .uid = 0x03625e6a, 360 .mask = 0xffffffff, 361 .features = PHY_GBIT_FEATURES, 362 .config = &bcm5461_config, 363 .startup = &bcm54xx_startup, 364 .shutdown = &genphy_shutdown, 365 }; 366 367 static struct phy_driver BCM5461S_driver = { 368 .name = "Broadcom BCM5461S", 369 .uid = 0x2060c0, 370 .mask = 0xfffff0, 371 .features = PHY_GBIT_FEATURES, 372 .config = &bcm5461_config, 373 .startup = &bcm54xx_startup, 374 .shutdown = &genphy_shutdown, 375 }; 376 377 static struct phy_driver BCM5464S_driver = { 378 .name = "Broadcom BCM5464S", 379 .uid = 0x2060b0, 380 .mask = 0xfffff0, 381 .features = PHY_GBIT_FEATURES, 382 .config = &bcm5461_config, 383 .startup = &bcm54xx_startup, 384 .shutdown = &genphy_shutdown, 385 }; 386 387 static struct phy_driver BCM5482S_driver = { 388 .name = "Broadcom BCM5482S", 389 .uid = 0x143bcb0, 390 .mask = 0xffffff0, 391 .features = PHY_GBIT_FEATURES, 392 .config = &bcm5482_config, 393 .startup = &bcm5482_startup, 394 .shutdown = &genphy_shutdown, 395 }; 396 397 static struct phy_driver BCM_CYGNUS_driver = { 398 .name = "Broadcom CYGNUS GPHY", 399 .uid = 0xae025200, 400 .mask = 0xfffff0, 401 .features = PHY_GBIT_FEATURES, 402 .config = &bcm_cygnus_config, 403 .startup = &bcm_cygnus_startup, 404 .shutdown = &genphy_shutdown, 405 }; 406 407 int phy_broadcom_init(void) 408 { 409 phy_register(&BCM54616S_driver); 410 phy_register(&BCM54612_driver); 411 phy_register(&BCM5482S_driver); 412 phy_register(&BCM5464S_driver); 413 phy_register(&BCM5461S_driver); 414 phy_register(&BCM_CYGNUS_driver); 415 416 return 0; 417 } 418