1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Broadcom PHY drivers 4 * 5 * Copyright 2010-2011 Freescale Semiconductor, Inc. 6 * author Andy Fleming 7 */ 8 #include <common.h> 9 #include <phy.h> 10 11 /* Broadcom BCM54xx -- taken from linux sungem_phy */ 12 #define MIIM_BCM54xx_AUXCNTL 0x18 13 #define MIIM_BCM54xx_AUXCNTL_ENCODE(val) (((val & 0x7) << 12)|(val & 0x7)) 14 #define MIIM_BCM54xx_AUXSTATUS 0x19 15 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 16 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 17 18 #define MIIM_BCM54XX_SHD 0x1c 19 #define MIIM_BCM54XX_SHD_WRITE 0x8000 20 #define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) 21 #define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) 22 #define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \ 23 (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \ 24 MIIM_BCM54XX_SHD_DATA(data)) 25 26 #define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ 27 #define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ 28 #define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ 29 #define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ 30 31 #define MIIM_BCM_AUXCNTL_SHDWSEL_MISC 0x0007 32 #define MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN 0x0800 33 34 #define MIIM_BCM_CHANNEL_WIDTH 0x2000 35 36 static void bcm_phy_write_misc(struct phy_device *phydev, 37 u16 reg, u16 chl, u16 value) 38 { 39 int reg_val; 40 41 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, 42 MIIM_BCM_AUXCNTL_SHDWSEL_MISC); 43 44 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); 45 reg_val |= MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN; 46 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val); 47 48 reg_val = (chl * MIIM_BCM_CHANNEL_WIDTH) | reg; 49 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val); 50 51 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value); 52 } 53 54 /* Broadcom BCM5461S */ 55 static int bcm5461_config(struct phy_device *phydev) 56 { 57 u32 reg18, reg1c; 58 59 phy_reset(phydev); 60 /* 61 * RX interface delay: reg 0x18, shadow value b'0111: misc control 62 * bit[8] RGMII RXD to RXC skew 63 */ 64 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, 65 MIIM_BCM54xx_AUXCNTL_ENCODE(0x7)); 66 reg18 = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); 67 reg18 &= ~(MIIM_BCM54xx_AUXCNTL_ENCODE(0x7) | BIT(8)); 68 reg18 |= BIT(15) | MIIM_BCM54xx_AUXCNTL_ENCODE(0x7); 69 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 70 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 71 reg18 |= BIT(8); 72 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg18); 73 74 /* 75 * TX interface delay: reg 0x1c, shadow value b'0011: clock alignment control 76 * bit[9] GTXCLK clock delay enable 77 */ 78 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, 79 MIIM_BCM54XX_SHD_VAL(0x3)); 80 reg1c = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD); 81 reg1c &= ~(MIIM_BCM54XX_SHD_VAL(0x1f) | BIT(9)); 82 reg1c |= BIT(15) | MIIM_BCM54XX_SHD_VAL(0x3); 83 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || 84 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 85 reg1c |= BIT(9); 86 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, reg1c); 87 88 genphy_config_aneg(phydev); 89 90 return 0; 91 } 92 93 static int bcm54xx_parse_status(struct phy_device *phydev) 94 { 95 unsigned int mii_reg; 96 97 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS); 98 99 switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> 100 MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) { 101 case 1: 102 phydev->duplex = DUPLEX_HALF; 103 phydev->speed = SPEED_10; 104 break; 105 case 2: 106 phydev->duplex = DUPLEX_FULL; 107 phydev->speed = SPEED_10; 108 break; 109 case 3: 110 phydev->duplex = DUPLEX_HALF; 111 phydev->speed = SPEED_100; 112 break; 113 case 5: 114 phydev->duplex = DUPLEX_FULL; 115 phydev->speed = SPEED_100; 116 break; 117 case 6: 118 phydev->duplex = DUPLEX_HALF; 119 phydev->speed = SPEED_1000; 120 break; 121 case 7: 122 phydev->duplex = DUPLEX_FULL; 123 phydev->speed = SPEED_1000; 124 break; 125 default: 126 printf("Auto-neg error, defaulting to 10BT/HD\n"); 127 phydev->duplex = DUPLEX_HALF; 128 phydev->speed = SPEED_10; 129 break; 130 } 131 132 return 0; 133 } 134 135 static int bcm54xx_startup(struct phy_device *phydev) 136 { 137 int ret; 138 139 /* Read the Status (2x to make sure link is right) */ 140 ret = genphy_update_link(phydev); 141 if (ret) 142 return ret; 143 144 return bcm54xx_parse_status(phydev); 145 } 146 147 /* Broadcom BCM5482S */ 148 /* 149 * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain 150 * circumstances. eg a gigabit TSEC connected to a gigabit switch with 151 * a 4-wire ethernet cable. Both ends advertise gigabit, but can't 152 * link. "Ethernet@Wirespeed" reduces advertised speed until link 153 * can be achieved. 154 */ 155 static u32 bcm5482_read_wirespeed(struct phy_device *phydev, u32 reg) 156 { 157 return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010; 158 } 159 160 static int bcm5482_config(struct phy_device *phydev) 161 { 162 unsigned int reg; 163 164 /* reset the PHY */ 165 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); 166 reg |= BMCR_RESET; 167 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); 168 169 /* Setup read from auxilary control shadow register 7 */ 170 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, 171 MIIM_BCM54xx_AUXCNTL_ENCODE(7)); 172 /* Read Misc Control register and or in Ethernet@Wirespeed */ 173 reg = bcm5482_read_wirespeed(phydev, MIIM_BCM54xx_AUXCNTL); 174 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg); 175 176 /* Initial config/enable of secondary SerDes interface */ 177 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, 178 MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf)); 179 /* Write intial value to secondary SerDes Contol */ 180 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, 181 MIIM_BCM54XX_EXP_SEL_SSD | 0); 182 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, 183 BMCR_ANRESTART); 184 /* Enable copper/fiber auto-detect */ 185 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD, 186 MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201)); 187 188 genphy_config_aneg(phydev); 189 190 return 0; 191 } 192 193 static int bcm_cygnus_startup(struct phy_device *phydev) 194 { 195 int ret; 196 197 /* Read the Status (2x to make sure link is right) */ 198 ret = genphy_update_link(phydev); 199 if (ret) 200 return ret; 201 202 return genphy_parse_link(phydev); 203 } 204 205 static void bcm_cygnus_afe(struct phy_device *phydev) 206 { 207 /* ensures smdspclk is enabled */ 208 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, 0x0c30); 209 210 /* AFE_VDAC_ICTRL_0 bit 7:4 Iq=1100 for 1g 10bt, normal modes */ 211 bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8); 212 213 /* AFE_HPF_TRIM_OTHERS bit11=1, short cascode for all modes*/ 214 bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803); 215 216 /* AFE_TX_CONFIG_1 bit 7:4 Iq=1100 for test modes */ 217 bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740); 218 219 /* AFE TEMPSEN_OTHERS rcal_HT, rcal_LT 10000 */ 220 bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400); 221 222 /* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */ 223 bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004); 224 225 /* Adjust bias current trim to overcome digital offSet */ 226 phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x02); 227 228 /* make rcal=100, since rdb default is 000 */ 229 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B1); 230 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010); 231 232 /* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */ 233 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0); 234 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010); 235 236 /* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */ 237 phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0); 238 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0000); 239 } 240 241 static int bcm_cygnus_config(struct phy_device *phydev) 242 { 243 genphy_config_aneg(phydev); 244 phy_reset(phydev); 245 /* AFE settings for PHY stability */ 246 bcm_cygnus_afe(phydev); 247 /* Forcing aneg after applying the AFE settings */ 248 genphy_restart_aneg(phydev); 249 250 return 0; 251 } 252 253 /* 254 * Find out if PHY is in copper or serdes mode by looking at Expansion Reg 255 * 0x42 - "Operating Mode Status Register" 256 */ 257 static int bcm5482_is_serdes(struct phy_device *phydev) 258 { 259 u16 val; 260 int serdes = 0; 261 262 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, 263 MIIM_BCM54XX_EXP_SEL_ER | 0x42); 264 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); 265 266 switch (val & 0x1f) { 267 case 0x0d: /* RGMII-to-100Base-FX */ 268 case 0x0e: /* RGMII-to-SGMII */ 269 case 0x0f: /* RGMII-to-SerDes */ 270 case 0x12: /* SGMII-to-SerDes */ 271 case 0x13: /* SGMII-to-100Base-FX */ 272 case 0x16: /* SerDes-to-Serdes */ 273 serdes = 1; 274 break; 275 case 0x6: /* RGMII-to-Copper */ 276 case 0x14: /* SGMII-to-Copper */ 277 case 0x17: /* SerDes-to-Copper */ 278 break; 279 default: 280 printf("ERROR, invalid PHY mode (0x%x\n)", val); 281 break; 282 } 283 284 return serdes; 285 } 286 287 /* 288 * Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating 289 * Mode Status Register" 290 */ 291 static u32 bcm5482_parse_serdes_sr(struct phy_device *phydev) 292 { 293 u16 val; 294 int i = 0; 295 296 /* Wait 1s for link - Clause 37 autonegotiation happens very fast */ 297 while (1) { 298 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, 299 MIIM_BCM54XX_EXP_SEL_ER | 0x42); 300 val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA); 301 302 if (val & 0x8000) 303 break; 304 305 if (i++ > 1000) { 306 phydev->link = 0; 307 return 1; 308 } 309 310 udelay(1000); /* 1 ms */ 311 } 312 313 phydev->link = 1; 314 switch ((val >> 13) & 0x3) { 315 case (0x00): 316 phydev->speed = 10; 317 break; 318 case (0x01): 319 phydev->speed = 100; 320 break; 321 case (0x02): 322 phydev->speed = 1000; 323 break; 324 } 325 326 phydev->duplex = (val & 0x1000) == 0x1000; 327 328 return 0; 329 } 330 331 /* 332 * Figure out if BCM5482 is in serdes or copper mode and determine link 333 * configuration accordingly 334 */ 335 static int bcm5482_startup(struct phy_device *phydev) 336 { 337 int ret; 338 339 if (bcm5482_is_serdes(phydev)) { 340 bcm5482_parse_serdes_sr(phydev); 341 phydev->port = PORT_FIBRE; 342 return 0; 343 } 344 345 /* Wait for auto-negotiation to complete or fail */ 346 ret = genphy_update_link(phydev); 347 if (ret) 348 return ret; 349 350 /* Parse BCM54xx copper aux status register */ 351 return bcm54xx_parse_status(phydev); 352 } 353 354 static struct phy_driver BCM54616S_driver = { 355 .name = "Broadcom BCM54616S", 356 .uid = 0x03625d12, 357 .mask = 0xffffffff, 358 .features = PHY_GBIT_FEATURES, 359 .config = &bcm5461_config, 360 .startup = &bcm54xx_startup, 361 .shutdown = &genphy_shutdown, 362 }; 363 364 static struct phy_driver BCM54612_driver = { 365 .name = "Broadcom BCM54612", 366 .uid = 0x03625e6a, 367 .mask = 0xffffffff, 368 .features = PHY_GBIT_FEATURES, 369 .config = &bcm5461_config, 370 .startup = &bcm54xx_startup, 371 .shutdown = &genphy_shutdown, 372 }; 373 374 static struct phy_driver BCM54210E_driver = { 375 .name = "Broadcom BCM54210E", 376 .uid = 0x600d84a0, 377 .mask = 0xfffffff0, 378 .features = PHY_GBIT_FEATURES, 379 .config = &bcm5461_config, 380 .startup = &bcm54xx_startup, 381 .shutdown = &genphy_shutdown, 382 }; 383 384 static struct phy_driver BCM5461S_driver = { 385 .name = "Broadcom BCM5461S", 386 .uid = 0x2060c0, 387 .mask = 0xfffff0, 388 .features = PHY_GBIT_FEATURES, 389 .config = &bcm5461_config, 390 .startup = &bcm54xx_startup, 391 .shutdown = &genphy_shutdown, 392 }; 393 394 static struct phy_driver BCM5464S_driver = { 395 .name = "Broadcom BCM5464S", 396 .uid = 0x2060b0, 397 .mask = 0xfffff0, 398 .features = PHY_GBIT_FEATURES, 399 .config = &bcm5461_config, 400 .startup = &bcm54xx_startup, 401 .shutdown = &genphy_shutdown, 402 }; 403 404 static struct phy_driver BCM5482S_driver = { 405 .name = "Broadcom BCM5482S", 406 .uid = 0x143bcb0, 407 .mask = 0xffffff0, 408 .features = PHY_GBIT_FEATURES, 409 .config = &bcm5482_config, 410 .startup = &bcm5482_startup, 411 .shutdown = &genphy_shutdown, 412 }; 413 414 static struct phy_driver BCM_CYGNUS_driver = { 415 .name = "Broadcom CYGNUS GPHY", 416 .uid = 0xae025200, 417 .mask = 0xfffff0, 418 .features = PHY_GBIT_FEATURES, 419 .config = &bcm_cygnus_config, 420 .startup = &bcm_cygnus_startup, 421 .shutdown = &genphy_shutdown, 422 }; 423 424 int phy_broadcom_init(void) 425 { 426 phy_register(&BCM54616S_driver); 427 phy_register(&BCM54612_driver); 428 phy_register(&BCM54210E_driver); 429 phy_register(&BCM5482S_driver); 430 phy_register(&BCM5464S_driver); 431 phy_register(&BCM5461S_driver); 432 phy_register(&BCM_CYGNUS_driver); 433 434 return 0; 435 } 436