1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Aquantia PHY drivers
4 *
5 * Copyright 2014 Freescale Semiconductor, Inc.
6 * Copyright 2018 NXP
7 */
8 #include <config.h>
9 #include <common.h>
10 #include <dm.h>
11 #include <phy.h>
12 #include <u-boot/crc.h>
13 #include <malloc.h>
14 #include <asm/byteorder.h>
15 #include <fs.h>
16
17 #define AQUNTIA_10G_CTL 0x20
18 #define AQUNTIA_VENDOR_P1 0xc400
19
20 #define AQUNTIA_SPEED_LSB_MASK 0x2000
21 #define AQUNTIA_SPEED_MSB_MASK 0x40
22
23 #define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812
24 #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
25 #define AQUANTIA_FIRMWARE_ID 0x20
26 #define AQUANTIA_RESERVED_STATUS 0xc885
27 #define AQUANTIA_FIRMWARE_MAJOR_MASK 0xff00
28 #define AQUANTIA_FIRMWARE_MINOR_MASK 0xff
29 #define AQUANTIA_FIRMWARE_BUILD_MASK 0xf0
30
31 #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
32 #define AQUANTIA_SI_IN_USE_MASK 0x0078
33 #define AQUANTIA_SI_USXGMII 0x0018
34
35 /* registers in MDIO_MMD_VEND1 region */
36 #define GLOBAL_FIRMWARE_ID 0x20
37 #define GLOBAL_FAULT 0xc850
38 #define GLOBAL_RSTATUS_1 0xc885
39
40 #define GLOBAL_STANDARD_CONTROL 0x0
41 #define SOFT_RESET BIT(15)
42 #define LOW_POWER BIT(11)
43
44 #define MAILBOX_CONTROL 0x0200
45 #define MAILBOX_EXECUTE BIT(15)
46 #define MAILBOX_WRITE BIT(14)
47 #define MAILBOX_RESET_CRC BIT(12)
48 #define MAILBOX_BUSY BIT(8)
49
50 #define MAILBOX_CRC 0x0201
51
52 #define MAILBOX_ADDR_MSW 0x0202
53 #define MAILBOX_ADDR_LSW 0x0203
54
55 #define MAILBOX_DATA_MSW 0x0204
56 #define MAILBOX_DATA_LSW 0x0205
57
58 #define UP_CONTROL 0xc001
59 #define UP_RESET BIT(15)
60 #define UP_RUN_STALL_OVERRIDE BIT(6)
61 #define UP_RUN_STALL BIT(0)
62
63 /* addresses of memory segments in the phy */
64 #define DRAM_BASE_ADDR 0x3FFE0000
65 #define IRAM_BASE_ADDR 0x40000000
66
67 /* firmware image format constants */
68 #define VERSION_STRING_SIZE 0x40
69 #define VERSION_STRING_OFFSET 0x0200
70 #define HEADER_OFFSET 0x300
71
72 #pragma pack(1)
73 struct fw_header {
74 u8 padding[4];
75 u8 iram_offset[3];
76 u8 iram_size[3];
77 u8 dram_offset[3];
78 u8 dram_size[3];
79 };
80
81 #pragma pack()
82
83 #if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW)
aquantia_read_fw(u8 ** fw_addr,size_t * fw_length)84 static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
85 {
86 loff_t length, read;
87 int ret;
88 void *addr = NULL;
89
90 *fw_addr = NULL;
91 *fw_length = 0;
92 debug("Loading Acquantia microcode from %s %s\n",
93 CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME);
94 ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
95 if (ret < 0)
96 goto cleanup;
97
98 ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length);
99 if (ret < 0)
100 goto cleanup;
101
102 addr = malloc(length);
103 if (!addr) {
104 ret = -ENOMEM;
105 goto cleanup;
106 }
107
108 ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
109 if (ret < 0)
110 goto cleanup;
111
112 ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,
113 &read);
114 if (ret < 0)
115 goto cleanup;
116
117 *fw_addr = addr;
118 *fw_length = length;
119 debug("Found Acquantia microcode.\n");
120
121 cleanup:
122 if (ret < 0) {
123 printf("loading firmware file %s %s failed with error %d\n",
124 CONFIG_PHY_AQUANTIA_FW_PART,
125 CONFIG_PHY_AQUANTIA_FW_NAME, ret);
126 free(addr);
127 }
128 return ret;
129 }
130
131 /* load data into the phy's memory */
aquantia_load_memory(struct phy_device * phydev,u32 addr,const u8 * data,size_t len)132 static int aquantia_load_memory(struct phy_device *phydev, u32 addr,
133 const u8 *data, size_t len)
134 {
135 size_t pos;
136 u16 crc = 0, up_crc;
137
138 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC);
139 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16);
140 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);
141
142 for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {
143 u32 word = 0;
144
145 memcpy(&word, &data[pos], min(sizeof(u32), len - pos));
146
147 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW,
148 (word >> 16));
149 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW,
150 word & 0xffff);
151
152 phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL,
153 MAILBOX_EXECUTE | MAILBOX_WRITE);
154
155 /* keep a big endian CRC to match the phy processor */
156 word = cpu_to_be32(word);
157 crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word));
158 }
159
160 up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC);
161 if (crc != up_crc) {
162 printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",
163 phydev->dev->name, crc, up_crc);
164 return -EINVAL;
165 }
166 return 0;
167 }
168
unpack_u24(const u8 * data)169 static u32 unpack_u24(const u8 *data)
170 {
171 return (data[2] << 16) + (data[1] << 8) + data[0];
172 }
173
aquantia_upload_firmware(struct phy_device * phydev)174 static int aquantia_upload_firmware(struct phy_device *phydev)
175 {
176 int ret;
177 u8 *addr = NULL;
178 size_t fw_length = 0;
179 u16 calculated_crc, read_crc;
180 char version[VERSION_STRING_SIZE];
181 u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size;
182 const struct fw_header *header;
183
184 ret = aquantia_read_fw(&addr, &fw_length);
185 if (ret != 0)
186 return ret;
187
188 read_crc = (addr[fw_length - 2] << 8) | addr[fw_length - 1];
189 calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
190 if (read_crc != calculated_crc) {
191 printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
192 phydev->dev->name, read_crc, calculated_crc);
193 ret = -EINVAL;
194 goto done;
195 }
196
197 /* Find the DRAM and IRAM sections within the firmware file. */
198 primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;
199
200 header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET];
201
202 iram_offset = primary_offset + unpack_u24(header->iram_offset);
203 iram_size = unpack_u24(header->iram_size);
204
205 dram_offset = primary_offset + unpack_u24(header->dram_offset);
206 dram_size = unpack_u24(header->dram_size);
207
208 debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n",
209 primary_offset, iram_offset, iram_size, dram_offset, dram_size);
210
211 strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
212 VERSION_STRING_SIZE);
213 printf("%s loading firmare version '%s'\n", phydev->dev->name, version);
214
215 /* stall the microcprocessor */
216 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
217 UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
218
219 debug("loading dram 0x%08x from offset=%d size=%d\n",
220 DRAM_BASE_ADDR, dram_offset, dram_size);
221 ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
222 dram_size);
223 if (ret != 0)
224 goto done;
225
226 debug("loading iram 0x%08x from offset=%d size=%d\n",
227 IRAM_BASE_ADDR, iram_offset, iram_size);
228 ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
229 iram_size);
230 if (ret != 0)
231 goto done;
232
233 /* make sure soft reset and low power mode are clear */
234 phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);
235
236 /* Release the microprocessor. UP_RESET must be held for 100 usec. */
237 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
238 UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET);
239
240 udelay(100);
241
242 phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE);
243
244 printf("%s firmare loading done.\n", phydev->dev->name);
245 done:
246 free(addr);
247 return ret;
248 }
249 #else
aquantia_upload_firmware(struct phy_device * phydev)250 static int aquantia_upload_firmware(struct phy_device *phydev)
251 {
252 printf("ERROR %s firmware loading disabled.\n", phydev->dev->name);
253 return -1;
254 }
255 #endif
256
aquantia_config(struct phy_device * phydev)257 int aquantia_config(struct phy_device *phydev)
258 {
259 u32 val, id, rstatus, fault;
260 u32 reg_val1 = 0;
261
262 id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
263 rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
264 fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT);
265
266 if (id != 0)
267 printf("%s running firmware version %X.%X.%X\n",
268 phydev->dev->name, (id >> 8), id & 0xff,
269 (rstatus >> 4) & 0xf);
270
271 if (fault != 0)
272 printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);
273
274 if (id == 0 || fault != 0) {
275 int ret;
276
277 ret = aquantia_upload_firmware(phydev);
278 if (ret != 0)
279 return ret;
280 }
281
282 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
283
284 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
285 /* 1000BASE-T mode */
286 phydev->advertising = SUPPORTED_1000baseT_Full;
287 phydev->supported = phydev->advertising;
288
289 val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
290 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
291 } else if (phydev->interface == PHY_INTERFACE_MODE_XGMII) {
292 /* 10GBASE-T mode */
293 phydev->advertising = SUPPORTED_10000baseT_Full;
294 phydev->supported = phydev->advertising;
295
296 if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
297 !(val & AQUNTIA_SPEED_MSB_MASK))
298 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
299 AQUNTIA_SPEED_LSB_MASK |
300 AQUNTIA_SPEED_MSB_MASK);
301
302 val = phy_read(phydev, MDIO_MMD_PHYXS,
303 AQUANTIA_SYSTEM_INTERFACE_SR);
304 /* If SI is USXGMII then start USXGMII autoneg */
305 if ((val & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) {
306 phy_write(phydev, MDIO_MMD_PHYXS,
307 AQUANTIA_VENDOR_PROVISIONING_REG,
308 AQUANTIA_USX_AUTONEG_CONTROL_ENA);
309 printf("%s: system interface USXGMII\n",
310 phydev->dev->name);
311 } else {
312 printf("%s: system interface XFI\n",
313 phydev->dev->name);
314 }
315
316 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII_2500) {
317 /* 2.5GBASE-T mode */
318 phydev->advertising = SUPPORTED_1000baseT_Full;
319 phydev->supported = phydev->advertising;
320
321 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
322 phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
323 } else if (phydev->interface == PHY_INTERFACE_MODE_MII) {
324 /* 100BASE-TX mode */
325 phydev->advertising = SUPPORTED_100baseT_Full;
326 phydev->supported = phydev->advertising;
327
328 val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
329 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
330 }
331
332 val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
333 reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
334
335 printf("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
336 phydev->drv->name,
337 (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
338 reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
339 (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
340
341 return 0;
342 }
343
aquantia_startup(struct phy_device * phydev)344 int aquantia_startup(struct phy_device *phydev)
345 {
346 u32 reg, speed;
347 int i = 0;
348
349 phydev->duplex = DUPLEX_FULL;
350
351 /* if the AN is still in progress, wait till timeout. */
352 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
353 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
354 if (!(reg & MDIO_AN_STAT1_COMPLETE)) {
355 printf("%s Waiting for PHY auto negotiation to complete",
356 phydev->dev->name);
357 do {
358 udelay(1000);
359 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
360 if ((i++ % 500) == 0)
361 printf(".");
362 } while (!(reg & MDIO_AN_STAT1_COMPLETE) &&
363 i < (4 * PHY_ANEG_TIMEOUT));
364
365 if (i > PHY_ANEG_TIMEOUT)
366 printf(" TIMEOUT !\n");
367 }
368
369 /* Read twice because link state is latched and a
370 * read moves the current state into the register */
371 phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
372 reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
373 if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
374 phydev->link = 0;
375 else
376 phydev->link = 1;
377
378 speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
379 if (speed & AQUNTIA_SPEED_MSB_MASK) {
380 if (speed & AQUNTIA_SPEED_LSB_MASK)
381 phydev->speed = SPEED_10000;
382 else
383 phydev->speed = SPEED_1000;
384 } else {
385 if (speed & AQUNTIA_SPEED_LSB_MASK)
386 phydev->speed = SPEED_100;
387 else
388 phydev->speed = SPEED_10;
389 }
390
391 return 0;
392 }
393
394 struct phy_driver aq1202_driver = {
395 .name = "Aquantia AQ1202",
396 .uid = 0x3a1b445,
397 .mask = 0xfffffff0,
398 .features = PHY_10G_FEATURES,
399 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
400 MDIO_MMD_PHYXS | MDIO_MMD_AN |
401 MDIO_MMD_VEND1),
402 .config = &aquantia_config,
403 .startup = &aquantia_startup,
404 .shutdown = &gen10g_shutdown,
405 };
406
407 struct phy_driver aq2104_driver = {
408 .name = "Aquantia AQ2104",
409 .uid = 0x3a1b460,
410 .mask = 0xfffffff0,
411 .features = PHY_10G_FEATURES,
412 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
413 MDIO_MMD_PHYXS | MDIO_MMD_AN |
414 MDIO_MMD_VEND1),
415 .config = &aquantia_config,
416 .startup = &aquantia_startup,
417 .shutdown = &gen10g_shutdown,
418 };
419
420 struct phy_driver aqr105_driver = {
421 .name = "Aquantia AQR105",
422 .uid = 0x3a1b4a2,
423 .mask = 0xfffffff0,
424 .features = PHY_10G_FEATURES,
425 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
426 MDIO_MMD_PHYXS | MDIO_MMD_AN |
427 MDIO_MMD_VEND1),
428 .config = &aquantia_config,
429 .startup = &aquantia_startup,
430 .shutdown = &gen10g_shutdown,
431 };
432
433 struct phy_driver aqr106_driver = {
434 .name = "Aquantia AQR106",
435 .uid = 0x3a1b4d0,
436 .mask = 0xfffffff0,
437 .features = PHY_10G_FEATURES,
438 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
439 MDIO_MMD_PHYXS | MDIO_MMD_AN |
440 MDIO_MMD_VEND1),
441 .config = &aquantia_config,
442 .startup = &aquantia_startup,
443 .shutdown = &gen10g_shutdown,
444 };
445
446 struct phy_driver aqr107_driver = {
447 .name = "Aquantia AQR107",
448 .uid = 0x3a1b4e0,
449 .mask = 0xfffffff0,
450 .features = PHY_10G_FEATURES,
451 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
452 MDIO_MMD_PHYXS | MDIO_MMD_AN |
453 MDIO_MMD_VEND1),
454 .config = &aquantia_config,
455 .startup = &aquantia_startup,
456 .shutdown = &gen10g_shutdown,
457 };
458
459 struct phy_driver aqr405_driver = {
460 .name = "Aquantia AQR405",
461 .uid = 0x3a1b4b2,
462 .mask = 0xfffffff0,
463 .features = PHY_10G_FEATURES,
464 .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
465 MDIO_MMD_PHYXS | MDIO_MMD_AN |
466 MDIO_MMD_VEND1),
467 .config = &aquantia_config,
468 .startup = &aquantia_startup,
469 .shutdown = &gen10g_shutdown,
470 };
471
phy_aquantia_init(void)472 int phy_aquantia_init(void)
473 {
474 phy_register(&aq1202_driver);
475 phy_register(&aq2104_driver);
476 phy_register(&aqr105_driver);
477 phy_register(&aqr106_driver);
478 phy_register(&aqr107_driver);
479 phy_register(&aqr405_driver);
480
481 return 0;
482 }
483