1 /* 2 * Copyright 2015-2016 Freescale Semiconductor, Inc. 3 * Copyright 2017 NXP 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <net/pfe_eth/pfe_eth.h> 9 #include <net/pfe_eth/pfe_firmware.h> 10 11 static struct tx_desc_s *g_tx_desc; 12 static struct rx_desc_s *g_rx_desc; 13 14 /* 15 * HIF Rx interface function 16 * Reads the rx descriptor from the current location (rx_to_read). 17 * - If the descriptor has a valid data/pkt, then get the data pointer 18 * - check for the input rx phy number 19 * - increment the rx data pointer by pkt_head_room_size 20 * - decrement the data length by pkt_head_room_size 21 * - handover the packet to caller. 22 * 23 * @param[out] pkt_ptr - Pointer to store rx packet 24 * @param[out] phy_port - Pointer to store recv phy port 25 * 26 * @return -1 if no packet, else return length of packet. 27 */ 28 int pfe_recv(uchar **pkt_ptr, int *phy_port) 29 { 30 struct rx_desc_s *rx_desc = g_rx_desc; 31 struct buf_desc *bd; 32 int len = 0; 33 34 struct hif_header_s *hif_header; 35 36 bd = rx_desc->rx_base + rx_desc->rx_to_read; 37 38 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN) 39 return len; /* No pending Rx packet */ 40 41 /* this len include hif_header(8 bytes) */ 42 len = readl(&bd->ctrl) & 0xFFFF; 43 44 hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(readl(&bd->data)); 45 46 /* Get the receive port info from the packet */ 47 debug("Pkt received:"); 48 debug(" Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n", 49 hif_header, len, hif_header->port_no, readl(&bd->status)); 50 #ifdef DEBUG 51 { 52 int i; 53 unsigned char *p = (unsigned char *)hif_header; 54 55 for (i = 0; i < len; i++) { 56 if (!(i % 16)) 57 printf("\n"); 58 printf(" %02x", p[i]); 59 } 60 printf("\n"); 61 } 62 #endif 63 64 *pkt_ptr = (uchar *)(hif_header + 1); 65 *phy_port = hif_header->port_no; 66 len -= sizeof(struct hif_header_s); 67 68 return len; 69 } 70 71 /* 72 * HIF function to check the Rx done 73 * This function will check the rx done indication of the current rx_to_read 74 * locations 75 * if success, moves the rx_to_read to next location. 76 */ 77 int pfe_eth_free_pkt(struct udevice *dev, uchar *packet, int length) 78 { 79 struct rx_desc_s *rx_desc = g_rx_desc; 80 struct buf_desc *bd; 81 82 debug("%s:rx_base: %p, rx_to_read: %d\n", __func__, rx_desc->rx_base, 83 rx_desc->rx_to_read); 84 85 bd = rx_desc->rx_base + rx_desc->rx_to_read; 86 87 /* reset the control field */ 88 writel((MAX_FRAME_SIZE | BD_CTRL_LIFM | BD_CTRL_DESC_EN 89 | BD_CTRL_DIR), &bd->ctrl); 90 writel(0, &bd->status); 91 92 debug("Rx Done : status: %08x, ctrl: %08x\n", readl(&bd->status), 93 readl(&bd->ctrl)); 94 95 /* Give START_STROBE to BDP to fetch the descriptor __NOW__, 96 * BDP need not wait for rx_poll_cycle time to fetch the descriptor, 97 * In idle state (ie., no rx pkt), BDP will not fetch 98 * the descriptor even if strobe is given. 99 */ 100 writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL); 101 102 /* increment the rx_to_read index to next location */ 103 rx_desc->rx_to_read = (rx_desc->rx_to_read + 1) 104 & (rx_desc->rx_ring_size - 1); 105 106 debug("Rx next pkt location: %d\n", rx_desc->rx_to_read); 107 108 return 0; 109 } 110 111 /* 112 * HIF Tx interface function 113 * This function sends a single packet to PFE from HIF interface. 114 * - No interrupt indication on tx completion. 115 * - Data is copied to tx buffers before tx descriptor is updated 116 * and TX DMA is enabled. 117 * 118 * @param[in] phy_port Phy port number to send out this packet 119 * @param[in] data Pointer to the data 120 * @param[in] length Length of the ethernet packet to be transferred. 121 * 122 * @return -1 if tx Q is full, else returns the tx location where the pkt is 123 * placed. 124 */ 125 int pfe_send(int phy_port, void *data, int length) 126 { 127 struct tx_desc_s *tx_desc = g_tx_desc; 128 struct buf_desc *bd; 129 struct hif_header_s hif_header; 130 u8 *tx_buf_va; 131 132 debug("%s:pkt: %p, len: %d, tx_base: %p, tx_to_send: %d\n", __func__, 133 data, length, tx_desc->tx_base, tx_desc->tx_to_send); 134 135 bd = tx_desc->tx_base + tx_desc->tx_to_send; 136 137 /* check queue-full condition */ 138 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN) 139 return -1; 140 141 /* PFE checks for min pkt size */ 142 if (length < MIN_PKT_SIZE) 143 length = MIN_PKT_SIZE; 144 145 tx_buf_va = (void *)DDR_PFE_TO_VIRT(readl(&bd->data)); 146 debug("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va, 147 readl(&bd->data)); 148 149 /* Fill the gemac/phy port number to send this packet out */ 150 memset(&hif_header, 0, sizeof(struct hif_header_s)); 151 hif_header.port_no = phy_port; 152 153 memcpy(tx_buf_va, (u8 *)&hif_header, sizeof(struct hif_header_s)); 154 memcpy(tx_buf_va + sizeof(struct hif_header_s), data, length); 155 length += sizeof(struct hif_header_s); 156 157 #ifdef DEBUG 158 { 159 int i; 160 unsigned char *p = (unsigned char *)tx_buf_va; 161 162 for (i = 0; i < length; i++) { 163 if (!(i % 16)) 164 printf("\n"); 165 printf("%02x ", p[i]); 166 } 167 } 168 #endif 169 170 debug("Tx Done: status: %08x, ctrl: %08x\n", readl(&bd->status), 171 readl(&bd->ctrl)); 172 173 /* fill the tx desc */ 174 writel((u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0xFFFF)), 175 &bd->ctrl); 176 writel(0, &bd->status); 177 178 writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL); 179 180 udelay(100); 181 182 return tx_desc->tx_to_send; 183 } 184 185 /* 186 * HIF function to check the Tx done 187 * This function will check the tx done indication of the current tx_to_send 188 * locations 189 * if success, moves the tx_to_send to next location. 190 * 191 * @return -1 if TX ownership bit is not cleared by hw. 192 * else on success (tx done completion) return zero. 193 */ 194 int pfe_tx_done(void) 195 { 196 struct tx_desc_s *tx_desc = g_tx_desc; 197 struct buf_desc *bd; 198 199 debug("%s:tx_base: %p, tx_to_send: %d\n", __func__, tx_desc->tx_base, 200 tx_desc->tx_to_send); 201 202 bd = tx_desc->tx_base + tx_desc->tx_to_send; 203 204 /* check queue-full condition */ 205 if (readl(&bd->ctrl) & BD_CTRL_DESC_EN) 206 return -1; 207 208 /* reset the control field */ 209 writel(0, &bd->ctrl); 210 writel(0, &bd->status); 211 212 debug("Tx Done : status: %08x, ctrl: %08x\n", readl(&bd->status), 213 readl(&bd->ctrl)); 214 215 /* increment the txtosend index to next location */ 216 tx_desc->tx_to_send = (tx_desc->tx_to_send + 1) 217 & (tx_desc->tx_ring_size - 1); 218 219 debug("Tx next pkt location: %d\n", tx_desc->tx_to_send); 220 221 return 0; 222 } 223 224 /* 225 * Helper function to dump Rx descriptors. 226 */ 227 static inline void hif_rx_desc_dump(void) 228 { 229 struct buf_desc *bd_va; 230 int i; 231 struct rx_desc_s *rx_desc; 232 233 if (!g_rx_desc) { 234 printf("%s: HIF Rx desc no init\n", __func__); 235 return; 236 } 237 238 rx_desc = g_rx_desc; 239 bd_va = rx_desc->rx_base; 240 241 debug("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rx_base, 242 rx_desc->rx_base_pa); 243 for (i = 0; i < rx_desc->rx_ring_size; i++) { 244 debug("status: %08x, ctrl: %08x, data: %08x, next: 0x%08x\n", 245 readl(&bd_va->status), 246 readl(&bd_va->ctrl), 247 readl(&bd_va->data), 248 readl(&bd_va->next)); 249 bd_va++; 250 } 251 } 252 253 /* 254 * This function mark all Rx descriptors as LAST_BD. 255 */ 256 void hif_rx_desc_disable(void) 257 { 258 int i; 259 struct rx_desc_s *rx_desc; 260 struct buf_desc *bd_va; 261 262 if (!g_rx_desc) { 263 printf("%s: HIF Rx desc not initialized\n", __func__); 264 return; 265 } 266 267 rx_desc = g_rx_desc; 268 bd_va = rx_desc->rx_base; 269 270 for (i = 0; i < rx_desc->rx_ring_size; i++) { 271 writel(readl(&bd_va->ctrl) | BD_CTRL_LAST_BD, &bd_va->ctrl); 272 bd_va++; 273 } 274 } 275 276 /* 277 * HIF Rx Desc initialization function. 278 */ 279 static int hif_rx_desc_init(struct pfe_ddr_address *pfe_addr) 280 { 281 u32 ctrl; 282 struct buf_desc *bd_va; 283 struct buf_desc *bd_pa; 284 struct rx_desc_s *rx_desc; 285 u32 rx_buf_pa; 286 int i; 287 288 /* sanity check */ 289 if (g_rx_desc) { 290 printf("%s: HIF Rx desc re-init request\n", __func__); 291 return 0; 292 } 293 294 rx_desc = (struct rx_desc_s *)malloc(sizeof(struct rx_desc_s)); 295 if (!rx_desc) { 296 printf("%s: Memory allocation failure\n", __func__); 297 return -ENOMEM; 298 } 299 memset(rx_desc, 0, sizeof(struct rx_desc_s)); 300 301 /* init: Rx ring buffer */ 302 rx_desc->rx_ring_size = HIF_RX_DESC_NT; 303 304 /* NOTE: must be 64bit aligned */ 305 bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr 306 + RX_BD_BASEADDR); 307 bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr 308 + RX_BD_BASEADDR); 309 310 rx_desc->rx_base = bd_va; 311 rx_desc->rx_base_pa = (unsigned long)bd_pa; 312 313 rx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR; 314 315 debug("%s: Rx desc base: %p, base_pa: %08x, desc_count: %d\n", 316 __func__, rx_desc->rx_base, rx_desc->rx_base_pa, 317 rx_desc->rx_ring_size); 318 319 memset(bd_va, 0, sizeof(struct buf_desc) * rx_desc->rx_ring_size); 320 321 ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM); 322 323 for (i = 0; i < rx_desc->rx_ring_size; i++) { 324 writel((unsigned long)(bd_pa + 1), &bd_va->next); 325 writel(ctrl, &bd_va->ctrl); 326 writel(rx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data); 327 bd_va++; 328 bd_pa++; 329 } 330 --bd_va; 331 writel((u32)rx_desc->rx_base_pa, &bd_va->next); 332 333 writel(rx_desc->rx_base_pa, HIF_RX_BDP_ADDR); 334 writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL); 335 336 g_rx_desc = rx_desc; 337 338 return 0; 339 } 340 341 /* 342 * Helper function to dump Tx Descriptors. 343 */ 344 static inline void hif_tx_desc_dump(void) 345 { 346 struct tx_desc_s *tx_desc; 347 int i; 348 struct buf_desc *bd_va; 349 350 if (!g_tx_desc) { 351 printf("%s: HIF Tx desc no init\n", __func__); 352 return; 353 } 354 355 tx_desc = g_tx_desc; 356 bd_va = tx_desc->tx_base; 357 358 debug("HIF tx desc: base_va: %p, base_pa: %08x\n", tx_desc->tx_base, 359 tx_desc->tx_base_pa); 360 361 for (i = 0; i < tx_desc->tx_ring_size; i++) 362 bd_va++; 363 } 364 365 /* 366 * HIF Tx descriptor initialization function. 367 */ 368 static int hif_tx_desc_init(struct pfe_ddr_address *pfe_addr) 369 { 370 struct buf_desc *bd_va; 371 struct buf_desc *bd_pa; 372 int i; 373 struct tx_desc_s *tx_desc; 374 u32 tx_buf_pa; 375 376 /* sanity check */ 377 if (g_tx_desc) { 378 printf("%s: HIF Tx desc re-init request\n", __func__); 379 return 0; 380 } 381 382 tx_desc = (struct tx_desc_s *)malloc(sizeof(struct tx_desc_s)); 383 if (!tx_desc) { 384 printf("%s:%d:Memory allocation failure\n", __func__, 385 __LINE__); 386 return -ENOMEM; 387 } 388 memset(tx_desc, 0, sizeof(struct tx_desc_s)); 389 390 /* init: Tx ring buffer */ 391 tx_desc->tx_ring_size = HIF_TX_DESC_NT; 392 393 /* NOTE: must be 64bit aligned */ 394 bd_va = (struct buf_desc *)(pfe_addr->ddr_pfe_baseaddr 395 + TX_BD_BASEADDR); 396 bd_pa = (struct buf_desc *)(pfe_addr->ddr_pfe_phys_baseaddr 397 + TX_BD_BASEADDR); 398 399 tx_desc->tx_base_pa = (unsigned long)bd_pa; 400 tx_desc->tx_base = bd_va; 401 402 debug("%s: Tx desc_base: %p, base_pa: %08x, desc_count: %d\n", 403 __func__, tx_desc->tx_base, tx_desc->tx_base_pa, 404 tx_desc->tx_ring_size); 405 406 memset(bd_va, 0, sizeof(struct buf_desc) * tx_desc->tx_ring_size); 407 408 tx_buf_pa = pfe_addr->ddr_pfe_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR; 409 410 for (i = 0; i < tx_desc->tx_ring_size; i++) { 411 writel((unsigned long)(bd_pa + 1), &bd_va->next); 412 writel(tx_buf_pa + (i * MAX_FRAME_SIZE), &bd_va->data); 413 bd_va++; 414 bd_pa++; 415 } 416 --bd_va; 417 writel((u32)tx_desc->tx_base_pa, &bd_va->next); 418 419 writel(tx_desc->tx_base_pa, HIF_TX_BDP_ADDR); 420 421 g_tx_desc = tx_desc; 422 423 return 0; 424 } 425 426 /* 427 * PFE/Class initialization. 428 */ 429 static void pfe_class_init(struct pfe_ddr_address *pfe_addr) 430 { 431 struct class_cfg class_cfg = { 432 .route_table_baseaddr = pfe_addr->ddr_pfe_phys_baseaddr + 433 ROUTE_TABLE_BASEADDR, 434 .route_table_hash_bits = ROUTE_TABLE_HASH_BITS, 435 }; 436 437 class_init(&class_cfg); 438 439 debug("class init complete\n"); 440 } 441 442 /* 443 * PFE/TMU initialization. 444 */ 445 static void pfe_tmu_init(struct pfe_ddr_address *pfe_addr) 446 { 447 struct tmu_cfg tmu_cfg = { 448 .llm_base_addr = pfe_addr->ddr_pfe_phys_baseaddr 449 + TMU_LLM_BASEADDR, 450 .llm_queue_len = TMU_LLM_QUEUE_LEN, 451 }; 452 453 tmu_init(&tmu_cfg); 454 455 debug("tmu init complete\n"); 456 } 457 458 /* 459 * PFE/BMU (both BMU1 & BMU2) initialization. 460 */ 461 static void pfe_bmu_init(struct pfe_ddr_address *pfe_addr) 462 { 463 struct bmu_cfg bmu1_cfg = { 464 .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR + 465 BMU1_LMEM_BASEADDR), 466 .count = BMU1_BUF_COUNT, 467 .size = BMU1_BUF_SIZE, 468 }; 469 470 struct bmu_cfg bmu2_cfg = { 471 .baseaddr = pfe_addr->ddr_pfe_phys_baseaddr + BMU2_DDR_BASEADDR, 472 .count = BMU2_BUF_COUNT, 473 .size = BMU2_BUF_SIZE, 474 }; 475 476 bmu_init(BMU1_BASE_ADDR, &bmu1_cfg); 477 debug("bmu1 init: done\n"); 478 479 bmu_init(BMU2_BASE_ADDR, &bmu2_cfg); 480 debug("bmu2 init: done\n"); 481 } 482 483 /* 484 * PFE/GPI initialization function. 485 * - egpi1, egpi2, egpi3, hgpi 486 */ 487 static void pfe_gpi_init(struct pfe_ddr_address *pfe_addr) 488 { 489 struct gpi_cfg egpi1_cfg = { 490 .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT, 491 .tmlf_txthres = EGPI1_TMLF_TXTHRES, 492 .aseq_len = EGPI1_ASEQ_LEN, 493 }; 494 495 struct gpi_cfg egpi2_cfg = { 496 .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT, 497 .tmlf_txthres = EGPI2_TMLF_TXTHRES, 498 .aseq_len = EGPI2_ASEQ_LEN, 499 }; 500 501 struct gpi_cfg hgpi_cfg = { 502 .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT, 503 .tmlf_txthres = HGPI_TMLF_TXTHRES, 504 .aseq_len = HGPI_ASEQ_LEN, 505 }; 506 507 gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg); 508 debug("GPI1 init complete\n"); 509 510 gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg); 511 debug("GPI2 init complete\n"); 512 513 gpi_init(HGPI_BASE_ADDR, &hgpi_cfg); 514 debug("HGPI init complete\n"); 515 } 516 517 /* 518 * PFE/HIF initialization function. 519 */ 520 static int pfe_hif_init(struct pfe_ddr_address *pfe_addr) 521 { 522 int ret = 0; 523 524 hif_tx_disable(); 525 hif_rx_disable(); 526 527 ret = hif_tx_desc_init(pfe_addr); 528 if (ret) 529 return ret; 530 ret = hif_rx_desc_init(pfe_addr); 531 if (ret) 532 return ret; 533 534 hif_init(); 535 536 hif_tx_enable(); 537 hif_rx_enable(); 538 539 hif_rx_desc_dump(); 540 hif_tx_desc_dump(); 541 542 debug("HIF init complete\n"); 543 return ret; 544 } 545 546 /* 547 * PFE initialization 548 * - Firmware loading (CLASS-PE and TMU-PE) 549 * - BMU1 and BMU2 init 550 * - GEMAC init 551 * - GPI init 552 * - CLASS-PE init 553 * - TMU-PE init 554 * - HIF tx and rx descriptors init 555 * 556 * @param[in] edev Pointer to eth device structure. 557 * 558 * @return 0, on success. 559 */ 560 static int pfe_hw_init(struct pfe_ddr_address *pfe_addr) 561 { 562 int ret = 0; 563 564 debug("%s: start\n", __func__); 565 566 writel(0x3, CLASS_PE_SYS_CLK_RATIO); 567 writel(0x3, TMU_PE_SYS_CLK_RATIO); 568 writel(0x3, UTIL_PE_SYS_CLK_RATIO); 569 udelay(10); 570 571 pfe_class_init(pfe_addr); 572 573 pfe_tmu_init(pfe_addr); 574 575 pfe_bmu_init(pfe_addr); 576 577 pfe_gpi_init(pfe_addr); 578 579 ret = pfe_hif_init(pfe_addr); 580 if (ret) 581 return ret; 582 583 bmu_enable(BMU1_BASE_ADDR); 584 debug("bmu1 enabled\n"); 585 586 bmu_enable(BMU2_BASE_ADDR); 587 debug("bmu2 enabled\n"); 588 589 debug("%s: done\n", __func__); 590 591 return ret; 592 } 593 594 /* 595 * PFE driver init function. 596 * - Initializes pfe_lib 597 * - pfe hw init 598 * - fw loading and enables PEs 599 * - should be executed once. 600 * 601 * @param[in] pfe Pointer the pfe control block 602 */ 603 int pfe_drv_init(struct pfe_ddr_address *pfe_addr) 604 { 605 int ret = 0; 606 607 pfe_lib_init(); 608 609 ret = pfe_hw_init(pfe_addr); 610 if (ret) 611 return ret; 612 613 /* Load the class,TM, Util fw. 614 * By now pfe is: 615 * - out of reset + disabled + configured. 616 * Fw loading should be done after pfe_hw_init() 617 */ 618 /* It loads default inbuilt sbl firmware */ 619 pfe_firmware_init(); 620 621 return ret; 622 } 623 624 /* 625 * PFE remove function 626 * - stops PEs 627 * - frees tx/rx descriptor resources 628 * - should be called once. 629 * 630 * @param[in] pfe Pointer to pfe control block. 631 */ 632 int pfe_eth_remove(struct udevice *dev) 633 { 634 if (g_tx_desc) 635 free(g_tx_desc); 636 637 if (g_rx_desc) 638 free(g_rx_desc); 639 640 pfe_firmware_exit(); 641 642 return 0; 643 } 644