1 /* 2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. 3 * 4 * This driver for AMD PCnet network controllers is derived from the 5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <net.h> 13 #include <netdev.h> 14 #include <asm/io.h> 15 #include <pci.h> 16 17 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ 18 19 #define PCNET_DEBUG1(fmt,args...) \ 20 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args) 21 #define PCNET_DEBUG2(fmt,args...) \ 22 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args) 23 24 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) 25 #error "Macro for PCnet chip version is not defined!" 26 #endif 27 28 /* 29 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 30 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 31 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 32 */ 33 #define PCNET_LOG_TX_BUFFERS 0 34 #define PCNET_LOG_RX_BUFFERS 2 35 36 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) 37 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) 38 39 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) 40 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) 41 42 #define PKT_BUF_SZ 1544 43 44 /* The PCNET Rx and Tx ring descriptors. */ 45 struct pcnet_rx_head { 46 u32 base; 47 s16 buf_length; 48 s16 status; 49 u32 msg_length; 50 u32 reserved; 51 }; 52 53 struct pcnet_tx_head { 54 u32 base; 55 s16 length; 56 s16 status; 57 u32 misc; 58 u32 reserved; 59 }; 60 61 /* The PCNET 32-Bit initialization block, described in databook. */ 62 struct pcnet_init_block { 63 u16 mode; 64 u16 tlen_rlen; 65 u8 phys_addr[6]; 66 u16 reserved; 67 u32 filter[2]; 68 /* Receive and transmit ring base, along with extra bits. */ 69 u32 rx_ring; 70 u32 tx_ring; 71 u32 reserved2; 72 }; 73 74 typedef struct pcnet_priv { 75 struct pcnet_rx_head rx_ring[RX_RING_SIZE]; 76 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; 77 struct pcnet_init_block init_block; 78 /* Receive Buffer space */ 79 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; 80 int cur_rx; 81 int cur_tx; 82 } pcnet_priv_t; 83 84 static pcnet_priv_t *lp; 85 86 /* Offsets from base I/O address for WIO mode */ 87 #define PCNET_RDP 0x10 88 #define PCNET_RAP 0x12 89 #define PCNET_RESET 0x14 90 #define PCNET_BDP 0x16 91 92 static u16 pcnet_read_csr (struct eth_device *dev, int index) 93 { 94 outw (index, dev->iobase + PCNET_RAP); 95 return inw (dev->iobase + PCNET_RDP); 96 } 97 98 static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) 99 { 100 outw (index, dev->iobase + PCNET_RAP); 101 outw (val, dev->iobase + PCNET_RDP); 102 } 103 104 static u16 pcnet_read_bcr (struct eth_device *dev, int index) 105 { 106 outw (index, dev->iobase + PCNET_RAP); 107 return inw (dev->iobase + PCNET_BDP); 108 } 109 110 static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) 111 { 112 outw (index, dev->iobase + PCNET_RAP); 113 outw (val, dev->iobase + PCNET_BDP); 114 } 115 116 static void pcnet_reset (struct eth_device *dev) 117 { 118 inw (dev->iobase + PCNET_RESET); 119 } 120 121 static int pcnet_check (struct eth_device *dev) 122 { 123 outw (88, dev->iobase + PCNET_RAP); 124 return (inw (dev->iobase + PCNET_RAP) == 88); 125 } 126 127 static int pcnet_init (struct eth_device *dev, bd_t * bis); 128 static int pcnet_send(struct eth_device *dev, void *packet, int length); 129 static int pcnet_recv (struct eth_device *dev); 130 static void pcnet_halt (struct eth_device *dev); 131 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); 132 133 #define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a)) 134 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) 135 136 static struct pci_device_id supported[] = { 137 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, 138 {} 139 }; 140 141 142 int pcnet_initialize (bd_t * bis) 143 { 144 pci_dev_t devbusfn; 145 struct eth_device *dev; 146 u16 command, status; 147 int dev_nr = 0; 148 149 PCNET_DEBUG1 ("\npcnet_initialize...\n"); 150 151 for (dev_nr = 0;; dev_nr++) { 152 153 /* 154 * Find the PCnet PCI device(s). 155 */ 156 if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) { 157 break; 158 } 159 160 /* 161 * Allocate and pre-fill the device structure. 162 */ 163 dev = (struct eth_device *) malloc (sizeof *dev); 164 if (!dev) { 165 printf("pcnet: Can not allocate memory\n"); 166 break; 167 } 168 memset(dev, 0, sizeof(*dev)); 169 dev->priv = (void *) devbusfn; 170 sprintf (dev->name, "pcnet#%d", dev_nr); 171 172 /* 173 * Setup the PCI device. 174 */ 175 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, 176 (unsigned int *) &dev->iobase); 177 dev->iobase=pci_io_to_phys (devbusfn, dev->iobase); 178 dev->iobase &= ~0xf; 179 180 PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ", 181 dev->name, devbusfn, dev->iobase); 182 183 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; 184 pci_write_config_word (devbusfn, PCI_COMMAND, command); 185 pci_read_config_word (devbusfn, PCI_COMMAND, &status); 186 if ((status & command) != command) { 187 printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name); 188 free (dev); 189 continue; 190 } 191 192 pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40); 193 194 /* 195 * Probe the PCnet chip. 196 */ 197 if (pcnet_probe (dev, bis, dev_nr) < 0) { 198 free (dev); 199 continue; 200 } 201 202 /* 203 * Setup device structure and register the driver. 204 */ 205 dev->init = pcnet_init; 206 dev->halt = pcnet_halt; 207 dev->send = pcnet_send; 208 dev->recv = pcnet_recv; 209 210 eth_register (dev); 211 } 212 213 udelay (10 * 1000); 214 215 return dev_nr; 216 } 217 218 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) 219 { 220 int chip_version; 221 char *chipname; 222 223 #ifdef PCNET_HAS_PROM 224 int i; 225 #endif 226 227 /* Reset the PCnet controller */ 228 pcnet_reset (dev); 229 230 /* Check if register access is working */ 231 if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) { 232 printf ("%s: CSR register access check failed\n", dev->name); 233 return -1; 234 } 235 236 /* Identify the chip */ 237 chip_version = 238 pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16); 239 if ((chip_version & 0xfff) != 0x003) 240 return -1; 241 chip_version = (chip_version >> 12) & 0xffff; 242 switch (chip_version) { 243 case 0x2621: 244 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 245 break; 246 #ifdef CONFIG_PCNET_79C973 247 case 0x2625: 248 chipname = "PCnet/FAST III 79C973"; /* PCI */ 249 break; 250 #endif 251 #ifdef CONFIG_PCNET_79C975 252 case 0x2627: 253 chipname = "PCnet/FAST III 79C975"; /* PCI */ 254 break; 255 #endif 256 default: 257 printf ("%s: PCnet version %#x not supported\n", 258 dev->name, chip_version); 259 return -1; 260 } 261 262 PCNET_DEBUG1 ("AMD %s\n", chipname); 263 264 #ifdef PCNET_HAS_PROM 265 /* 266 * In most chips, after a chip reset, the ethernet address is read from 267 * the station address PROM at the base address and programmed into the 268 * "Physical Address Registers" CSR12-14. 269 */ 270 for (i = 0; i < 3; i++) { 271 unsigned int val; 272 273 val = pcnet_read_csr (dev, i + 12) & 0x0ffff; 274 /* There may be endianness issues here. */ 275 dev->enetaddr[2 * i] = val & 0x0ff; 276 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; 277 } 278 #endif /* PCNET_HAS_PROM */ 279 280 return 0; 281 } 282 283 static int pcnet_init (struct eth_device *dev, bd_t * bis) 284 { 285 int i, val; 286 u32 addr; 287 288 PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name); 289 290 /* Switch pcnet to 32bit mode */ 291 pcnet_write_bcr (dev, 20, 2); 292 293 #ifdef CONFIG_PN62 294 /* Setup LED registers */ 295 val = pcnet_read_bcr (dev, 2) | 0x1000; 296 pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ 297 pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ 298 pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ 299 pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ 300 pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ 301 #endif 302 303 /* Set/reset autoselect bit */ 304 val = pcnet_read_bcr (dev, 2) & ~2; 305 val |= 2; 306 pcnet_write_bcr (dev, 2, val); 307 308 /* Enable auto negotiate, setup, disable fd */ 309 val = pcnet_read_bcr (dev, 32) & ~0x98; 310 val |= 0x20; 311 pcnet_write_bcr (dev, 32, val); 312 313 /* 314 * We only maintain one structure because the drivers will never 315 * be used concurrently. In 32bit mode the RX and TX ring entries 316 * must be aligned on 16-byte boundaries. 317 */ 318 if (lp == NULL) { 319 addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10); 320 addr = (addr + 0xf) & ~0xf; 321 lp = (pcnet_priv_t *) addr; 322 } 323 324 lp->init_block.mode = cpu_to_le16 (0x0000); 325 lp->init_block.filter[0] = 0x00000000; 326 lp->init_block.filter[1] = 0x00000000; 327 328 /* 329 * Initialize the Rx ring. 330 */ 331 lp->cur_rx = 0; 332 for (i = 0; i < RX_RING_SIZE; i++) { 333 lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]); 334 lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ); 335 lp->rx_ring[i].status = cpu_to_le16 (0x8000); 336 PCNET_DEBUG1 337 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, 338 lp->rx_ring[i].base, lp->rx_ring[i].buf_length, 339 lp->rx_ring[i].status); 340 } 341 342 /* 343 * Initialize the Tx ring. The Tx buffer address is filled in as 344 * needed, but we do need to clear the upper ownership bit. 345 */ 346 lp->cur_tx = 0; 347 for (i = 0; i < TX_RING_SIZE; i++) { 348 lp->tx_ring[i].base = 0; 349 lp->tx_ring[i].status = 0; 350 } 351 352 /* 353 * Setup Init Block. 354 */ 355 PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block); 356 357 for (i = 0; i < 6; i++) { 358 lp->init_block.phys_addr[i] = dev->enetaddr[i]; 359 PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]); 360 } 361 362 lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS | 363 RX_RING_LEN_BITS); 364 lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring); 365 lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring); 366 367 PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", 368 lp->init_block.tlen_rlen, 369 lp->init_block.rx_ring, lp->init_block.tx_ring); 370 371 /* 372 * Tell the controller where the Init Block is located. 373 */ 374 addr = PCI_TO_MEM (dev, &lp->init_block); 375 pcnet_write_csr (dev, 1, addr & 0xffff); 376 pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff); 377 378 pcnet_write_csr (dev, 4, 0x0915); 379 pcnet_write_csr (dev, 0, 0x0001); /* start */ 380 381 /* Wait for Init Done bit */ 382 for (i = 10000; i > 0; i--) { 383 if (pcnet_read_csr (dev, 0) & 0x0100) 384 break; 385 udelay (10); 386 } 387 if (i <= 0) { 388 printf ("%s: TIMEOUT: controller init failed\n", dev->name); 389 pcnet_reset (dev); 390 return -1; 391 } 392 393 /* 394 * Finally start network controller operation. 395 */ 396 pcnet_write_csr (dev, 0, 0x0002); 397 398 return 0; 399 } 400 401 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) 402 { 403 int i, status; 404 struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; 405 406 PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, 407 packet); 408 409 /* Wait for completion by testing the OWN bit */ 410 for (i = 1000; i > 0; i--) { 411 status = le16_to_cpu (entry->status); 412 if ((status & 0x8000) == 0) 413 break; 414 udelay (100); 415 PCNET_DEBUG2 ("."); 416 } 417 if (i <= 0) { 418 printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", 419 dev->name, lp->cur_tx, status); 420 pkt_len = 0; 421 goto failure; 422 } 423 424 /* 425 * Setup Tx ring. Caution: the write order is important here, 426 * set the status with the "ownership" bits last. 427 */ 428 status = 0x8300; 429 entry->length = le16_to_cpu (-pkt_len); 430 entry->misc = 0x00000000; 431 entry->base = PCI_TO_MEM_LE (dev, packet); 432 entry->status = le16_to_cpu (status); 433 434 /* Trigger an immediate send poll. */ 435 pcnet_write_csr (dev, 0, 0x0008); 436 437 failure: 438 if (++lp->cur_tx >= TX_RING_SIZE) 439 lp->cur_tx = 0; 440 441 PCNET_DEBUG2 ("done\n"); 442 return pkt_len; 443 } 444 445 static int pcnet_recv (struct eth_device *dev) 446 { 447 struct pcnet_rx_head *entry; 448 int pkt_len = 0; 449 u16 status; 450 451 while (1) { 452 entry = &lp->rx_ring[lp->cur_rx]; 453 /* 454 * If we own the next entry, it's a new packet. Send it up. 455 */ 456 if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) { 457 break; 458 } 459 status >>= 8; 460 461 if (status != 0x03) { /* There was an error. */ 462 463 printf ("%s: Rx%d", dev->name, lp->cur_rx); 464 PCNET_DEBUG1 (" (status=0x%x)", status); 465 if (status & 0x20) 466 printf (" Frame"); 467 if (status & 0x10) 468 printf (" Overflow"); 469 if (status & 0x08) 470 printf (" CRC"); 471 if (status & 0x04) 472 printf (" Fifo"); 473 printf (" Error\n"); 474 entry->status &= le16_to_cpu (0x03ff); 475 476 } else { 477 478 pkt_len = 479 (le32_to_cpu (entry->msg_length) & 0xfff) - 4; 480 if (pkt_len < 60) { 481 printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); 482 } else { 483 NetReceive (lp->rx_buf[lp->cur_rx], pkt_len); 484 PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n", 485 lp->cur_rx, pkt_len, 486 lp->rx_buf[lp->cur_rx]); 487 } 488 } 489 entry->status |= cpu_to_le16 (0x8000); 490 491 if (++lp->cur_rx >= RX_RING_SIZE) 492 lp->cur_rx = 0; 493 } 494 return pkt_len; 495 } 496 497 static void pcnet_halt (struct eth_device *dev) 498 { 499 int i; 500 501 PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name); 502 503 /* Reset the PCnet controller */ 504 pcnet_reset (dev); 505 506 /* Wait for Stop bit */ 507 for (i = 1000; i > 0; i--) { 508 if (pcnet_read_csr (dev, 0) & 0x4) 509 break; 510 udelay (10); 511 } 512 if (i <= 0) { 513 printf ("%s: TIMEOUT: controller reset failed\n", dev->name); 514 } 515 } 516