1 /* 2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. 3 * 4 * This driver for AMD PCnet network controllers is derived from the 5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <net.h> 13 #include <netdev.h> 14 #include <asm/io.h> 15 #include <pci.h> 16 17 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ 18 19 #define PCNET_DEBUG1(fmt,args...) \ 20 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args) 21 #define PCNET_DEBUG2(fmt,args...) \ 22 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args) 23 24 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) 25 #error "Macro for PCnet chip version is not defined!" 26 #endif 27 28 /* 29 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 30 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 31 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 32 */ 33 #define PCNET_LOG_TX_BUFFERS 0 34 #define PCNET_LOG_RX_BUFFERS 2 35 36 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) 37 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) 38 39 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) 40 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) 41 42 #define PKT_BUF_SZ 1544 43 44 /* The PCNET Rx and Tx ring descriptors. */ 45 struct pcnet_rx_head { 46 u32 base; 47 s16 buf_length; 48 s16 status; 49 u32 msg_length; 50 u32 reserved; 51 }; 52 53 struct pcnet_tx_head { 54 u32 base; 55 s16 length; 56 s16 status; 57 u32 misc; 58 u32 reserved; 59 }; 60 61 /* The PCNET 32-Bit initialization block, described in databook. */ 62 struct pcnet_init_block { 63 u16 mode; 64 u16 tlen_rlen; 65 u8 phys_addr[6]; 66 u16 reserved; 67 u32 filter[2]; 68 /* Receive and transmit ring base, along with extra bits. */ 69 u32 rx_ring; 70 u32 tx_ring; 71 u32 reserved2; 72 }; 73 74 struct pcnet_uncached_priv { 75 struct pcnet_rx_head rx_ring[RX_RING_SIZE]; 76 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; 77 struct pcnet_init_block init_block; 78 }; 79 80 typedef struct pcnet_priv { 81 struct pcnet_uncached_priv *uc; 82 /* Receive Buffer space */ 83 unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4]; 84 int cur_rx; 85 int cur_tx; 86 } pcnet_priv_t; 87 88 static pcnet_priv_t *lp; 89 90 /* Offsets from base I/O address for WIO mode */ 91 #define PCNET_RDP 0x10 92 #define PCNET_RAP 0x12 93 #define PCNET_RESET 0x14 94 #define PCNET_BDP 0x16 95 96 static u16 pcnet_read_csr(struct eth_device *dev, int index) 97 { 98 outw(index, dev->iobase + PCNET_RAP); 99 return inw(dev->iobase + PCNET_RDP); 100 } 101 102 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val) 103 { 104 outw(index, dev->iobase + PCNET_RAP); 105 outw(val, dev->iobase + PCNET_RDP); 106 } 107 108 static u16 pcnet_read_bcr(struct eth_device *dev, int index) 109 { 110 outw(index, dev->iobase + PCNET_RAP); 111 return inw(dev->iobase + PCNET_BDP); 112 } 113 114 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val) 115 { 116 outw(index, dev->iobase + PCNET_RAP); 117 outw(val, dev->iobase + PCNET_BDP); 118 } 119 120 static void pcnet_reset(struct eth_device *dev) 121 { 122 inw(dev->iobase + PCNET_RESET); 123 } 124 125 static int pcnet_check(struct eth_device *dev) 126 { 127 outw(88, dev->iobase + PCNET_RAP); 128 return inw(dev->iobase + PCNET_RAP) == 88; 129 } 130 131 static int pcnet_init (struct eth_device *dev, bd_t * bis); 132 static int pcnet_send(struct eth_device *dev, void *packet, int length); 133 static int pcnet_recv (struct eth_device *dev); 134 static void pcnet_halt (struct eth_device *dev); 135 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); 136 137 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev, 138 void *addr, bool uncached) 139 { 140 pci_dev_t devbusfn = (pci_dev_t)dev->priv; 141 void *virt_addr = addr; 142 143 if (uncached) 144 virt_addr = (void *)CKSEG0ADDR(addr); 145 146 return pci_virt_to_mem(devbusfn, virt_addr); 147 } 148 149 static struct pci_device_id supported[] = { 150 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, 151 {} 152 }; 153 154 155 int pcnet_initialize(bd_t *bis) 156 { 157 pci_dev_t devbusfn; 158 struct eth_device *dev; 159 u16 command, status; 160 int dev_nr = 0; 161 162 PCNET_DEBUG1("\npcnet_initialize...\n"); 163 164 for (dev_nr = 0;; dev_nr++) { 165 166 /* 167 * Find the PCnet PCI device(s). 168 */ 169 devbusfn = pci_find_devices(supported, dev_nr); 170 if (devbusfn < 0) 171 break; 172 173 /* 174 * Allocate and pre-fill the device structure. 175 */ 176 dev = (struct eth_device *)malloc(sizeof(*dev)); 177 if (!dev) { 178 printf("pcnet: Can not allocate memory\n"); 179 break; 180 } 181 memset(dev, 0, sizeof(*dev)); 182 dev->priv = (void *)devbusfn; 183 sprintf(dev->name, "pcnet#%d", dev_nr); 184 185 /* 186 * Setup the PCI device. 187 */ 188 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, 189 (unsigned int *)&dev->iobase); 190 dev->iobase = pci_io_to_phys(devbusfn, dev->iobase); 191 dev->iobase &= ~0xf; 192 193 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ", 194 dev->name, devbusfn, dev->iobase); 195 196 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; 197 pci_write_config_word(devbusfn, PCI_COMMAND, command); 198 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 199 if ((status & command) != command) { 200 printf("%s: Couldn't enable IO access or Bus Mastering\n", 201 dev->name); 202 free(dev); 203 continue; 204 } 205 206 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); 207 208 /* 209 * Probe the PCnet chip. 210 */ 211 if (pcnet_probe(dev, bis, dev_nr) < 0) { 212 free(dev); 213 continue; 214 } 215 216 /* 217 * Setup device structure and register the driver. 218 */ 219 dev->init = pcnet_init; 220 dev->halt = pcnet_halt; 221 dev->send = pcnet_send; 222 dev->recv = pcnet_recv; 223 224 eth_register(dev); 225 } 226 227 udelay(10 * 1000); 228 229 return dev_nr; 230 } 231 232 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr) 233 { 234 int chip_version; 235 char *chipname; 236 237 #ifdef PCNET_HAS_PROM 238 int i; 239 #endif 240 241 /* Reset the PCnet controller */ 242 pcnet_reset(dev); 243 244 /* Check if register access is working */ 245 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { 246 printf("%s: CSR register access check failed\n", dev->name); 247 return -1; 248 } 249 250 /* Identify the chip */ 251 chip_version = 252 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16); 253 if ((chip_version & 0xfff) != 0x003) 254 return -1; 255 chip_version = (chip_version >> 12) & 0xffff; 256 switch (chip_version) { 257 case 0x2621: 258 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 259 break; 260 #ifdef CONFIG_PCNET_79C973 261 case 0x2625: 262 chipname = "PCnet/FAST III 79C973"; /* PCI */ 263 break; 264 #endif 265 #ifdef CONFIG_PCNET_79C975 266 case 0x2627: 267 chipname = "PCnet/FAST III 79C975"; /* PCI */ 268 break; 269 #endif 270 default: 271 printf("%s: PCnet version %#x not supported\n", 272 dev->name, chip_version); 273 return -1; 274 } 275 276 PCNET_DEBUG1("AMD %s\n", chipname); 277 278 #ifdef PCNET_HAS_PROM 279 /* 280 * In most chips, after a chip reset, the ethernet address is read from 281 * the station address PROM at the base address and programmed into the 282 * "Physical Address Registers" CSR12-14. 283 */ 284 for (i = 0; i < 3; i++) { 285 unsigned int val; 286 287 val = pcnet_read_csr(dev, i + 12) & 0x0ffff; 288 /* There may be endianness issues here. */ 289 dev->enetaddr[2 * i] = val & 0x0ff; 290 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; 291 } 292 #endif /* PCNET_HAS_PROM */ 293 294 return 0; 295 } 296 297 static int pcnet_init(struct eth_device *dev, bd_t *bis) 298 { 299 struct pcnet_uncached_priv *uc; 300 int i, val; 301 u32 addr; 302 303 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); 304 305 /* Switch pcnet to 32bit mode */ 306 pcnet_write_bcr(dev, 20, 2); 307 308 /* Set/reset autoselect bit */ 309 val = pcnet_read_bcr(dev, 2) & ~2; 310 val |= 2; 311 pcnet_write_bcr(dev, 2, val); 312 313 /* Enable auto negotiate, setup, disable fd */ 314 val = pcnet_read_bcr(dev, 32) & ~0x98; 315 val |= 0x20; 316 pcnet_write_bcr(dev, 32, val); 317 318 /* 319 * Enable NOUFLO on supported controllers, with the transmit 320 * start point set to the full packet. This will cause entire 321 * packets to be buffered by the ethernet controller before 322 * transmission, eliminating underflows which are common on 323 * slower devices. Controllers which do not support NOUFLO will 324 * simply be left with a larger transmit FIFO threshold. 325 */ 326 val = pcnet_read_bcr(dev, 18); 327 val |= 1 << 11; 328 pcnet_write_bcr(dev, 18, val); 329 val = pcnet_read_csr(dev, 80); 330 val |= 0x3 << 10; 331 pcnet_write_csr(dev, 80, val); 332 333 /* 334 * We only maintain one structure because the drivers will never 335 * be used concurrently. In 32bit mode the RX and TX ring entries 336 * must be aligned on 16-byte boundaries. 337 */ 338 if (lp == NULL) { 339 addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); 340 addr = (addr + 0xf) & ~0xf; 341 lp = (pcnet_priv_t *)addr; 342 343 addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc)); 344 flush_dcache_range(addr, addr + sizeof(*lp->uc)); 345 addr = UNCACHED_SDRAM(addr); 346 lp->uc = (struct pcnet_uncached_priv *)addr; 347 348 addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->rx_buf)); 349 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf)); 350 lp->rx_buf = (void *)addr; 351 } 352 353 uc = lp->uc; 354 355 uc->init_block.mode = cpu_to_le16(0x0000); 356 uc->init_block.filter[0] = 0x00000000; 357 uc->init_block.filter[1] = 0x00000000; 358 359 /* 360 * Initialize the Rx ring. 361 */ 362 lp->cur_rx = 0; 363 for (i = 0; i < RX_RING_SIZE; i++) { 364 addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i], false); 365 uc->rx_ring[i].base = cpu_to_le32(addr); 366 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); 367 uc->rx_ring[i].status = cpu_to_le16(0x8000); 368 PCNET_DEBUG1 369 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, 370 uc->rx_ring[i].base, uc->rx_ring[i].buf_length, 371 uc->rx_ring[i].status); 372 } 373 374 /* 375 * Initialize the Tx ring. The Tx buffer address is filled in as 376 * needed, but we do need to clear the upper ownership bit. 377 */ 378 lp->cur_tx = 0; 379 for (i = 0; i < TX_RING_SIZE; i++) { 380 uc->tx_ring[i].base = 0; 381 uc->tx_ring[i].status = 0; 382 } 383 384 /* 385 * Setup Init Block. 386 */ 387 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block); 388 389 for (i = 0; i < 6; i++) { 390 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i]; 391 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]); 392 } 393 394 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | 395 RX_RING_LEN_BITS); 396 addr = pcnet_virt_to_mem(dev, uc->rx_ring, true); 397 uc->init_block.rx_ring = cpu_to_le32(addr); 398 addr = pcnet_virt_to_mem(dev, uc->tx_ring, true); 399 uc->init_block.tx_ring = cpu_to_le32(addr); 400 401 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", 402 uc->init_block.tlen_rlen, 403 uc->init_block.rx_ring, uc->init_block.tx_ring); 404 405 /* 406 * Tell the controller where the Init Block is located. 407 */ 408 barrier(); 409 addr = pcnet_virt_to_mem(dev, &lp->uc->init_block, true); 410 pcnet_write_csr(dev, 1, addr & 0xffff); 411 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); 412 413 pcnet_write_csr(dev, 4, 0x0915); 414 pcnet_write_csr(dev, 0, 0x0001); /* start */ 415 416 /* Wait for Init Done bit */ 417 for (i = 10000; i > 0; i--) { 418 if (pcnet_read_csr(dev, 0) & 0x0100) 419 break; 420 udelay(10); 421 } 422 if (i <= 0) { 423 printf("%s: TIMEOUT: controller init failed\n", dev->name); 424 pcnet_reset(dev); 425 return -1; 426 } 427 428 /* 429 * Finally start network controller operation. 430 */ 431 pcnet_write_csr(dev, 0, 0x0002); 432 433 return 0; 434 } 435 436 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) 437 { 438 int i, status; 439 u32 addr; 440 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx]; 441 442 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, 443 packet); 444 445 flush_dcache_range((unsigned long)packet, 446 (unsigned long)packet + pkt_len); 447 448 /* Wait for completion by testing the OWN bit */ 449 for (i = 1000; i > 0; i--) { 450 status = readw(&entry->status); 451 if ((status & 0x8000) == 0) 452 break; 453 udelay(100); 454 PCNET_DEBUG2("."); 455 } 456 if (i <= 0) { 457 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", 458 dev->name, lp->cur_tx, status); 459 pkt_len = 0; 460 goto failure; 461 } 462 463 /* 464 * Setup Tx ring. Caution: the write order is important here, 465 * set the status with the "ownership" bits last. 466 */ 467 addr = pcnet_virt_to_mem(dev, packet, false); 468 writew(-pkt_len, &entry->length); 469 writel(0, &entry->misc); 470 writel(addr, &entry->base); 471 writew(0x8300, &entry->status); 472 473 /* Trigger an immediate send poll. */ 474 pcnet_write_csr(dev, 0, 0x0008); 475 476 failure: 477 if (++lp->cur_tx >= TX_RING_SIZE) 478 lp->cur_tx = 0; 479 480 PCNET_DEBUG2("done\n"); 481 return pkt_len; 482 } 483 484 static int pcnet_recv (struct eth_device *dev) 485 { 486 struct pcnet_rx_head *entry; 487 unsigned char *buf; 488 int pkt_len = 0; 489 u16 status, err_status; 490 491 while (1) { 492 entry = &lp->uc->rx_ring[lp->cur_rx]; 493 /* 494 * If we own the next entry, it's a new packet. Send it up. 495 */ 496 status = readw(&entry->status); 497 if ((status & 0x8000) != 0) 498 break; 499 err_status = status >> 8; 500 501 if (err_status != 0x03) { /* There was an error. */ 502 printf("%s: Rx%d", dev->name, lp->cur_rx); 503 PCNET_DEBUG1(" (status=0x%x)", err_status); 504 if (err_status & 0x20) 505 printf(" Frame"); 506 if (err_status & 0x10) 507 printf(" Overflow"); 508 if (err_status & 0x08) 509 printf(" CRC"); 510 if (err_status & 0x04) 511 printf(" Fifo"); 512 printf(" Error\n"); 513 status &= 0x03ff; 514 515 } else { 516 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4; 517 if (pkt_len < 60) { 518 printf("%s: Rx%d: invalid packet length %d\n", 519 dev->name, lp->cur_rx, pkt_len); 520 } else { 521 buf = (*lp->rx_buf)[lp->cur_rx]; 522 invalidate_dcache_range((unsigned long)buf, 523 (unsigned long)buf + pkt_len); 524 net_process_received_packet(buf, pkt_len); 525 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", 526 lp->cur_rx, pkt_len, buf); 527 } 528 } 529 530 status |= 0x8000; 531 writew(status, &entry->status); 532 533 if (++lp->cur_rx >= RX_RING_SIZE) 534 lp->cur_rx = 0; 535 } 536 return pkt_len; 537 } 538 539 static void pcnet_halt(struct eth_device *dev) 540 { 541 int i; 542 543 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); 544 545 /* Reset the PCnet controller */ 546 pcnet_reset(dev); 547 548 /* Wait for Stop bit */ 549 for (i = 1000; i > 0; i--) { 550 if (pcnet_read_csr(dev, 0) & 0x4) 551 break; 552 udelay(10); 553 } 554 if (i <= 0) 555 printf("%s: TIMEOUT: controller reset failed\n", dev->name); 556 } 557