1 /* 2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. 3 * 4 * This driver for AMD PCnet network controllers is derived from the 5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <net.h> 13 #include <netdev.h> 14 #include <asm/io.h> 15 #include <pci.h> 16 17 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ 18 19 #define PCNET_DEBUG1(fmt,args...) \ 20 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args) 21 #define PCNET_DEBUG2(fmt,args...) \ 22 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args) 23 24 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) 25 #error "Macro for PCnet chip version is not defined!" 26 #endif 27 28 /* 29 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 30 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 31 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 32 */ 33 #define PCNET_LOG_TX_BUFFERS 0 34 #define PCNET_LOG_RX_BUFFERS 2 35 36 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) 37 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) 38 39 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) 40 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) 41 42 #define PKT_BUF_SZ 1544 43 44 /* The PCNET Rx and Tx ring descriptors. */ 45 struct pcnet_rx_head { 46 u32 base; 47 s16 buf_length; 48 s16 status; 49 u32 msg_length; 50 u32 reserved; 51 }; 52 53 struct pcnet_tx_head { 54 u32 base; 55 s16 length; 56 s16 status; 57 u32 misc; 58 u32 reserved; 59 }; 60 61 /* The PCNET 32-Bit initialization block, described in databook. */ 62 struct pcnet_init_block { 63 u16 mode; 64 u16 tlen_rlen; 65 u8 phys_addr[6]; 66 u16 reserved; 67 u32 filter[2]; 68 /* Receive and transmit ring base, along with extra bits. */ 69 u32 rx_ring; 70 u32 tx_ring; 71 u32 reserved2; 72 }; 73 74 struct pcnet_uncached_priv { 75 struct pcnet_rx_head rx_ring[RX_RING_SIZE]; 76 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; 77 struct pcnet_init_block init_block; 78 }; 79 80 typedef struct pcnet_priv { 81 struct pcnet_uncached_priv *uc; 82 /* Receive Buffer space */ 83 unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4]; 84 int cur_rx; 85 int cur_tx; 86 } pcnet_priv_t; 87 88 static pcnet_priv_t *lp; 89 90 /* Offsets from base I/O address for WIO mode */ 91 #define PCNET_RDP 0x10 92 #define PCNET_RAP 0x12 93 #define PCNET_RESET 0x14 94 #define PCNET_BDP 0x16 95 96 static u16 pcnet_read_csr(struct eth_device *dev, int index) 97 { 98 outw(index, dev->iobase + PCNET_RAP); 99 return inw(dev->iobase + PCNET_RDP); 100 } 101 102 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val) 103 { 104 outw(index, dev->iobase + PCNET_RAP); 105 outw(val, dev->iobase + PCNET_RDP); 106 } 107 108 static u16 pcnet_read_bcr(struct eth_device *dev, int index) 109 { 110 outw(index, dev->iobase + PCNET_RAP); 111 return inw(dev->iobase + PCNET_BDP); 112 } 113 114 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val) 115 { 116 outw(index, dev->iobase + PCNET_RAP); 117 outw(val, dev->iobase + PCNET_BDP); 118 } 119 120 static void pcnet_reset(struct eth_device *dev) 121 { 122 inw(dev->iobase + PCNET_RESET); 123 } 124 125 static int pcnet_check(struct eth_device *dev) 126 { 127 outw(88, dev->iobase + PCNET_RAP); 128 return inw(dev->iobase + PCNET_RAP) == 88; 129 } 130 131 static int pcnet_init (struct eth_device *dev, bd_t * bis); 132 static int pcnet_send(struct eth_device *dev, void *packet, int length); 133 static int pcnet_recv (struct eth_device *dev); 134 static void pcnet_halt (struct eth_device *dev); 135 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); 136 137 #define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a)) 138 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) 139 140 static struct pci_device_id supported[] = { 141 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, 142 {} 143 }; 144 145 146 int pcnet_initialize(bd_t *bis) 147 { 148 pci_dev_t devbusfn; 149 struct eth_device *dev; 150 u16 command, status; 151 int dev_nr = 0; 152 153 PCNET_DEBUG1("\npcnet_initialize...\n"); 154 155 for (dev_nr = 0;; dev_nr++) { 156 157 /* 158 * Find the PCnet PCI device(s). 159 */ 160 devbusfn = pci_find_devices(supported, dev_nr); 161 if (devbusfn < 0) 162 break; 163 164 /* 165 * Allocate and pre-fill the device structure. 166 */ 167 dev = (struct eth_device *)malloc(sizeof(*dev)); 168 if (!dev) { 169 printf("pcnet: Can not allocate memory\n"); 170 break; 171 } 172 memset(dev, 0, sizeof(*dev)); 173 dev->priv = (void *)devbusfn; 174 sprintf(dev->name, "pcnet#%d", dev_nr); 175 176 /* 177 * Setup the PCI device. 178 */ 179 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, 180 (unsigned int *)&dev->iobase); 181 dev->iobase = pci_io_to_phys(devbusfn, dev->iobase); 182 dev->iobase &= ~0xf; 183 184 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%x: ", 185 dev->name, devbusfn, dev->iobase); 186 187 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; 188 pci_write_config_word(devbusfn, PCI_COMMAND, command); 189 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 190 if ((status & command) != command) { 191 printf("%s: Couldn't enable IO access or Bus Mastering\n", 192 dev->name); 193 free(dev); 194 continue; 195 } 196 197 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); 198 199 /* 200 * Probe the PCnet chip. 201 */ 202 if (pcnet_probe(dev, bis, dev_nr) < 0) { 203 free(dev); 204 continue; 205 } 206 207 /* 208 * Setup device structure and register the driver. 209 */ 210 dev->init = pcnet_init; 211 dev->halt = pcnet_halt; 212 dev->send = pcnet_send; 213 dev->recv = pcnet_recv; 214 215 eth_register(dev); 216 } 217 218 udelay(10 * 1000); 219 220 return dev_nr; 221 } 222 223 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr) 224 { 225 int chip_version; 226 char *chipname; 227 228 #ifdef PCNET_HAS_PROM 229 int i; 230 #endif 231 232 /* Reset the PCnet controller */ 233 pcnet_reset(dev); 234 235 /* Check if register access is working */ 236 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { 237 printf("%s: CSR register access check failed\n", dev->name); 238 return -1; 239 } 240 241 /* Identify the chip */ 242 chip_version = 243 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16); 244 if ((chip_version & 0xfff) != 0x003) 245 return -1; 246 chip_version = (chip_version >> 12) & 0xffff; 247 switch (chip_version) { 248 case 0x2621: 249 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 250 break; 251 #ifdef CONFIG_PCNET_79C973 252 case 0x2625: 253 chipname = "PCnet/FAST III 79C973"; /* PCI */ 254 break; 255 #endif 256 #ifdef CONFIG_PCNET_79C975 257 case 0x2627: 258 chipname = "PCnet/FAST III 79C975"; /* PCI */ 259 break; 260 #endif 261 default: 262 printf("%s: PCnet version %#x not supported\n", 263 dev->name, chip_version); 264 return -1; 265 } 266 267 PCNET_DEBUG1("AMD %s\n", chipname); 268 269 #ifdef PCNET_HAS_PROM 270 /* 271 * In most chips, after a chip reset, the ethernet address is read from 272 * the station address PROM at the base address and programmed into the 273 * "Physical Address Registers" CSR12-14. 274 */ 275 for (i = 0; i < 3; i++) { 276 unsigned int val; 277 278 val = pcnet_read_csr(dev, i + 12) & 0x0ffff; 279 /* There may be endianness issues here. */ 280 dev->enetaddr[2 * i] = val & 0x0ff; 281 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; 282 } 283 #endif /* PCNET_HAS_PROM */ 284 285 return 0; 286 } 287 288 static int pcnet_init(struct eth_device *dev, bd_t *bis) 289 { 290 struct pcnet_uncached_priv *uc; 291 int i, val; 292 u32 addr; 293 294 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); 295 296 /* Switch pcnet to 32bit mode */ 297 pcnet_write_bcr(dev, 20, 2); 298 299 /* Set/reset autoselect bit */ 300 val = pcnet_read_bcr(dev, 2) & ~2; 301 val |= 2; 302 pcnet_write_bcr(dev, 2, val); 303 304 /* Enable auto negotiate, setup, disable fd */ 305 val = pcnet_read_bcr(dev, 32) & ~0x98; 306 val |= 0x20; 307 pcnet_write_bcr(dev, 32, val); 308 309 /* 310 * Enable NOUFLO on supported controllers, with the transmit 311 * start point set to the full packet. This will cause entire 312 * packets to be buffered by the ethernet controller before 313 * transmission, eliminating underflows which are common on 314 * slower devices. Controllers which do not support NOUFLO will 315 * simply be left with a larger transmit FIFO threshold. 316 */ 317 val = pcnet_read_bcr(dev, 18); 318 val |= 1 << 11; 319 pcnet_write_bcr(dev, 18, val); 320 val = pcnet_read_csr(dev, 80); 321 val |= 0x3 << 10; 322 pcnet_write_csr(dev, 80, val); 323 324 /* 325 * We only maintain one structure because the drivers will never 326 * be used concurrently. In 32bit mode the RX and TX ring entries 327 * must be aligned on 16-byte boundaries. 328 */ 329 if (lp == NULL) { 330 addr = (u32)malloc(sizeof(pcnet_priv_t) + 0x10); 331 addr = (addr + 0xf) & ~0xf; 332 lp = (pcnet_priv_t *)addr; 333 334 addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->uc)); 335 flush_dcache_range(addr, addr + sizeof(*lp->uc)); 336 addr = UNCACHED_SDRAM(addr); 337 lp->uc = (struct pcnet_uncached_priv *)addr; 338 339 addr = (u32)memalign(ARCH_DMA_MINALIGN, sizeof(*lp->rx_buf)); 340 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf)); 341 lp->rx_buf = (void *)addr; 342 } 343 344 uc = lp->uc; 345 346 uc->init_block.mode = cpu_to_le16(0x0000); 347 uc->init_block.filter[0] = 0x00000000; 348 uc->init_block.filter[1] = 0x00000000; 349 350 /* 351 * Initialize the Rx ring. 352 */ 353 lp->cur_rx = 0; 354 for (i = 0; i < RX_RING_SIZE; i++) { 355 uc->rx_ring[i].base = PCI_TO_MEM_LE(dev, (*lp->rx_buf)[i]); 356 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); 357 uc->rx_ring[i].status = cpu_to_le16(0x8000); 358 PCNET_DEBUG1 359 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, 360 uc->rx_ring[i].base, uc->rx_ring[i].buf_length, 361 uc->rx_ring[i].status); 362 } 363 364 /* 365 * Initialize the Tx ring. The Tx buffer address is filled in as 366 * needed, but we do need to clear the upper ownership bit. 367 */ 368 lp->cur_tx = 0; 369 for (i = 0; i < TX_RING_SIZE; i++) { 370 uc->tx_ring[i].base = 0; 371 uc->tx_ring[i].status = 0; 372 } 373 374 /* 375 * Setup Init Block. 376 */ 377 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block); 378 379 for (i = 0; i < 6; i++) { 380 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i]; 381 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]); 382 } 383 384 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | 385 RX_RING_LEN_BITS); 386 uc->init_block.rx_ring = PCI_TO_MEM_LE(dev, uc->rx_ring); 387 uc->init_block.tx_ring = PCI_TO_MEM_LE(dev, uc->tx_ring); 388 389 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", 390 uc->init_block.tlen_rlen, 391 uc->init_block.rx_ring, uc->init_block.tx_ring); 392 393 /* 394 * Tell the controller where the Init Block is located. 395 */ 396 barrier(); 397 addr = PCI_TO_MEM(dev, &lp->uc->init_block); 398 pcnet_write_csr(dev, 1, addr & 0xffff); 399 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); 400 401 pcnet_write_csr(dev, 4, 0x0915); 402 pcnet_write_csr(dev, 0, 0x0001); /* start */ 403 404 /* Wait for Init Done bit */ 405 for (i = 10000; i > 0; i--) { 406 if (pcnet_read_csr(dev, 0) & 0x0100) 407 break; 408 udelay(10); 409 } 410 if (i <= 0) { 411 printf("%s: TIMEOUT: controller init failed\n", dev->name); 412 pcnet_reset(dev); 413 return -1; 414 } 415 416 /* 417 * Finally start network controller operation. 418 */ 419 pcnet_write_csr(dev, 0, 0x0002); 420 421 return 0; 422 } 423 424 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) 425 { 426 int i, status; 427 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx]; 428 429 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, 430 packet); 431 432 flush_dcache_range((unsigned long)packet, 433 (unsigned long)packet + pkt_len); 434 435 /* Wait for completion by testing the OWN bit */ 436 for (i = 1000; i > 0; i--) { 437 status = readw(&entry->status); 438 if ((status & 0x8000) == 0) 439 break; 440 udelay(100); 441 PCNET_DEBUG2("."); 442 } 443 if (i <= 0) { 444 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", 445 dev->name, lp->cur_tx, status); 446 pkt_len = 0; 447 goto failure; 448 } 449 450 /* 451 * Setup Tx ring. Caution: the write order is important here, 452 * set the status with the "ownership" bits last. 453 */ 454 writew(-pkt_len, &entry->length); 455 writel(0, &entry->misc); 456 writel(PCI_TO_MEM(dev, packet), &entry->base); 457 writew(0x8300, &entry->status); 458 459 /* Trigger an immediate send poll. */ 460 pcnet_write_csr(dev, 0, 0x0008); 461 462 failure: 463 if (++lp->cur_tx >= TX_RING_SIZE) 464 lp->cur_tx = 0; 465 466 PCNET_DEBUG2("done\n"); 467 return pkt_len; 468 } 469 470 static int pcnet_recv (struct eth_device *dev) 471 { 472 struct pcnet_rx_head *entry; 473 unsigned char *buf; 474 int pkt_len = 0; 475 u16 status, err_status; 476 477 while (1) { 478 entry = &lp->uc->rx_ring[lp->cur_rx]; 479 /* 480 * If we own the next entry, it's a new packet. Send it up. 481 */ 482 status = readw(&entry->status); 483 if ((status & 0x8000) != 0) 484 break; 485 err_status = status >> 8; 486 487 if (err_status != 0x03) { /* There was an error. */ 488 printf("%s: Rx%d", dev->name, lp->cur_rx); 489 PCNET_DEBUG1(" (status=0x%x)", err_status); 490 if (err_status & 0x20) 491 printf(" Frame"); 492 if (err_status & 0x10) 493 printf(" Overflow"); 494 if (err_status & 0x08) 495 printf(" CRC"); 496 if (err_status & 0x04) 497 printf(" Fifo"); 498 printf(" Error\n"); 499 status &= 0x03ff; 500 501 } else { 502 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4; 503 if (pkt_len < 60) { 504 printf("%s: Rx%d: invalid packet length %d\n", 505 dev->name, lp->cur_rx, pkt_len); 506 } else { 507 buf = (*lp->rx_buf)[lp->cur_rx]; 508 invalidate_dcache_range((unsigned long)buf, 509 (unsigned long)buf + pkt_len); 510 NetReceive(buf, pkt_len); 511 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", 512 lp->cur_rx, pkt_len, buf); 513 } 514 } 515 516 status |= 0x8000; 517 writew(status, &entry->status); 518 519 if (++lp->cur_rx >= RX_RING_SIZE) 520 lp->cur_rx = 0; 521 } 522 return pkt_len; 523 } 524 525 static void pcnet_halt(struct eth_device *dev) 526 { 527 int i; 528 529 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); 530 531 /* Reset the PCnet controller */ 532 pcnet_reset(dev); 533 534 /* Wait for Stop bit */ 535 for (i = 1000; i > 0; i--) { 536 if (pcnet_read_csr(dev, 0) & 0x4) 537 break; 538 udelay(10); 539 } 540 if (i <= 0) 541 printf("%s: TIMEOUT: controller reset failed\n", dev->name); 542 } 543