1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. 4 * 5 * This driver for AMD PCnet network controllers is derived from the 6 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. 7 */ 8 9 #include <common.h> 10 #include <malloc.h> 11 #include <net.h> 12 #include <netdev.h> 13 #include <asm/io.h> 14 #include <pci.h> 15 16 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ 17 18 #define PCNET_DEBUG1(fmt,args...) \ 19 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args) 20 #define PCNET_DEBUG2(fmt,args...) \ 21 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args) 22 23 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) 24 #error "Macro for PCnet chip version is not defined!" 25 #endif 26 27 /* 28 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 29 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 30 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 31 */ 32 #define PCNET_LOG_TX_BUFFERS 0 33 #define PCNET_LOG_RX_BUFFERS 2 34 35 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) 36 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) 37 38 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) 39 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) 40 41 #define PKT_BUF_SZ 1544 42 43 /* The PCNET Rx and Tx ring descriptors. */ 44 struct pcnet_rx_head { 45 u32 base; 46 s16 buf_length; 47 s16 status; 48 u32 msg_length; 49 u32 reserved; 50 }; 51 52 struct pcnet_tx_head { 53 u32 base; 54 s16 length; 55 s16 status; 56 u32 misc; 57 u32 reserved; 58 }; 59 60 /* The PCNET 32-Bit initialization block, described in databook. */ 61 struct pcnet_init_block { 62 u16 mode; 63 u16 tlen_rlen; 64 u8 phys_addr[6]; 65 u16 reserved; 66 u32 filter[2]; 67 /* Receive and transmit ring base, along with extra bits. */ 68 u32 rx_ring; 69 u32 tx_ring; 70 u32 reserved2; 71 }; 72 73 struct pcnet_uncached_priv { 74 struct pcnet_rx_head rx_ring[RX_RING_SIZE]; 75 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; 76 struct pcnet_init_block init_block; 77 }; 78 79 typedef struct pcnet_priv { 80 struct pcnet_uncached_priv *uc; 81 /* Receive Buffer space */ 82 unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4]; 83 int cur_rx; 84 int cur_tx; 85 } pcnet_priv_t; 86 87 static pcnet_priv_t *lp; 88 89 /* Offsets from base I/O address for WIO mode */ 90 #define PCNET_RDP 0x10 91 #define PCNET_RAP 0x12 92 #define PCNET_RESET 0x14 93 #define PCNET_BDP 0x16 94 95 static u16 pcnet_read_csr(struct eth_device *dev, int index) 96 { 97 outw(index, dev->iobase + PCNET_RAP); 98 return inw(dev->iobase + PCNET_RDP); 99 } 100 101 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val) 102 { 103 outw(index, dev->iobase + PCNET_RAP); 104 outw(val, dev->iobase + PCNET_RDP); 105 } 106 107 static u16 pcnet_read_bcr(struct eth_device *dev, int index) 108 { 109 outw(index, dev->iobase + PCNET_RAP); 110 return inw(dev->iobase + PCNET_BDP); 111 } 112 113 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val) 114 { 115 outw(index, dev->iobase + PCNET_RAP); 116 outw(val, dev->iobase + PCNET_BDP); 117 } 118 119 static void pcnet_reset(struct eth_device *dev) 120 { 121 inw(dev->iobase + PCNET_RESET); 122 } 123 124 static int pcnet_check(struct eth_device *dev) 125 { 126 outw(88, dev->iobase + PCNET_RAP); 127 return inw(dev->iobase + PCNET_RAP) == 88; 128 } 129 130 static int pcnet_init (struct eth_device *dev, bd_t * bis); 131 static int pcnet_send(struct eth_device *dev, void *packet, int length); 132 static int pcnet_recv (struct eth_device *dev); 133 static void pcnet_halt (struct eth_device *dev); 134 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); 135 136 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev, 137 void *addr) 138 { 139 pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv; 140 void *virt_addr = addr; 141 142 return pci_virt_to_mem(devbusfn, virt_addr); 143 } 144 145 static struct pci_device_id supported[] = { 146 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, 147 {} 148 }; 149 150 151 int pcnet_initialize(bd_t *bis) 152 { 153 pci_dev_t devbusfn; 154 struct eth_device *dev; 155 u16 command, status; 156 int dev_nr = 0; 157 u32 bar; 158 159 PCNET_DEBUG1("\npcnet_initialize...\n"); 160 161 for (dev_nr = 0;; dev_nr++) { 162 163 /* 164 * Find the PCnet PCI device(s). 165 */ 166 devbusfn = pci_find_devices(supported, dev_nr); 167 if (devbusfn < 0) 168 break; 169 170 /* 171 * Allocate and pre-fill the device structure. 172 */ 173 dev = (struct eth_device *)malloc(sizeof(*dev)); 174 if (!dev) { 175 printf("pcnet: Can not allocate memory\n"); 176 break; 177 } 178 memset(dev, 0, sizeof(*dev)); 179 dev->priv = (void *)(unsigned long)devbusfn; 180 sprintf(dev->name, "pcnet#%d", dev_nr); 181 182 /* 183 * Setup the PCI device. 184 */ 185 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar); 186 dev->iobase = pci_io_to_phys(devbusfn, bar); 187 dev->iobase &= ~0xf; 188 189 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ", 190 dev->name, devbusfn, (unsigned long)dev->iobase); 191 192 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; 193 pci_write_config_word(devbusfn, PCI_COMMAND, command); 194 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 195 if ((status & command) != command) { 196 printf("%s: Couldn't enable IO access or Bus Mastering\n", 197 dev->name); 198 free(dev); 199 continue; 200 } 201 202 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); 203 204 /* 205 * Probe the PCnet chip. 206 */ 207 if (pcnet_probe(dev, bis, dev_nr) < 0) { 208 free(dev); 209 continue; 210 } 211 212 /* 213 * Setup device structure and register the driver. 214 */ 215 dev->init = pcnet_init; 216 dev->halt = pcnet_halt; 217 dev->send = pcnet_send; 218 dev->recv = pcnet_recv; 219 220 eth_register(dev); 221 } 222 223 udelay(10 * 1000); 224 225 return dev_nr; 226 } 227 228 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr) 229 { 230 int chip_version; 231 char *chipname; 232 233 #ifdef PCNET_HAS_PROM 234 int i; 235 #endif 236 237 /* Reset the PCnet controller */ 238 pcnet_reset(dev); 239 240 /* Check if register access is working */ 241 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { 242 printf("%s: CSR register access check failed\n", dev->name); 243 return -1; 244 } 245 246 /* Identify the chip */ 247 chip_version = 248 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16); 249 if ((chip_version & 0xfff) != 0x003) 250 return -1; 251 chip_version = (chip_version >> 12) & 0xffff; 252 switch (chip_version) { 253 case 0x2621: 254 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 255 break; 256 #ifdef CONFIG_PCNET_79C973 257 case 0x2625: 258 chipname = "PCnet/FAST III 79C973"; /* PCI */ 259 break; 260 #endif 261 #ifdef CONFIG_PCNET_79C975 262 case 0x2627: 263 chipname = "PCnet/FAST III 79C975"; /* PCI */ 264 break; 265 #endif 266 default: 267 printf("%s: PCnet version %#x not supported\n", 268 dev->name, chip_version); 269 return -1; 270 } 271 272 PCNET_DEBUG1("AMD %s\n", chipname); 273 274 #ifdef PCNET_HAS_PROM 275 /* 276 * In most chips, after a chip reset, the ethernet address is read from 277 * the station address PROM at the base address and programmed into the 278 * "Physical Address Registers" CSR12-14. 279 */ 280 for (i = 0; i < 3; i++) { 281 unsigned int val; 282 283 val = pcnet_read_csr(dev, i + 12) & 0x0ffff; 284 /* There may be endianness issues here. */ 285 dev->enetaddr[2 * i] = val & 0x0ff; 286 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; 287 } 288 #endif /* PCNET_HAS_PROM */ 289 290 return 0; 291 } 292 293 static int pcnet_init(struct eth_device *dev, bd_t *bis) 294 { 295 struct pcnet_uncached_priv *uc; 296 int i, val; 297 unsigned long addr; 298 299 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); 300 301 /* Switch pcnet to 32bit mode */ 302 pcnet_write_bcr(dev, 20, 2); 303 304 /* Set/reset autoselect bit */ 305 val = pcnet_read_bcr(dev, 2) & ~2; 306 val |= 2; 307 pcnet_write_bcr(dev, 2, val); 308 309 /* Enable auto negotiate, setup, disable fd */ 310 val = pcnet_read_bcr(dev, 32) & ~0x98; 311 val |= 0x20; 312 pcnet_write_bcr(dev, 32, val); 313 314 /* 315 * Enable NOUFLO on supported controllers, with the transmit 316 * start point set to the full packet. This will cause entire 317 * packets to be buffered by the ethernet controller before 318 * transmission, eliminating underflows which are common on 319 * slower devices. Controllers which do not support NOUFLO will 320 * simply be left with a larger transmit FIFO threshold. 321 */ 322 val = pcnet_read_bcr(dev, 18); 323 val |= 1 << 11; 324 pcnet_write_bcr(dev, 18, val); 325 val = pcnet_read_csr(dev, 80); 326 val |= 0x3 << 10; 327 pcnet_write_csr(dev, 80, val); 328 329 /* 330 * We only maintain one structure because the drivers will never 331 * be used concurrently. In 32bit mode the RX and TX ring entries 332 * must be aligned on 16-byte boundaries. 333 */ 334 if (lp == NULL) { 335 addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10); 336 addr = (addr + 0xf) & ~0xf; 337 lp = (pcnet_priv_t *)addr; 338 339 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN, 340 sizeof(*lp->uc)); 341 flush_dcache_range(addr, addr + sizeof(*lp->uc)); 342 addr = UNCACHED_SDRAM(addr); 343 lp->uc = (struct pcnet_uncached_priv *)addr; 344 345 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN, 346 sizeof(*lp->rx_buf)); 347 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf)); 348 lp->rx_buf = (void *)addr; 349 } 350 351 uc = lp->uc; 352 353 uc->init_block.mode = cpu_to_le16(0x0000); 354 uc->init_block.filter[0] = 0x00000000; 355 uc->init_block.filter[1] = 0x00000000; 356 357 /* 358 * Initialize the Rx ring. 359 */ 360 lp->cur_rx = 0; 361 for (i = 0; i < RX_RING_SIZE; i++) { 362 addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]); 363 uc->rx_ring[i].base = cpu_to_le32(addr); 364 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); 365 uc->rx_ring[i].status = cpu_to_le16(0x8000); 366 PCNET_DEBUG1 367 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, 368 uc->rx_ring[i].base, uc->rx_ring[i].buf_length, 369 uc->rx_ring[i].status); 370 } 371 372 /* 373 * Initialize the Tx ring. The Tx buffer address is filled in as 374 * needed, but we do need to clear the upper ownership bit. 375 */ 376 lp->cur_tx = 0; 377 for (i = 0; i < TX_RING_SIZE; i++) { 378 uc->tx_ring[i].base = 0; 379 uc->tx_ring[i].status = 0; 380 } 381 382 /* 383 * Setup Init Block. 384 */ 385 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block); 386 387 for (i = 0; i < 6; i++) { 388 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i]; 389 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]); 390 } 391 392 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | 393 RX_RING_LEN_BITS); 394 addr = pcnet_virt_to_mem(dev, uc->rx_ring); 395 uc->init_block.rx_ring = cpu_to_le32(addr); 396 addr = pcnet_virt_to_mem(dev, uc->tx_ring); 397 uc->init_block.tx_ring = cpu_to_le32(addr); 398 399 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", 400 uc->init_block.tlen_rlen, 401 uc->init_block.rx_ring, uc->init_block.tx_ring); 402 403 /* 404 * Tell the controller where the Init Block is located. 405 */ 406 barrier(); 407 addr = pcnet_virt_to_mem(dev, &lp->uc->init_block); 408 pcnet_write_csr(dev, 1, addr & 0xffff); 409 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); 410 411 pcnet_write_csr(dev, 4, 0x0915); 412 pcnet_write_csr(dev, 0, 0x0001); /* start */ 413 414 /* Wait for Init Done bit */ 415 for (i = 10000; i > 0; i--) { 416 if (pcnet_read_csr(dev, 0) & 0x0100) 417 break; 418 udelay(10); 419 } 420 if (i <= 0) { 421 printf("%s: TIMEOUT: controller init failed\n", dev->name); 422 pcnet_reset(dev); 423 return -1; 424 } 425 426 /* 427 * Finally start network controller operation. 428 */ 429 pcnet_write_csr(dev, 0, 0x0002); 430 431 return 0; 432 } 433 434 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) 435 { 436 int i, status; 437 u32 addr; 438 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx]; 439 440 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, 441 packet); 442 443 flush_dcache_range((unsigned long)packet, 444 (unsigned long)packet + pkt_len); 445 446 /* Wait for completion by testing the OWN bit */ 447 for (i = 1000; i > 0; i--) { 448 status = readw(&entry->status); 449 if ((status & 0x8000) == 0) 450 break; 451 udelay(100); 452 PCNET_DEBUG2("."); 453 } 454 if (i <= 0) { 455 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", 456 dev->name, lp->cur_tx, status); 457 pkt_len = 0; 458 goto failure; 459 } 460 461 /* 462 * Setup Tx ring. Caution: the write order is important here, 463 * set the status with the "ownership" bits last. 464 */ 465 addr = pcnet_virt_to_mem(dev, packet); 466 writew(-pkt_len, &entry->length); 467 writel(0, &entry->misc); 468 writel(addr, &entry->base); 469 writew(0x8300, &entry->status); 470 471 /* Trigger an immediate send poll. */ 472 pcnet_write_csr(dev, 0, 0x0008); 473 474 failure: 475 if (++lp->cur_tx >= TX_RING_SIZE) 476 lp->cur_tx = 0; 477 478 PCNET_DEBUG2("done\n"); 479 return pkt_len; 480 } 481 482 static int pcnet_recv (struct eth_device *dev) 483 { 484 struct pcnet_rx_head *entry; 485 unsigned char *buf; 486 int pkt_len = 0; 487 u16 status, err_status; 488 489 while (1) { 490 entry = &lp->uc->rx_ring[lp->cur_rx]; 491 /* 492 * If we own the next entry, it's a new packet. Send it up. 493 */ 494 status = readw(&entry->status); 495 if ((status & 0x8000) != 0) 496 break; 497 err_status = status >> 8; 498 499 if (err_status != 0x03) { /* There was an error. */ 500 printf("%s: Rx%d", dev->name, lp->cur_rx); 501 PCNET_DEBUG1(" (status=0x%x)", err_status); 502 if (err_status & 0x20) 503 printf(" Frame"); 504 if (err_status & 0x10) 505 printf(" Overflow"); 506 if (err_status & 0x08) 507 printf(" CRC"); 508 if (err_status & 0x04) 509 printf(" Fifo"); 510 printf(" Error\n"); 511 status &= 0x03ff; 512 513 } else { 514 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4; 515 if (pkt_len < 60) { 516 printf("%s: Rx%d: invalid packet length %d\n", 517 dev->name, lp->cur_rx, pkt_len); 518 } else { 519 buf = (*lp->rx_buf)[lp->cur_rx]; 520 invalidate_dcache_range((unsigned long)buf, 521 (unsigned long)buf + pkt_len); 522 net_process_received_packet(buf, pkt_len); 523 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", 524 lp->cur_rx, pkt_len, buf); 525 } 526 } 527 528 status |= 0x8000; 529 writew(status, &entry->status); 530 531 if (++lp->cur_rx >= RX_RING_SIZE) 532 lp->cur_rx = 0; 533 } 534 return pkt_len; 535 } 536 537 static void pcnet_halt(struct eth_device *dev) 538 { 539 int i; 540 541 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); 542 543 /* Reset the PCnet controller */ 544 pcnet_reset(dev); 545 546 /* Wait for Stop bit */ 547 for (i = 1000; i > 0; i--) { 548 if (pcnet_read_csr(dev, 0) & 0x4) 549 break; 550 udelay(10); 551 } 552 if (i <= 0) 553 printf("%s: TIMEOUT: controller reset failed\n", dev->name); 554 } 555