1 /* 2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. 3 * 4 * This driver for AMD PCnet network controllers is derived from the 5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <malloc.h> 28 #include <net.h> 29 #include <netdev.h> 30 #include <asm/io.h> 31 #include <pci.h> 32 33 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ 34 35 #define PCNET_DEBUG1(fmt,args...) \ 36 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args) 37 #define PCNET_DEBUG2(fmt,args...) \ 38 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args) 39 40 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) 41 #error "Macro for PCnet chip version is not defined!" 42 #endif 43 44 /* 45 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 46 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 47 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 48 */ 49 #define PCNET_LOG_TX_BUFFERS 0 50 #define PCNET_LOG_RX_BUFFERS 2 51 52 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) 53 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) 54 55 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) 56 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) 57 58 #define PKT_BUF_SZ 1544 59 60 /* The PCNET Rx and Tx ring descriptors. */ 61 struct pcnet_rx_head { 62 u32 base; 63 s16 buf_length; 64 s16 status; 65 u32 msg_length; 66 u32 reserved; 67 }; 68 69 struct pcnet_tx_head { 70 u32 base; 71 s16 length; 72 s16 status; 73 u32 misc; 74 u32 reserved; 75 }; 76 77 /* The PCNET 32-Bit initialization block, described in databook. */ 78 struct pcnet_init_block { 79 u16 mode; 80 u16 tlen_rlen; 81 u8 phys_addr[6]; 82 u16 reserved; 83 u32 filter[2]; 84 /* Receive and transmit ring base, along with extra bits. */ 85 u32 rx_ring; 86 u32 tx_ring; 87 u32 reserved2; 88 }; 89 90 typedef struct pcnet_priv { 91 struct pcnet_rx_head rx_ring[RX_RING_SIZE]; 92 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; 93 struct pcnet_init_block init_block; 94 /* Receive Buffer space */ 95 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; 96 int cur_rx; 97 int cur_tx; 98 } pcnet_priv_t; 99 100 static pcnet_priv_t *lp; 101 102 /* Offsets from base I/O address for WIO mode */ 103 #define PCNET_RDP 0x10 104 #define PCNET_RAP 0x12 105 #define PCNET_RESET 0x14 106 #define PCNET_BDP 0x16 107 108 static u16 pcnet_read_csr (struct eth_device *dev, int index) 109 { 110 outw (index, dev->iobase + PCNET_RAP); 111 return inw (dev->iobase + PCNET_RDP); 112 } 113 114 static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) 115 { 116 outw (index, dev->iobase + PCNET_RAP); 117 outw (val, dev->iobase + PCNET_RDP); 118 } 119 120 static u16 pcnet_read_bcr (struct eth_device *dev, int index) 121 { 122 outw (index, dev->iobase + PCNET_RAP); 123 return inw (dev->iobase + PCNET_BDP); 124 } 125 126 static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) 127 { 128 outw (index, dev->iobase + PCNET_RAP); 129 outw (val, dev->iobase + PCNET_BDP); 130 } 131 132 static void pcnet_reset (struct eth_device *dev) 133 { 134 inw (dev->iobase + PCNET_RESET); 135 } 136 137 static int pcnet_check (struct eth_device *dev) 138 { 139 outw (88, dev->iobase + PCNET_RAP); 140 return (inw (dev->iobase + PCNET_RAP) == 88); 141 } 142 143 static int pcnet_init (struct eth_device *dev, bd_t * bis); 144 static int pcnet_send(struct eth_device *dev, void *packet, int length); 145 static int pcnet_recv (struct eth_device *dev); 146 static void pcnet_halt (struct eth_device *dev); 147 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); 148 149 #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a)) 150 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) 151 152 static struct pci_device_id supported[] = { 153 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, 154 {} 155 }; 156 157 158 int pcnet_initialize (bd_t * bis) 159 { 160 pci_dev_t devbusfn; 161 struct eth_device *dev; 162 u16 command, status; 163 int dev_nr = 0; 164 165 PCNET_DEBUG1 ("\npcnet_initialize...\n"); 166 167 for (dev_nr = 0;; dev_nr++) { 168 169 /* 170 * Find the PCnet PCI device(s). 171 */ 172 if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) { 173 break; 174 } 175 176 /* 177 * Allocate and pre-fill the device structure. 178 */ 179 dev = (struct eth_device *) malloc (sizeof *dev); 180 if (!dev) { 181 printf("pcnet: Can not allocate memory\n"); 182 break; 183 } 184 memset(dev, 0, sizeof(*dev)); 185 dev->priv = (void *) devbusfn; 186 sprintf (dev->name, "pcnet#%d", dev_nr); 187 188 /* 189 * Setup the PCI device. 190 */ 191 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, 192 (unsigned int *) &dev->iobase); 193 dev->iobase=pci_io_to_phys (devbusfn, dev->iobase); 194 dev->iobase &= ~0xf; 195 196 PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ", 197 dev->name, devbusfn, dev->iobase); 198 199 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; 200 pci_write_config_word (devbusfn, PCI_COMMAND, command); 201 pci_read_config_word (devbusfn, PCI_COMMAND, &status); 202 if ((status & command) != command) { 203 printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name); 204 free (dev); 205 continue; 206 } 207 208 pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40); 209 210 /* 211 * Probe the PCnet chip. 212 */ 213 if (pcnet_probe (dev, bis, dev_nr) < 0) { 214 free (dev); 215 continue; 216 } 217 218 /* 219 * Setup device structure and register the driver. 220 */ 221 dev->init = pcnet_init; 222 dev->halt = pcnet_halt; 223 dev->send = pcnet_send; 224 dev->recv = pcnet_recv; 225 226 eth_register (dev); 227 } 228 229 udelay (10 * 1000); 230 231 return dev_nr; 232 } 233 234 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) 235 { 236 int chip_version; 237 char *chipname; 238 239 #ifdef PCNET_HAS_PROM 240 int i; 241 #endif 242 243 /* Reset the PCnet controller */ 244 pcnet_reset (dev); 245 246 /* Check if register access is working */ 247 if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) { 248 printf ("%s: CSR register access check failed\n", dev->name); 249 return -1; 250 } 251 252 /* Identify the chip */ 253 chip_version = 254 pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16); 255 if ((chip_version & 0xfff) != 0x003) 256 return -1; 257 chip_version = (chip_version >> 12) & 0xffff; 258 switch (chip_version) { 259 case 0x2621: 260 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 261 break; 262 #ifdef CONFIG_PCNET_79C973 263 case 0x2625: 264 chipname = "PCnet/FAST III 79C973"; /* PCI */ 265 break; 266 #endif 267 #ifdef CONFIG_PCNET_79C975 268 case 0x2627: 269 chipname = "PCnet/FAST III 79C975"; /* PCI */ 270 break; 271 #endif 272 default: 273 printf ("%s: PCnet version %#x not supported\n", 274 dev->name, chip_version); 275 return -1; 276 } 277 278 PCNET_DEBUG1 ("AMD %s\n", chipname); 279 280 #ifdef PCNET_HAS_PROM 281 /* 282 * In most chips, after a chip reset, the ethernet address is read from 283 * the station address PROM at the base address and programmed into the 284 * "Physical Address Registers" CSR12-14. 285 */ 286 for (i = 0; i < 3; i++) { 287 unsigned int val; 288 289 val = pcnet_read_csr (dev, i + 12) & 0x0ffff; 290 /* There may be endianness issues here. */ 291 dev->enetaddr[2 * i] = val & 0x0ff; 292 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; 293 } 294 #endif /* PCNET_HAS_PROM */ 295 296 return 0; 297 } 298 299 static int pcnet_init (struct eth_device *dev, bd_t * bis) 300 { 301 int i, val; 302 u32 addr; 303 304 PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name); 305 306 /* Switch pcnet to 32bit mode */ 307 pcnet_write_bcr (dev, 20, 2); 308 309 #ifdef CONFIG_PN62 310 /* Setup LED registers */ 311 val = pcnet_read_bcr (dev, 2) | 0x1000; 312 pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ 313 pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ 314 pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ 315 pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ 316 pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ 317 #endif 318 319 /* Set/reset autoselect bit */ 320 val = pcnet_read_bcr (dev, 2) & ~2; 321 val |= 2; 322 pcnet_write_bcr (dev, 2, val); 323 324 /* Enable auto negotiate, setup, disable fd */ 325 val = pcnet_read_bcr (dev, 32) & ~0x98; 326 val |= 0x20; 327 pcnet_write_bcr (dev, 32, val); 328 329 /* 330 * We only maintain one structure because the drivers will never 331 * be used concurrently. In 32bit mode the RX and TX ring entries 332 * must be aligned on 16-byte boundaries. 333 */ 334 if (lp == NULL) { 335 addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10); 336 addr = (addr + 0xf) & ~0xf; 337 lp = (pcnet_priv_t *) addr; 338 } 339 340 lp->init_block.mode = cpu_to_le16 (0x0000); 341 lp->init_block.filter[0] = 0x00000000; 342 lp->init_block.filter[1] = 0x00000000; 343 344 /* 345 * Initialize the Rx ring. 346 */ 347 lp->cur_rx = 0; 348 for (i = 0; i < RX_RING_SIZE; i++) { 349 lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]); 350 lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ); 351 lp->rx_ring[i].status = cpu_to_le16 (0x8000); 352 PCNET_DEBUG1 353 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, 354 lp->rx_ring[i].base, lp->rx_ring[i].buf_length, 355 lp->rx_ring[i].status); 356 } 357 358 /* 359 * Initialize the Tx ring. The Tx buffer address is filled in as 360 * needed, but we do need to clear the upper ownership bit. 361 */ 362 lp->cur_tx = 0; 363 for (i = 0; i < TX_RING_SIZE; i++) { 364 lp->tx_ring[i].base = 0; 365 lp->tx_ring[i].status = 0; 366 } 367 368 /* 369 * Setup Init Block. 370 */ 371 PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block); 372 373 for (i = 0; i < 6; i++) { 374 lp->init_block.phys_addr[i] = dev->enetaddr[i]; 375 PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]); 376 } 377 378 lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS | 379 RX_RING_LEN_BITS); 380 lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring); 381 lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring); 382 383 PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", 384 lp->init_block.tlen_rlen, 385 lp->init_block.rx_ring, lp->init_block.tx_ring); 386 387 /* 388 * Tell the controller where the Init Block is located. 389 */ 390 addr = PCI_TO_MEM (dev, &lp->init_block); 391 pcnet_write_csr (dev, 1, addr & 0xffff); 392 pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff); 393 394 pcnet_write_csr (dev, 4, 0x0915); 395 pcnet_write_csr (dev, 0, 0x0001); /* start */ 396 397 /* Wait for Init Done bit */ 398 for (i = 10000; i > 0; i--) { 399 if (pcnet_read_csr (dev, 0) & 0x0100) 400 break; 401 udelay (10); 402 } 403 if (i <= 0) { 404 printf ("%s: TIMEOUT: controller init failed\n", dev->name); 405 pcnet_reset (dev); 406 return -1; 407 } 408 409 /* 410 * Finally start network controller operation. 411 */ 412 pcnet_write_csr (dev, 0, 0x0002); 413 414 return 0; 415 } 416 417 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) 418 { 419 int i, status; 420 struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; 421 422 PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, 423 packet); 424 425 /* Wait for completion by testing the OWN bit */ 426 for (i = 1000; i > 0; i--) { 427 status = le16_to_cpu (entry->status); 428 if ((status & 0x8000) == 0) 429 break; 430 udelay (100); 431 PCNET_DEBUG2 ("."); 432 } 433 if (i <= 0) { 434 printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", 435 dev->name, lp->cur_tx, status); 436 pkt_len = 0; 437 goto failure; 438 } 439 440 /* 441 * Setup Tx ring. Caution: the write order is important here, 442 * set the status with the "ownership" bits last. 443 */ 444 status = 0x8300; 445 entry->length = le16_to_cpu (-pkt_len); 446 entry->misc = 0x00000000; 447 entry->base = PCI_TO_MEM_LE (dev, packet); 448 entry->status = le16_to_cpu (status); 449 450 /* Trigger an immediate send poll. */ 451 pcnet_write_csr (dev, 0, 0x0008); 452 453 failure: 454 if (++lp->cur_tx >= TX_RING_SIZE) 455 lp->cur_tx = 0; 456 457 PCNET_DEBUG2 ("done\n"); 458 return pkt_len; 459 } 460 461 static int pcnet_recv (struct eth_device *dev) 462 { 463 struct pcnet_rx_head *entry; 464 int pkt_len = 0; 465 u16 status; 466 467 while (1) { 468 entry = &lp->rx_ring[lp->cur_rx]; 469 /* 470 * If we own the next entry, it's a new packet. Send it up. 471 */ 472 if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) { 473 break; 474 } 475 status >>= 8; 476 477 if (status != 0x03) { /* There was an error. */ 478 479 printf ("%s: Rx%d", dev->name, lp->cur_rx); 480 PCNET_DEBUG1 (" (status=0x%x)", status); 481 if (status & 0x20) 482 printf (" Frame"); 483 if (status & 0x10) 484 printf (" Overflow"); 485 if (status & 0x08) 486 printf (" CRC"); 487 if (status & 0x04) 488 printf (" Fifo"); 489 printf (" Error\n"); 490 entry->status &= le16_to_cpu (0x03ff); 491 492 } else { 493 494 pkt_len = 495 (le32_to_cpu (entry->msg_length) & 0xfff) - 4; 496 if (pkt_len < 60) { 497 printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); 498 } else { 499 NetReceive (lp->rx_buf[lp->cur_rx], pkt_len); 500 PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n", 501 lp->cur_rx, pkt_len, 502 lp->rx_buf[lp->cur_rx]); 503 } 504 } 505 entry->status |= cpu_to_le16 (0x8000); 506 507 if (++lp->cur_rx >= RX_RING_SIZE) 508 lp->cur_rx = 0; 509 } 510 return pkt_len; 511 } 512 513 static void pcnet_halt (struct eth_device *dev) 514 { 515 int i; 516 517 PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name); 518 519 /* Reset the PCnet controller */ 520 pcnet_reset (dev); 521 522 /* Wait for Stop bit */ 523 for (i = 1000; i > 0; i--) { 524 if (pcnet_read_csr (dev, 0) & 0x4) 525 break; 526 udelay (10); 527 } 528 if (i <= 0) { 529 printf ("%s: TIMEOUT: controller reset failed\n", dev->name); 530 } 531 } 532