1 /* 2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. 3 * 4 * This driver for AMD PCnet network controllers is derived from the 5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <malloc.h> 28 #include <net.h> 29 #include <netdev.h> 30 #include <asm/io.h> 31 #include <pci.h> 32 33 #if 0 34 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ 35 #endif 36 37 #if PCNET_DEBUG_LEVEL > 0 38 #define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args) 39 #if PCNET_DEBUG_LEVEL > 1 40 #define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args) 41 #else 42 #define PCNET_DEBUG2(fmt,args...) 43 #endif 44 #else 45 #define PCNET_DEBUG1(fmt,args...) 46 #define PCNET_DEBUG2(fmt,args...) 47 #endif 48 49 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) 50 #error "Macro for PCnet chip version is not defined!" 51 #endif 52 53 /* 54 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 55 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 56 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 57 */ 58 #define PCNET_LOG_TX_BUFFERS 0 59 #define PCNET_LOG_RX_BUFFERS 2 60 61 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) 62 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) 63 64 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) 65 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) 66 67 #define PKT_BUF_SZ 1544 68 69 /* The PCNET Rx and Tx ring descriptors. */ 70 struct pcnet_rx_head { 71 u32 base; 72 s16 buf_length; 73 s16 status; 74 u32 msg_length; 75 u32 reserved; 76 }; 77 78 struct pcnet_tx_head { 79 u32 base; 80 s16 length; 81 s16 status; 82 u32 misc; 83 u32 reserved; 84 }; 85 86 /* The PCNET 32-Bit initialization block, described in databook. */ 87 struct pcnet_init_block { 88 u16 mode; 89 u16 tlen_rlen; 90 u8 phys_addr[6]; 91 u16 reserved; 92 u32 filter[2]; 93 /* Receive and transmit ring base, along with extra bits. */ 94 u32 rx_ring; 95 u32 tx_ring; 96 u32 reserved2; 97 }; 98 99 typedef struct pcnet_priv { 100 struct pcnet_rx_head rx_ring[RX_RING_SIZE]; 101 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; 102 struct pcnet_init_block init_block; 103 /* Receive Buffer space */ 104 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; 105 int cur_rx; 106 int cur_tx; 107 } pcnet_priv_t; 108 109 static pcnet_priv_t *lp; 110 111 /* Offsets from base I/O address for WIO mode */ 112 #define PCNET_RDP 0x10 113 #define PCNET_RAP 0x12 114 #define PCNET_RESET 0x14 115 #define PCNET_BDP 0x16 116 117 static u16 pcnet_read_csr (struct eth_device *dev, int index) 118 { 119 outw (index, dev->iobase + PCNET_RAP); 120 return inw (dev->iobase + PCNET_RDP); 121 } 122 123 static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) 124 { 125 outw (index, dev->iobase + PCNET_RAP); 126 outw (val, dev->iobase + PCNET_RDP); 127 } 128 129 static u16 pcnet_read_bcr (struct eth_device *dev, int index) 130 { 131 outw (index, dev->iobase + PCNET_RAP); 132 return inw (dev->iobase + PCNET_BDP); 133 } 134 135 static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) 136 { 137 outw (index, dev->iobase + PCNET_RAP); 138 outw (val, dev->iobase + PCNET_BDP); 139 } 140 141 static void pcnet_reset (struct eth_device *dev) 142 { 143 inw (dev->iobase + PCNET_RESET); 144 } 145 146 static int pcnet_check (struct eth_device *dev) 147 { 148 outw (88, dev->iobase + PCNET_RAP); 149 return (inw (dev->iobase + PCNET_RAP) == 88); 150 } 151 152 static int pcnet_init (struct eth_device *dev, bd_t * bis); 153 static int pcnet_send (struct eth_device *dev, volatile void *packet, 154 int length); 155 static int pcnet_recv (struct eth_device *dev); 156 static void pcnet_halt (struct eth_device *dev); 157 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); 158 159 #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a)) 160 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) 161 162 static struct pci_device_id supported[] = { 163 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, 164 {} 165 }; 166 167 168 int pcnet_initialize (bd_t * bis) 169 { 170 pci_dev_t devbusfn; 171 struct eth_device *dev; 172 u16 command, status; 173 int dev_nr = 0; 174 175 PCNET_DEBUG1 ("\npcnet_initialize...\n"); 176 177 for (dev_nr = 0;; dev_nr++) { 178 179 /* 180 * Find the PCnet PCI device(s). 181 */ 182 if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) { 183 break; 184 } 185 186 /* 187 * Allocate and pre-fill the device structure. 188 */ 189 dev = (struct eth_device *) malloc (sizeof *dev); 190 if (!dev) { 191 printf("pcnet: Can not allocate memory\n"); 192 break; 193 } 194 memset(dev, 0, sizeof(*dev)); 195 dev->priv = (void *) devbusfn; 196 sprintf (dev->name, "pcnet#%d", dev_nr); 197 198 /* 199 * Setup the PCI device. 200 */ 201 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, 202 (unsigned int *) &dev->iobase); 203 dev->iobase=pci_io_to_phys (devbusfn, dev->iobase); 204 dev->iobase &= ~0xf; 205 206 PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ", 207 dev->name, devbusfn, dev->iobase); 208 209 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; 210 pci_write_config_word (devbusfn, PCI_COMMAND, command); 211 pci_read_config_word (devbusfn, PCI_COMMAND, &status); 212 if ((status & command) != command) { 213 printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name); 214 free (dev); 215 continue; 216 } 217 218 pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40); 219 220 /* 221 * Probe the PCnet chip. 222 */ 223 if (pcnet_probe (dev, bis, dev_nr) < 0) { 224 free (dev); 225 continue; 226 } 227 228 /* 229 * Setup device structure and register the driver. 230 */ 231 dev->init = pcnet_init; 232 dev->halt = pcnet_halt; 233 dev->send = pcnet_send; 234 dev->recv = pcnet_recv; 235 236 eth_register (dev); 237 } 238 239 udelay (10 * 1000); 240 241 return dev_nr; 242 } 243 244 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) 245 { 246 int chip_version; 247 char *chipname; 248 249 #ifdef PCNET_HAS_PROM 250 int i; 251 #endif 252 253 /* Reset the PCnet controller */ 254 pcnet_reset (dev); 255 256 /* Check if register access is working */ 257 if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) { 258 printf ("%s: CSR register access check failed\n", dev->name); 259 return -1; 260 } 261 262 /* Identify the chip */ 263 chip_version = 264 pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16); 265 if ((chip_version & 0xfff) != 0x003) 266 return -1; 267 chip_version = (chip_version >> 12) & 0xffff; 268 switch (chip_version) { 269 case 0x2621: 270 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 271 break; 272 #ifdef CONFIG_PCNET_79C973 273 case 0x2625: 274 chipname = "PCnet/FAST III 79C973"; /* PCI */ 275 break; 276 #endif 277 #ifdef CONFIG_PCNET_79C975 278 case 0x2627: 279 chipname = "PCnet/FAST III 79C975"; /* PCI */ 280 break; 281 #endif 282 default: 283 printf ("%s: PCnet version %#x not supported\n", 284 dev->name, chip_version); 285 return -1; 286 } 287 288 PCNET_DEBUG1 ("AMD %s\n", chipname); 289 290 #ifdef PCNET_HAS_PROM 291 /* 292 * In most chips, after a chip reset, the ethernet address is read from 293 * the station address PROM at the base address and programmed into the 294 * "Physical Address Registers" CSR12-14. 295 */ 296 for (i = 0; i < 3; i++) { 297 unsigned int val; 298 299 val = pcnet_read_csr (dev, i + 12) & 0x0ffff; 300 /* There may be endianness issues here. */ 301 dev->enetaddr[2 * i] = val & 0x0ff; 302 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; 303 } 304 #endif /* PCNET_HAS_PROM */ 305 306 return 0; 307 } 308 309 static int pcnet_init (struct eth_device *dev, bd_t * bis) 310 { 311 int i, val; 312 u32 addr; 313 314 PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name); 315 316 /* Switch pcnet to 32bit mode */ 317 pcnet_write_bcr (dev, 20, 2); 318 319 #ifdef CONFIG_PN62 320 /* Setup LED registers */ 321 val = pcnet_read_bcr (dev, 2) | 0x1000; 322 pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ 323 pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ 324 pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ 325 pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ 326 pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ 327 #endif 328 329 /* Set/reset autoselect bit */ 330 val = pcnet_read_bcr (dev, 2) & ~2; 331 val |= 2; 332 pcnet_write_bcr (dev, 2, val); 333 334 /* Enable auto negotiate, setup, disable fd */ 335 val = pcnet_read_bcr (dev, 32) & ~0x98; 336 val |= 0x20; 337 pcnet_write_bcr (dev, 32, val); 338 339 /* 340 * We only maintain one structure because the drivers will never 341 * be used concurrently. In 32bit mode the RX and TX ring entries 342 * must be aligned on 16-byte boundaries. 343 */ 344 if (lp == NULL) { 345 addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10); 346 addr = (addr + 0xf) & ~0xf; 347 lp = (pcnet_priv_t *) addr; 348 } 349 350 lp->init_block.mode = cpu_to_le16 (0x0000); 351 lp->init_block.filter[0] = 0x00000000; 352 lp->init_block.filter[1] = 0x00000000; 353 354 /* 355 * Initialize the Rx ring. 356 */ 357 lp->cur_rx = 0; 358 for (i = 0; i < RX_RING_SIZE; i++) { 359 lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]); 360 lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ); 361 lp->rx_ring[i].status = cpu_to_le16 (0x8000); 362 PCNET_DEBUG1 363 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, 364 lp->rx_ring[i].base, lp->rx_ring[i].buf_length, 365 lp->rx_ring[i].status); 366 } 367 368 /* 369 * Initialize the Tx ring. The Tx buffer address is filled in as 370 * needed, but we do need to clear the upper ownership bit. 371 */ 372 lp->cur_tx = 0; 373 for (i = 0; i < TX_RING_SIZE; i++) { 374 lp->tx_ring[i].base = 0; 375 lp->tx_ring[i].status = 0; 376 } 377 378 /* 379 * Setup Init Block. 380 */ 381 PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block); 382 383 for (i = 0; i < 6; i++) { 384 lp->init_block.phys_addr[i] = dev->enetaddr[i]; 385 PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]); 386 } 387 388 lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS | 389 RX_RING_LEN_BITS); 390 lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring); 391 lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring); 392 393 PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", 394 lp->init_block.tlen_rlen, 395 lp->init_block.rx_ring, lp->init_block.tx_ring); 396 397 /* 398 * Tell the controller where the Init Block is located. 399 */ 400 addr = PCI_TO_MEM (dev, &lp->init_block); 401 pcnet_write_csr (dev, 1, addr & 0xffff); 402 pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff); 403 404 pcnet_write_csr (dev, 4, 0x0915); 405 pcnet_write_csr (dev, 0, 0x0001); /* start */ 406 407 /* Wait for Init Done bit */ 408 for (i = 10000; i > 0; i--) { 409 if (pcnet_read_csr (dev, 0) & 0x0100) 410 break; 411 udelay (10); 412 } 413 if (i <= 0) { 414 printf ("%s: TIMEOUT: controller init failed\n", dev->name); 415 pcnet_reset (dev); 416 return -1; 417 } 418 419 /* 420 * Finally start network controller operation. 421 */ 422 pcnet_write_csr (dev, 0, 0x0002); 423 424 return 0; 425 } 426 427 static int pcnet_send (struct eth_device *dev, volatile void *packet, 428 int pkt_len) 429 { 430 int i, status; 431 struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; 432 433 PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, 434 packet); 435 436 /* Wait for completion by testing the OWN bit */ 437 for (i = 1000; i > 0; i--) { 438 status = le16_to_cpu (entry->status); 439 if ((status & 0x8000) == 0) 440 break; 441 udelay (100); 442 PCNET_DEBUG2 ("."); 443 } 444 if (i <= 0) { 445 printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", 446 dev->name, lp->cur_tx, status); 447 pkt_len = 0; 448 goto failure; 449 } 450 451 /* 452 * Setup Tx ring. Caution: the write order is important here, 453 * set the status with the "ownership" bits last. 454 */ 455 status = 0x8300; 456 entry->length = le16_to_cpu (-pkt_len); 457 entry->misc = 0x00000000; 458 entry->base = PCI_TO_MEM_LE (dev, packet); 459 entry->status = le16_to_cpu (status); 460 461 /* Trigger an immediate send poll. */ 462 pcnet_write_csr (dev, 0, 0x0008); 463 464 failure: 465 if (++lp->cur_tx >= TX_RING_SIZE) 466 lp->cur_tx = 0; 467 468 PCNET_DEBUG2 ("done\n"); 469 return pkt_len; 470 } 471 472 static int pcnet_recv (struct eth_device *dev) 473 { 474 struct pcnet_rx_head *entry; 475 int pkt_len = 0; 476 u16 status; 477 478 while (1) { 479 entry = &lp->rx_ring[lp->cur_rx]; 480 /* 481 * If we own the next entry, it's a new packet. Send it up. 482 */ 483 if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) { 484 break; 485 } 486 status >>= 8; 487 488 if (status != 0x03) { /* There was an error. */ 489 490 printf ("%s: Rx%d", dev->name, lp->cur_rx); 491 PCNET_DEBUG1 (" (status=0x%x)", status); 492 if (status & 0x20) 493 printf (" Frame"); 494 if (status & 0x10) 495 printf (" Overflow"); 496 if (status & 0x08) 497 printf (" CRC"); 498 if (status & 0x04) 499 printf (" Fifo"); 500 printf (" Error\n"); 501 entry->status &= le16_to_cpu (0x03ff); 502 503 } else { 504 505 pkt_len = 506 (le32_to_cpu (entry->msg_length) & 0xfff) - 4; 507 if (pkt_len < 60) { 508 printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); 509 } else { 510 NetReceive (lp->rx_buf[lp->cur_rx], pkt_len); 511 PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n", 512 lp->cur_rx, pkt_len, 513 lp->rx_buf[lp->cur_rx]); 514 } 515 } 516 entry->status |= cpu_to_le16 (0x8000); 517 518 if (++lp->cur_rx >= RX_RING_SIZE) 519 lp->cur_rx = 0; 520 } 521 return pkt_len; 522 } 523 524 static void pcnet_halt (struct eth_device *dev) 525 { 526 int i; 527 528 PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name); 529 530 /* Reset the PCnet controller */ 531 pcnet_reset (dev); 532 533 /* Wait for Stop bit */ 534 for (i = 1000; i > 0; i--) { 535 if (pcnet_read_csr (dev, 0) & 0x4) 536 break; 537 udelay (10); 538 } 539 if (i <= 0) { 540 printf ("%s: TIMEOUT: controller reset failed\n", dev->name); 541 } 542 } 543