1 /* 2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. 3 * 4 * This driver for AMD PCnet network controllers is derived from the 5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <malloc.h> 28 #include <net.h> 29 #include <asm/io.h> 30 #include <pci.h> 31 32 #if 0 33 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ 34 #endif 35 36 #if PCNET_DEBUG_LEVEL > 0 37 #define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args) 38 #if PCNET_DEBUG_LEVEL > 1 39 #define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args) 40 #else 41 #define PCNET_DEBUG2(fmt,args...) 42 #endif 43 #else 44 #define PCNET_DEBUG1(fmt,args...) 45 #define PCNET_DEBUG2(fmt,args...) 46 #endif 47 48 #if defined(CONFIG_CMD_NET) \ 49 && defined(CONFIG_NET_MULTI) && defined(CONFIG_PCNET) 50 51 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) 52 #error "Macro for PCnet chip version is not defined!" 53 #endif 54 55 /* 56 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 57 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 58 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 59 */ 60 #define PCNET_LOG_TX_BUFFERS 0 61 #define PCNET_LOG_RX_BUFFERS 2 62 63 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) 64 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) 65 66 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) 67 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) 68 69 #define PKT_BUF_SZ 1544 70 71 /* The PCNET Rx and Tx ring descriptors. */ 72 struct pcnet_rx_head { 73 u32 base; 74 s16 buf_length; 75 s16 status; 76 u32 msg_length; 77 u32 reserved; 78 }; 79 80 struct pcnet_tx_head { 81 u32 base; 82 s16 length; 83 s16 status; 84 u32 misc; 85 u32 reserved; 86 }; 87 88 /* The PCNET 32-Bit initialization block, described in databook. */ 89 struct pcnet_init_block { 90 u16 mode; 91 u16 tlen_rlen; 92 u8 phys_addr[6]; 93 u16 reserved; 94 u32 filter[2]; 95 /* Receive and transmit ring base, along with extra bits. */ 96 u32 rx_ring; 97 u32 tx_ring; 98 u32 reserved2; 99 }; 100 101 typedef struct pcnet_priv { 102 struct pcnet_rx_head rx_ring[RX_RING_SIZE]; 103 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; 104 struct pcnet_init_block init_block; 105 /* Receive Buffer space */ 106 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; 107 int cur_rx; 108 int cur_tx; 109 } pcnet_priv_t; 110 111 static pcnet_priv_t *lp; 112 113 /* Offsets from base I/O address for WIO mode */ 114 #define PCNET_RDP 0x10 115 #define PCNET_RAP 0x12 116 #define PCNET_RESET 0x14 117 #define PCNET_BDP 0x16 118 119 static u16 pcnet_read_csr (struct eth_device *dev, int index) 120 { 121 outw (index, dev->iobase + PCNET_RAP); 122 return inw (dev->iobase + PCNET_RDP); 123 } 124 125 static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) 126 { 127 outw (index, dev->iobase + PCNET_RAP); 128 outw (val, dev->iobase + PCNET_RDP); 129 } 130 131 static u16 pcnet_read_bcr (struct eth_device *dev, int index) 132 { 133 outw (index, dev->iobase + PCNET_RAP); 134 return inw (dev->iobase + PCNET_BDP); 135 } 136 137 static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) 138 { 139 outw (index, dev->iobase + PCNET_RAP); 140 outw (val, dev->iobase + PCNET_BDP); 141 } 142 143 static void pcnet_reset (struct eth_device *dev) 144 { 145 inw (dev->iobase + PCNET_RESET); 146 } 147 148 static int pcnet_check (struct eth_device *dev) 149 { 150 outw (88, dev->iobase + PCNET_RAP); 151 return (inw (dev->iobase + PCNET_RAP) == 88); 152 } 153 154 static int pcnet_init (struct eth_device *dev, bd_t * bis); 155 static int pcnet_send (struct eth_device *dev, volatile void *packet, 156 int length); 157 static int pcnet_recv (struct eth_device *dev); 158 static void pcnet_halt (struct eth_device *dev); 159 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); 160 161 #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a)) 162 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) 163 164 static struct pci_device_id supported[] = { 165 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, 166 {} 167 }; 168 169 170 int pcnet_initialize (bd_t * bis) 171 { 172 pci_dev_t devbusfn; 173 struct eth_device *dev; 174 u16 command, status; 175 int dev_nr = 0; 176 177 PCNET_DEBUG1 ("\npcnet_initialize...\n"); 178 179 for (dev_nr = 0;; dev_nr++) { 180 181 /* 182 * Find the PCnet PCI device(s). 183 */ 184 if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) { 185 break; 186 } 187 188 /* 189 * Allocate and pre-fill the device structure. 190 */ 191 dev = (struct eth_device *) malloc (sizeof *dev); 192 dev->priv = (void *) devbusfn; 193 sprintf (dev->name, "pcnet#%d", dev_nr); 194 195 /* 196 * Setup the PCI device. 197 */ 198 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, 199 (unsigned int *) &dev->iobase); 200 dev->iobase=pci_io_to_phys (devbusfn, dev->iobase); 201 dev->iobase &= ~0xf; 202 203 PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ", 204 dev->name, devbusfn, dev->iobase); 205 206 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; 207 pci_write_config_word (devbusfn, PCI_COMMAND, command); 208 pci_read_config_word (devbusfn, PCI_COMMAND, &status); 209 if ((status & command) != command) { 210 printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name); 211 free (dev); 212 continue; 213 } 214 215 pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40); 216 217 /* 218 * Probe the PCnet chip. 219 */ 220 if (pcnet_probe (dev, bis, dev_nr) < 0) { 221 free (dev); 222 continue; 223 } 224 225 /* 226 * Setup device structure and register the driver. 227 */ 228 dev->init = pcnet_init; 229 dev->halt = pcnet_halt; 230 dev->send = pcnet_send; 231 dev->recv = pcnet_recv; 232 233 eth_register (dev); 234 } 235 236 udelay (10 * 1000); 237 238 return dev_nr; 239 } 240 241 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) 242 { 243 int chip_version; 244 char *chipname; 245 246 #ifdef PCNET_HAS_PROM 247 int i; 248 #endif 249 250 /* Reset the PCnet controller */ 251 pcnet_reset (dev); 252 253 /* Check if register access is working */ 254 if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) { 255 printf ("%s: CSR register access check failed\n", dev->name); 256 return -1; 257 } 258 259 /* Identify the chip */ 260 chip_version = 261 pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16); 262 if ((chip_version & 0xfff) != 0x003) 263 return -1; 264 chip_version = (chip_version >> 12) & 0xffff; 265 switch (chip_version) { 266 case 0x2621: 267 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 268 break; 269 #ifdef CONFIG_PCNET_79C973 270 case 0x2625: 271 chipname = "PCnet/FAST III 79C973"; /* PCI */ 272 break; 273 #endif 274 #ifdef CONFIG_PCNET_79C975 275 case 0x2627: 276 chipname = "PCnet/FAST III 79C975"; /* PCI */ 277 break; 278 #endif 279 default: 280 printf ("%s: PCnet version %#x not supported\n", 281 dev->name, chip_version); 282 return -1; 283 } 284 285 PCNET_DEBUG1 ("AMD %s\n", chipname); 286 287 #ifdef PCNET_HAS_PROM 288 /* 289 * In most chips, after a chip reset, the ethernet address is read from 290 * the station address PROM at the base address and programmed into the 291 * "Physical Address Registers" CSR12-14. 292 */ 293 for (i = 0; i < 3; i++) { 294 unsigned int val; 295 296 val = pcnet_read_csr (dev, i + 12) & 0x0ffff; 297 /* There may be endianness issues here. */ 298 dev->enetaddr[2 * i] = val & 0x0ff; 299 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; 300 } 301 #endif /* PCNET_HAS_PROM */ 302 303 return 0; 304 } 305 306 static int pcnet_init (struct eth_device *dev, bd_t * bis) 307 { 308 int i, val; 309 u32 addr; 310 311 PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name); 312 313 /* Switch pcnet to 32bit mode */ 314 pcnet_write_bcr (dev, 20, 2); 315 316 #ifdef CONFIG_PN62 317 /* Setup LED registers */ 318 val = pcnet_read_bcr (dev, 2) | 0x1000; 319 pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ 320 pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ 321 pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ 322 pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ 323 pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ 324 #endif 325 326 /* Set/reset autoselect bit */ 327 val = pcnet_read_bcr (dev, 2) & ~2; 328 val |= 2; 329 pcnet_write_bcr (dev, 2, val); 330 331 /* Enable auto negotiate, setup, disable fd */ 332 val = pcnet_read_bcr (dev, 32) & ~0x98; 333 val |= 0x20; 334 pcnet_write_bcr (dev, 32, val); 335 336 /* 337 * We only maintain one structure because the drivers will never 338 * be used concurrently. In 32bit mode the RX and TX ring entries 339 * must be aligned on 16-byte boundaries. 340 */ 341 if (lp == NULL) { 342 addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10); 343 addr = (addr + 0xf) & ~0xf; 344 lp = (pcnet_priv_t *) addr; 345 } 346 347 lp->init_block.mode = cpu_to_le16 (0x0000); 348 lp->init_block.filter[0] = 0x00000000; 349 lp->init_block.filter[1] = 0x00000000; 350 351 /* 352 * Initialize the Rx ring. 353 */ 354 lp->cur_rx = 0; 355 for (i = 0; i < RX_RING_SIZE; i++) { 356 lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]); 357 lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ); 358 lp->rx_ring[i].status = cpu_to_le16 (0x8000); 359 PCNET_DEBUG1 360 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, 361 lp->rx_ring[i].base, lp->rx_ring[i].buf_length, 362 lp->rx_ring[i].status); 363 } 364 365 /* 366 * Initialize the Tx ring. The Tx buffer address is filled in as 367 * needed, but we do need to clear the upper ownership bit. 368 */ 369 lp->cur_tx = 0; 370 for (i = 0; i < TX_RING_SIZE; i++) { 371 lp->tx_ring[i].base = 0; 372 lp->tx_ring[i].status = 0; 373 } 374 375 /* 376 * Setup Init Block. 377 */ 378 PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block); 379 380 for (i = 0; i < 6; i++) { 381 lp->init_block.phys_addr[i] = dev->enetaddr[i]; 382 PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]); 383 } 384 385 lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS | 386 RX_RING_LEN_BITS); 387 lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring); 388 lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring); 389 390 PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", 391 lp->init_block.tlen_rlen, 392 lp->init_block.rx_ring, lp->init_block.tx_ring); 393 394 /* 395 * Tell the controller where the Init Block is located. 396 */ 397 addr = PCI_TO_MEM (dev, &lp->init_block); 398 pcnet_write_csr (dev, 1, addr & 0xffff); 399 pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff); 400 401 pcnet_write_csr (dev, 4, 0x0915); 402 pcnet_write_csr (dev, 0, 0x0001); /* start */ 403 404 /* Wait for Init Done bit */ 405 for (i = 10000; i > 0; i--) { 406 if (pcnet_read_csr (dev, 0) & 0x0100) 407 break; 408 udelay (10); 409 } 410 if (i <= 0) { 411 printf ("%s: TIMEOUT: controller init failed\n", dev->name); 412 pcnet_reset (dev); 413 return -1; 414 } 415 416 /* 417 * Finally start network controller operation. 418 */ 419 pcnet_write_csr (dev, 0, 0x0002); 420 421 return 0; 422 } 423 424 static int pcnet_send (struct eth_device *dev, volatile void *packet, 425 int pkt_len) 426 { 427 int i, status; 428 struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; 429 430 PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, 431 packet); 432 433 /* Wait for completion by testing the OWN bit */ 434 for (i = 1000; i > 0; i--) { 435 status = le16_to_cpu (entry->status); 436 if ((status & 0x8000) == 0) 437 break; 438 udelay (100); 439 PCNET_DEBUG2 ("."); 440 } 441 if (i <= 0) { 442 printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", 443 dev->name, lp->cur_tx, status); 444 pkt_len = 0; 445 goto failure; 446 } 447 448 /* 449 * Setup Tx ring. Caution: the write order is important here, 450 * set the status with the "ownership" bits last. 451 */ 452 status = 0x8300; 453 entry->length = le16_to_cpu (-pkt_len); 454 entry->misc = 0x00000000; 455 entry->base = PCI_TO_MEM_LE (dev, packet); 456 entry->status = le16_to_cpu (status); 457 458 /* Trigger an immediate send poll. */ 459 pcnet_write_csr (dev, 0, 0x0008); 460 461 failure: 462 if (++lp->cur_tx >= TX_RING_SIZE) 463 lp->cur_tx = 0; 464 465 PCNET_DEBUG2 ("done\n"); 466 return pkt_len; 467 } 468 469 static int pcnet_recv (struct eth_device *dev) 470 { 471 struct pcnet_rx_head *entry; 472 int pkt_len = 0; 473 u16 status; 474 475 while (1) { 476 entry = &lp->rx_ring[lp->cur_rx]; 477 /* 478 * If we own the next entry, it's a new packet. Send it up. 479 */ 480 if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) { 481 break; 482 } 483 status >>= 8; 484 485 if (status != 0x03) { /* There was an error. */ 486 487 printf ("%s: Rx%d", dev->name, lp->cur_rx); 488 PCNET_DEBUG1 (" (status=0x%x)", status); 489 if (status & 0x20) 490 printf (" Frame"); 491 if (status & 0x10) 492 printf (" Overflow"); 493 if (status & 0x08) 494 printf (" CRC"); 495 if (status & 0x04) 496 printf (" Fifo"); 497 printf (" Error\n"); 498 entry->status &= le16_to_cpu (0x03ff); 499 500 } else { 501 502 pkt_len = 503 (le32_to_cpu (entry->msg_length) & 0xfff) - 4; 504 if (pkt_len < 60) { 505 printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); 506 } else { 507 NetReceive (lp->rx_buf[lp->cur_rx], pkt_len); 508 PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n", 509 lp->cur_rx, pkt_len, 510 lp->rx_buf[lp->cur_rx]); 511 } 512 } 513 entry->status |= cpu_to_le16 (0x8000); 514 515 if (++lp->cur_rx >= RX_RING_SIZE) 516 lp->cur_rx = 0; 517 } 518 return pkt_len; 519 } 520 521 static void pcnet_halt (struct eth_device *dev) 522 { 523 int i; 524 525 PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name); 526 527 /* Reset the PCnet controller */ 528 pcnet_reset (dev); 529 530 /* Wait for Stop bit */ 531 for (i = 1000; i > 0; i--) { 532 if (pcnet_read_csr (dev, 0) & 0x4) 533 break; 534 udelay (10); 535 } 536 if (i <= 0) { 537 printf ("%s: TIMEOUT: controller reset failed\n", dev->name); 538 } 539 } 540 #endif 541