1 /* 2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. 3 * 4 * This driver for AMD PCnet network controllers is derived from the 5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <malloc.h> 12 #include <net.h> 13 #include <netdev.h> 14 #include <asm/io.h> 15 #include <pci.h> 16 17 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ 18 19 #define PCNET_DEBUG1(fmt,args...) \ 20 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args) 21 #define PCNET_DEBUG2(fmt,args...) \ 22 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args) 23 24 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) 25 #error "Macro for PCnet chip version is not defined!" 26 #endif 27 28 /* 29 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 30 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 31 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 32 */ 33 #define PCNET_LOG_TX_BUFFERS 0 34 #define PCNET_LOG_RX_BUFFERS 2 35 36 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) 37 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) 38 39 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) 40 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) 41 42 #define PKT_BUF_SZ 1544 43 44 /* The PCNET Rx and Tx ring descriptors. */ 45 struct pcnet_rx_head { 46 u32 base; 47 s16 buf_length; 48 s16 status; 49 u32 msg_length; 50 u32 reserved; 51 }; 52 53 struct pcnet_tx_head { 54 u32 base; 55 s16 length; 56 s16 status; 57 u32 misc; 58 u32 reserved; 59 }; 60 61 /* The PCNET 32-Bit initialization block, described in databook. */ 62 struct pcnet_init_block { 63 u16 mode; 64 u16 tlen_rlen; 65 u8 phys_addr[6]; 66 u16 reserved; 67 u32 filter[2]; 68 /* Receive and transmit ring base, along with extra bits. */ 69 u32 rx_ring; 70 u32 tx_ring; 71 u32 reserved2; 72 }; 73 74 struct pcnet_uncached_priv { 75 struct pcnet_rx_head rx_ring[RX_RING_SIZE]; 76 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; 77 struct pcnet_init_block init_block; 78 }; 79 80 typedef struct pcnet_priv { 81 struct pcnet_uncached_priv *uc; 82 /* Receive Buffer space */ 83 unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4]; 84 int cur_rx; 85 int cur_tx; 86 } pcnet_priv_t; 87 88 static pcnet_priv_t *lp; 89 90 /* Offsets from base I/O address for WIO mode */ 91 #define PCNET_RDP 0x10 92 #define PCNET_RAP 0x12 93 #define PCNET_RESET 0x14 94 #define PCNET_BDP 0x16 95 96 static u16 pcnet_read_csr(struct eth_device *dev, int index) 97 { 98 outw(index, dev->iobase + PCNET_RAP); 99 return inw(dev->iobase + PCNET_RDP); 100 } 101 102 static void pcnet_write_csr(struct eth_device *dev, int index, u16 val) 103 { 104 outw(index, dev->iobase + PCNET_RAP); 105 outw(val, dev->iobase + PCNET_RDP); 106 } 107 108 static u16 pcnet_read_bcr(struct eth_device *dev, int index) 109 { 110 outw(index, dev->iobase + PCNET_RAP); 111 return inw(dev->iobase + PCNET_BDP); 112 } 113 114 static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val) 115 { 116 outw(index, dev->iobase + PCNET_RAP); 117 outw(val, dev->iobase + PCNET_BDP); 118 } 119 120 static void pcnet_reset(struct eth_device *dev) 121 { 122 inw(dev->iobase + PCNET_RESET); 123 } 124 125 static int pcnet_check(struct eth_device *dev) 126 { 127 outw(88, dev->iobase + PCNET_RAP); 128 return inw(dev->iobase + PCNET_RAP) == 88; 129 } 130 131 static int pcnet_init (struct eth_device *dev, bd_t * bis); 132 static int pcnet_send(struct eth_device *dev, void *packet, int length); 133 static int pcnet_recv (struct eth_device *dev); 134 static void pcnet_halt (struct eth_device *dev); 135 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); 136 137 static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev, 138 void *addr) 139 { 140 pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv; 141 void *virt_addr = addr; 142 143 return pci_virt_to_mem(devbusfn, virt_addr); 144 } 145 146 static struct pci_device_id supported[] = { 147 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, 148 {} 149 }; 150 151 152 int pcnet_initialize(bd_t *bis) 153 { 154 pci_dev_t devbusfn; 155 struct eth_device *dev; 156 u16 command, status; 157 int dev_nr = 0; 158 u32 bar; 159 160 PCNET_DEBUG1("\npcnet_initialize...\n"); 161 162 for (dev_nr = 0;; dev_nr++) { 163 164 /* 165 * Find the PCnet PCI device(s). 166 */ 167 devbusfn = pci_find_devices(supported, dev_nr); 168 if (devbusfn < 0) 169 break; 170 171 /* 172 * Allocate and pre-fill the device structure. 173 */ 174 dev = (struct eth_device *)malloc(sizeof(*dev)); 175 if (!dev) { 176 printf("pcnet: Can not allocate memory\n"); 177 break; 178 } 179 memset(dev, 0, sizeof(*dev)); 180 dev->priv = (void *)(unsigned long)devbusfn; 181 sprintf(dev->name, "pcnet#%d", dev_nr); 182 183 /* 184 * Setup the PCI device. 185 */ 186 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &bar); 187 dev->iobase = pci_io_to_phys(devbusfn, bar); 188 dev->iobase &= ~0xf; 189 190 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ", 191 dev->name, devbusfn, (unsigned long)dev->iobase); 192 193 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; 194 pci_write_config_word(devbusfn, PCI_COMMAND, command); 195 pci_read_config_word(devbusfn, PCI_COMMAND, &status); 196 if ((status & command) != command) { 197 printf("%s: Couldn't enable IO access or Bus Mastering\n", 198 dev->name); 199 free(dev); 200 continue; 201 } 202 203 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40); 204 205 /* 206 * Probe the PCnet chip. 207 */ 208 if (pcnet_probe(dev, bis, dev_nr) < 0) { 209 free(dev); 210 continue; 211 } 212 213 /* 214 * Setup device structure and register the driver. 215 */ 216 dev->init = pcnet_init; 217 dev->halt = pcnet_halt; 218 dev->send = pcnet_send; 219 dev->recv = pcnet_recv; 220 221 eth_register(dev); 222 } 223 224 udelay(10 * 1000); 225 226 return dev_nr; 227 } 228 229 static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr) 230 { 231 int chip_version; 232 char *chipname; 233 234 #ifdef PCNET_HAS_PROM 235 int i; 236 #endif 237 238 /* Reset the PCnet controller */ 239 pcnet_reset(dev); 240 241 /* Check if register access is working */ 242 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) { 243 printf("%s: CSR register access check failed\n", dev->name); 244 return -1; 245 } 246 247 /* Identify the chip */ 248 chip_version = 249 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16); 250 if ((chip_version & 0xfff) != 0x003) 251 return -1; 252 chip_version = (chip_version >> 12) & 0xffff; 253 switch (chip_version) { 254 case 0x2621: 255 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 256 break; 257 #ifdef CONFIG_PCNET_79C973 258 case 0x2625: 259 chipname = "PCnet/FAST III 79C973"; /* PCI */ 260 break; 261 #endif 262 #ifdef CONFIG_PCNET_79C975 263 case 0x2627: 264 chipname = "PCnet/FAST III 79C975"; /* PCI */ 265 break; 266 #endif 267 default: 268 printf("%s: PCnet version %#x not supported\n", 269 dev->name, chip_version); 270 return -1; 271 } 272 273 PCNET_DEBUG1("AMD %s\n", chipname); 274 275 #ifdef PCNET_HAS_PROM 276 /* 277 * In most chips, after a chip reset, the ethernet address is read from 278 * the station address PROM at the base address and programmed into the 279 * "Physical Address Registers" CSR12-14. 280 */ 281 for (i = 0; i < 3; i++) { 282 unsigned int val; 283 284 val = pcnet_read_csr(dev, i + 12) & 0x0ffff; 285 /* There may be endianness issues here. */ 286 dev->enetaddr[2 * i] = val & 0x0ff; 287 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; 288 } 289 #endif /* PCNET_HAS_PROM */ 290 291 return 0; 292 } 293 294 static int pcnet_init(struct eth_device *dev, bd_t *bis) 295 { 296 struct pcnet_uncached_priv *uc; 297 int i, val; 298 unsigned long addr; 299 300 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name); 301 302 /* Switch pcnet to 32bit mode */ 303 pcnet_write_bcr(dev, 20, 2); 304 305 /* Set/reset autoselect bit */ 306 val = pcnet_read_bcr(dev, 2) & ~2; 307 val |= 2; 308 pcnet_write_bcr(dev, 2, val); 309 310 /* Enable auto negotiate, setup, disable fd */ 311 val = pcnet_read_bcr(dev, 32) & ~0x98; 312 val |= 0x20; 313 pcnet_write_bcr(dev, 32, val); 314 315 /* 316 * Enable NOUFLO on supported controllers, with the transmit 317 * start point set to the full packet. This will cause entire 318 * packets to be buffered by the ethernet controller before 319 * transmission, eliminating underflows which are common on 320 * slower devices. Controllers which do not support NOUFLO will 321 * simply be left with a larger transmit FIFO threshold. 322 */ 323 val = pcnet_read_bcr(dev, 18); 324 val |= 1 << 11; 325 pcnet_write_bcr(dev, 18, val); 326 val = pcnet_read_csr(dev, 80); 327 val |= 0x3 << 10; 328 pcnet_write_csr(dev, 80, val); 329 330 /* 331 * We only maintain one structure because the drivers will never 332 * be used concurrently. In 32bit mode the RX and TX ring entries 333 * must be aligned on 16-byte boundaries. 334 */ 335 if (lp == NULL) { 336 addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10); 337 addr = (addr + 0xf) & ~0xf; 338 lp = (pcnet_priv_t *)addr; 339 340 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN, 341 sizeof(*lp->uc)); 342 flush_dcache_range(addr, addr + sizeof(*lp->uc)); 343 addr = UNCACHED_SDRAM(addr); 344 lp->uc = (struct pcnet_uncached_priv *)addr; 345 346 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN, 347 sizeof(*lp->rx_buf)); 348 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf)); 349 lp->rx_buf = (void *)addr; 350 } 351 352 uc = lp->uc; 353 354 uc->init_block.mode = cpu_to_le16(0x0000); 355 uc->init_block.filter[0] = 0x00000000; 356 uc->init_block.filter[1] = 0x00000000; 357 358 /* 359 * Initialize the Rx ring. 360 */ 361 lp->cur_rx = 0; 362 for (i = 0; i < RX_RING_SIZE; i++) { 363 addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]); 364 uc->rx_ring[i].base = cpu_to_le32(addr); 365 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ); 366 uc->rx_ring[i].status = cpu_to_le16(0x8000); 367 PCNET_DEBUG1 368 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, 369 uc->rx_ring[i].base, uc->rx_ring[i].buf_length, 370 uc->rx_ring[i].status); 371 } 372 373 /* 374 * Initialize the Tx ring. The Tx buffer address is filled in as 375 * needed, but we do need to clear the upper ownership bit. 376 */ 377 lp->cur_tx = 0; 378 for (i = 0; i < TX_RING_SIZE; i++) { 379 uc->tx_ring[i].base = 0; 380 uc->tx_ring[i].status = 0; 381 } 382 383 /* 384 * Setup Init Block. 385 */ 386 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block); 387 388 for (i = 0; i < 6; i++) { 389 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i]; 390 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]); 391 } 392 393 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS | 394 RX_RING_LEN_BITS); 395 addr = pcnet_virt_to_mem(dev, uc->rx_ring); 396 uc->init_block.rx_ring = cpu_to_le32(addr); 397 addr = pcnet_virt_to_mem(dev, uc->tx_ring); 398 uc->init_block.tx_ring = cpu_to_le32(addr); 399 400 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", 401 uc->init_block.tlen_rlen, 402 uc->init_block.rx_ring, uc->init_block.tx_ring); 403 404 /* 405 * Tell the controller where the Init Block is located. 406 */ 407 barrier(); 408 addr = pcnet_virt_to_mem(dev, &lp->uc->init_block); 409 pcnet_write_csr(dev, 1, addr & 0xffff); 410 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff); 411 412 pcnet_write_csr(dev, 4, 0x0915); 413 pcnet_write_csr(dev, 0, 0x0001); /* start */ 414 415 /* Wait for Init Done bit */ 416 for (i = 10000; i > 0; i--) { 417 if (pcnet_read_csr(dev, 0) & 0x0100) 418 break; 419 udelay(10); 420 } 421 if (i <= 0) { 422 printf("%s: TIMEOUT: controller init failed\n", dev->name); 423 pcnet_reset(dev); 424 return -1; 425 } 426 427 /* 428 * Finally start network controller operation. 429 */ 430 pcnet_write_csr(dev, 0, 0x0002); 431 432 return 0; 433 } 434 435 static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len) 436 { 437 int i, status; 438 u32 addr; 439 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx]; 440 441 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, 442 packet); 443 444 flush_dcache_range((unsigned long)packet, 445 (unsigned long)packet + pkt_len); 446 447 /* Wait for completion by testing the OWN bit */ 448 for (i = 1000; i > 0; i--) { 449 status = readw(&entry->status); 450 if ((status & 0x8000) == 0) 451 break; 452 udelay(100); 453 PCNET_DEBUG2("."); 454 } 455 if (i <= 0) { 456 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", 457 dev->name, lp->cur_tx, status); 458 pkt_len = 0; 459 goto failure; 460 } 461 462 /* 463 * Setup Tx ring. Caution: the write order is important here, 464 * set the status with the "ownership" bits last. 465 */ 466 addr = pcnet_virt_to_mem(dev, packet); 467 writew(-pkt_len, &entry->length); 468 writel(0, &entry->misc); 469 writel(addr, &entry->base); 470 writew(0x8300, &entry->status); 471 472 /* Trigger an immediate send poll. */ 473 pcnet_write_csr(dev, 0, 0x0008); 474 475 failure: 476 if (++lp->cur_tx >= TX_RING_SIZE) 477 lp->cur_tx = 0; 478 479 PCNET_DEBUG2("done\n"); 480 return pkt_len; 481 } 482 483 static int pcnet_recv (struct eth_device *dev) 484 { 485 struct pcnet_rx_head *entry; 486 unsigned char *buf; 487 int pkt_len = 0; 488 u16 status, err_status; 489 490 while (1) { 491 entry = &lp->uc->rx_ring[lp->cur_rx]; 492 /* 493 * If we own the next entry, it's a new packet. Send it up. 494 */ 495 status = readw(&entry->status); 496 if ((status & 0x8000) != 0) 497 break; 498 err_status = status >> 8; 499 500 if (err_status != 0x03) { /* There was an error. */ 501 printf("%s: Rx%d", dev->name, lp->cur_rx); 502 PCNET_DEBUG1(" (status=0x%x)", err_status); 503 if (err_status & 0x20) 504 printf(" Frame"); 505 if (err_status & 0x10) 506 printf(" Overflow"); 507 if (err_status & 0x08) 508 printf(" CRC"); 509 if (err_status & 0x04) 510 printf(" Fifo"); 511 printf(" Error\n"); 512 status &= 0x03ff; 513 514 } else { 515 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4; 516 if (pkt_len < 60) { 517 printf("%s: Rx%d: invalid packet length %d\n", 518 dev->name, lp->cur_rx, pkt_len); 519 } else { 520 buf = (*lp->rx_buf)[lp->cur_rx]; 521 invalidate_dcache_range((unsigned long)buf, 522 (unsigned long)buf + pkt_len); 523 net_process_received_packet(buf, pkt_len); 524 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n", 525 lp->cur_rx, pkt_len, buf); 526 } 527 } 528 529 status |= 0x8000; 530 writew(status, &entry->status); 531 532 if (++lp->cur_rx >= RX_RING_SIZE) 533 lp->cur_rx = 0; 534 } 535 return pkt_len; 536 } 537 538 static void pcnet_halt(struct eth_device *dev) 539 { 540 int i; 541 542 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name); 543 544 /* Reset the PCnet controller */ 545 pcnet_reset(dev); 546 547 /* Wait for Stop bit */ 548 for (i = 1000; i > 0; i--) { 549 if (pcnet_read_csr(dev, 0) & 0x4) 550 break; 551 udelay(10); 552 } 553 if (i <= 0) 554 printf("%s: TIMEOUT: controller reset failed\n", dev->name); 555 } 556