1 /* 2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. 3 * 4 * This driver for AMD PCnet network controllers is derived from the 5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <malloc.h> 28 #include <net.h> 29 #include <netdev.h> 30 #include <asm/io.h> 31 #include <pci.h> 32 33 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ 34 35 #define PCNET_DEBUG1(fmt,args...) \ 36 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args) 37 #define PCNET_DEBUG2(fmt,args...) \ 38 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args) 39 40 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) 41 #error "Macro for PCnet chip version is not defined!" 42 #endif 43 44 /* 45 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 46 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 47 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 48 */ 49 #define PCNET_LOG_TX_BUFFERS 0 50 #define PCNET_LOG_RX_BUFFERS 2 51 52 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) 53 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) 54 55 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) 56 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) 57 58 #define PKT_BUF_SZ 1544 59 60 /* The PCNET Rx and Tx ring descriptors. */ 61 struct pcnet_rx_head { 62 u32 base; 63 s16 buf_length; 64 s16 status; 65 u32 msg_length; 66 u32 reserved; 67 }; 68 69 struct pcnet_tx_head { 70 u32 base; 71 s16 length; 72 s16 status; 73 u32 misc; 74 u32 reserved; 75 }; 76 77 /* The PCNET 32-Bit initialization block, described in databook. */ 78 struct pcnet_init_block { 79 u16 mode; 80 u16 tlen_rlen; 81 u8 phys_addr[6]; 82 u16 reserved; 83 u32 filter[2]; 84 /* Receive and transmit ring base, along with extra bits. */ 85 u32 rx_ring; 86 u32 tx_ring; 87 u32 reserved2; 88 }; 89 90 typedef struct pcnet_priv { 91 struct pcnet_rx_head rx_ring[RX_RING_SIZE]; 92 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; 93 struct pcnet_init_block init_block; 94 /* Receive Buffer space */ 95 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; 96 int cur_rx; 97 int cur_tx; 98 } pcnet_priv_t; 99 100 static pcnet_priv_t *lp; 101 102 /* Offsets from base I/O address for WIO mode */ 103 #define PCNET_RDP 0x10 104 #define PCNET_RAP 0x12 105 #define PCNET_RESET 0x14 106 #define PCNET_BDP 0x16 107 108 static u16 pcnet_read_csr (struct eth_device *dev, int index) 109 { 110 outw (index, dev->iobase + PCNET_RAP); 111 return inw (dev->iobase + PCNET_RDP); 112 } 113 114 static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) 115 { 116 outw (index, dev->iobase + PCNET_RAP); 117 outw (val, dev->iobase + PCNET_RDP); 118 } 119 120 static u16 pcnet_read_bcr (struct eth_device *dev, int index) 121 { 122 outw (index, dev->iobase + PCNET_RAP); 123 return inw (dev->iobase + PCNET_BDP); 124 } 125 126 static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) 127 { 128 outw (index, dev->iobase + PCNET_RAP); 129 outw (val, dev->iobase + PCNET_BDP); 130 } 131 132 static void pcnet_reset (struct eth_device *dev) 133 { 134 inw (dev->iobase + PCNET_RESET); 135 } 136 137 static int pcnet_check (struct eth_device *dev) 138 { 139 outw (88, dev->iobase + PCNET_RAP); 140 return (inw (dev->iobase + PCNET_RAP) == 88); 141 } 142 143 static int pcnet_init (struct eth_device *dev, bd_t * bis); 144 static int pcnet_send (struct eth_device *dev, volatile void *packet, 145 int length); 146 static int pcnet_recv (struct eth_device *dev); 147 static void pcnet_halt (struct eth_device *dev); 148 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); 149 150 #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a)) 151 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) 152 153 static struct pci_device_id supported[] = { 154 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, 155 {} 156 }; 157 158 159 int pcnet_initialize (bd_t * bis) 160 { 161 pci_dev_t devbusfn; 162 struct eth_device *dev; 163 u16 command, status; 164 int dev_nr = 0; 165 166 PCNET_DEBUG1 ("\npcnet_initialize...\n"); 167 168 for (dev_nr = 0;; dev_nr++) { 169 170 /* 171 * Find the PCnet PCI device(s). 172 */ 173 if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) { 174 break; 175 } 176 177 /* 178 * Allocate and pre-fill the device structure. 179 */ 180 dev = (struct eth_device *) malloc (sizeof *dev); 181 if (!dev) { 182 printf("pcnet: Can not allocate memory\n"); 183 break; 184 } 185 memset(dev, 0, sizeof(*dev)); 186 dev->priv = (void *) devbusfn; 187 sprintf (dev->name, "pcnet#%d", dev_nr); 188 189 /* 190 * Setup the PCI device. 191 */ 192 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, 193 (unsigned int *) &dev->iobase); 194 dev->iobase=pci_io_to_phys (devbusfn, dev->iobase); 195 dev->iobase &= ~0xf; 196 197 PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ", 198 dev->name, devbusfn, dev->iobase); 199 200 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; 201 pci_write_config_word (devbusfn, PCI_COMMAND, command); 202 pci_read_config_word (devbusfn, PCI_COMMAND, &status); 203 if ((status & command) != command) { 204 printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name); 205 free (dev); 206 continue; 207 } 208 209 pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40); 210 211 /* 212 * Probe the PCnet chip. 213 */ 214 if (pcnet_probe (dev, bis, dev_nr) < 0) { 215 free (dev); 216 continue; 217 } 218 219 /* 220 * Setup device structure and register the driver. 221 */ 222 dev->init = pcnet_init; 223 dev->halt = pcnet_halt; 224 dev->send = pcnet_send; 225 dev->recv = pcnet_recv; 226 227 eth_register (dev); 228 } 229 230 udelay (10 * 1000); 231 232 return dev_nr; 233 } 234 235 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) 236 { 237 int chip_version; 238 char *chipname; 239 240 #ifdef PCNET_HAS_PROM 241 int i; 242 #endif 243 244 /* Reset the PCnet controller */ 245 pcnet_reset (dev); 246 247 /* Check if register access is working */ 248 if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) { 249 printf ("%s: CSR register access check failed\n", dev->name); 250 return -1; 251 } 252 253 /* Identify the chip */ 254 chip_version = 255 pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16); 256 if ((chip_version & 0xfff) != 0x003) 257 return -1; 258 chip_version = (chip_version >> 12) & 0xffff; 259 switch (chip_version) { 260 case 0x2621: 261 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 262 break; 263 #ifdef CONFIG_PCNET_79C973 264 case 0x2625: 265 chipname = "PCnet/FAST III 79C973"; /* PCI */ 266 break; 267 #endif 268 #ifdef CONFIG_PCNET_79C975 269 case 0x2627: 270 chipname = "PCnet/FAST III 79C975"; /* PCI */ 271 break; 272 #endif 273 default: 274 printf ("%s: PCnet version %#x not supported\n", 275 dev->name, chip_version); 276 return -1; 277 } 278 279 PCNET_DEBUG1 ("AMD %s\n", chipname); 280 281 #ifdef PCNET_HAS_PROM 282 /* 283 * In most chips, after a chip reset, the ethernet address is read from 284 * the station address PROM at the base address and programmed into the 285 * "Physical Address Registers" CSR12-14. 286 */ 287 for (i = 0; i < 3; i++) { 288 unsigned int val; 289 290 val = pcnet_read_csr (dev, i + 12) & 0x0ffff; 291 /* There may be endianness issues here. */ 292 dev->enetaddr[2 * i] = val & 0x0ff; 293 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; 294 } 295 #endif /* PCNET_HAS_PROM */ 296 297 return 0; 298 } 299 300 static int pcnet_init (struct eth_device *dev, bd_t * bis) 301 { 302 int i, val; 303 u32 addr; 304 305 PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name); 306 307 /* Switch pcnet to 32bit mode */ 308 pcnet_write_bcr (dev, 20, 2); 309 310 #ifdef CONFIG_PN62 311 /* Setup LED registers */ 312 val = pcnet_read_bcr (dev, 2) | 0x1000; 313 pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ 314 pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ 315 pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ 316 pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ 317 pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ 318 #endif 319 320 /* Set/reset autoselect bit */ 321 val = pcnet_read_bcr (dev, 2) & ~2; 322 val |= 2; 323 pcnet_write_bcr (dev, 2, val); 324 325 /* Enable auto negotiate, setup, disable fd */ 326 val = pcnet_read_bcr (dev, 32) & ~0x98; 327 val |= 0x20; 328 pcnet_write_bcr (dev, 32, val); 329 330 /* 331 * We only maintain one structure because the drivers will never 332 * be used concurrently. In 32bit mode the RX and TX ring entries 333 * must be aligned on 16-byte boundaries. 334 */ 335 if (lp == NULL) { 336 addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10); 337 addr = (addr + 0xf) & ~0xf; 338 lp = (pcnet_priv_t *) addr; 339 } 340 341 lp->init_block.mode = cpu_to_le16 (0x0000); 342 lp->init_block.filter[0] = 0x00000000; 343 lp->init_block.filter[1] = 0x00000000; 344 345 /* 346 * Initialize the Rx ring. 347 */ 348 lp->cur_rx = 0; 349 for (i = 0; i < RX_RING_SIZE; i++) { 350 lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]); 351 lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ); 352 lp->rx_ring[i].status = cpu_to_le16 (0x8000); 353 PCNET_DEBUG1 354 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, 355 lp->rx_ring[i].base, lp->rx_ring[i].buf_length, 356 lp->rx_ring[i].status); 357 } 358 359 /* 360 * Initialize the Tx ring. The Tx buffer address is filled in as 361 * needed, but we do need to clear the upper ownership bit. 362 */ 363 lp->cur_tx = 0; 364 for (i = 0; i < TX_RING_SIZE; i++) { 365 lp->tx_ring[i].base = 0; 366 lp->tx_ring[i].status = 0; 367 } 368 369 /* 370 * Setup Init Block. 371 */ 372 PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block); 373 374 for (i = 0; i < 6; i++) { 375 lp->init_block.phys_addr[i] = dev->enetaddr[i]; 376 PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]); 377 } 378 379 lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS | 380 RX_RING_LEN_BITS); 381 lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring); 382 lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring); 383 384 PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", 385 lp->init_block.tlen_rlen, 386 lp->init_block.rx_ring, lp->init_block.tx_ring); 387 388 /* 389 * Tell the controller where the Init Block is located. 390 */ 391 addr = PCI_TO_MEM (dev, &lp->init_block); 392 pcnet_write_csr (dev, 1, addr & 0xffff); 393 pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff); 394 395 pcnet_write_csr (dev, 4, 0x0915); 396 pcnet_write_csr (dev, 0, 0x0001); /* start */ 397 398 /* Wait for Init Done bit */ 399 for (i = 10000; i > 0; i--) { 400 if (pcnet_read_csr (dev, 0) & 0x0100) 401 break; 402 udelay (10); 403 } 404 if (i <= 0) { 405 printf ("%s: TIMEOUT: controller init failed\n", dev->name); 406 pcnet_reset (dev); 407 return -1; 408 } 409 410 /* 411 * Finally start network controller operation. 412 */ 413 pcnet_write_csr (dev, 0, 0x0002); 414 415 return 0; 416 } 417 418 static int pcnet_send (struct eth_device *dev, volatile void *packet, 419 int pkt_len) 420 { 421 int i, status; 422 struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; 423 424 PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, 425 packet); 426 427 /* Wait for completion by testing the OWN bit */ 428 for (i = 1000; i > 0; i--) { 429 status = le16_to_cpu (entry->status); 430 if ((status & 0x8000) == 0) 431 break; 432 udelay (100); 433 PCNET_DEBUG2 ("."); 434 } 435 if (i <= 0) { 436 printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", 437 dev->name, lp->cur_tx, status); 438 pkt_len = 0; 439 goto failure; 440 } 441 442 /* 443 * Setup Tx ring. Caution: the write order is important here, 444 * set the status with the "ownership" bits last. 445 */ 446 status = 0x8300; 447 entry->length = le16_to_cpu (-pkt_len); 448 entry->misc = 0x00000000; 449 entry->base = PCI_TO_MEM_LE (dev, packet); 450 entry->status = le16_to_cpu (status); 451 452 /* Trigger an immediate send poll. */ 453 pcnet_write_csr (dev, 0, 0x0008); 454 455 failure: 456 if (++lp->cur_tx >= TX_RING_SIZE) 457 lp->cur_tx = 0; 458 459 PCNET_DEBUG2 ("done\n"); 460 return pkt_len; 461 } 462 463 static int pcnet_recv (struct eth_device *dev) 464 { 465 struct pcnet_rx_head *entry; 466 int pkt_len = 0; 467 u16 status; 468 469 while (1) { 470 entry = &lp->rx_ring[lp->cur_rx]; 471 /* 472 * If we own the next entry, it's a new packet. Send it up. 473 */ 474 if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) { 475 break; 476 } 477 status >>= 8; 478 479 if (status != 0x03) { /* There was an error. */ 480 481 printf ("%s: Rx%d", dev->name, lp->cur_rx); 482 PCNET_DEBUG1 (" (status=0x%x)", status); 483 if (status & 0x20) 484 printf (" Frame"); 485 if (status & 0x10) 486 printf (" Overflow"); 487 if (status & 0x08) 488 printf (" CRC"); 489 if (status & 0x04) 490 printf (" Fifo"); 491 printf (" Error\n"); 492 entry->status &= le16_to_cpu (0x03ff); 493 494 } else { 495 496 pkt_len = 497 (le32_to_cpu (entry->msg_length) & 0xfff) - 4; 498 if (pkt_len < 60) { 499 printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); 500 } else { 501 NetReceive (lp->rx_buf[lp->cur_rx], pkt_len); 502 PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n", 503 lp->cur_rx, pkt_len, 504 lp->rx_buf[lp->cur_rx]); 505 } 506 } 507 entry->status |= cpu_to_le16 (0x8000); 508 509 if (++lp->cur_rx >= RX_RING_SIZE) 510 lp->cur_rx = 0; 511 } 512 return pkt_len; 513 } 514 515 static void pcnet_halt (struct eth_device *dev) 516 { 517 int i; 518 519 PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name); 520 521 /* Reset the PCnet controller */ 522 pcnet_reset (dev); 523 524 /* Wait for Stop bit */ 525 for (i = 1000; i > 0; i--) { 526 if (pcnet_read_csr (dev, 0) & 0x4) 527 break; 528 udelay (10); 529 } 530 if (i <= 0) { 531 printf ("%s: TIMEOUT: controller reset failed\n", dev->name); 532 } 533 } 534