1 /* 2 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de. 3 * 4 * This driver for AMD PCnet network controllers is derived from the 5 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer. 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #include <common.h> 27 #include <malloc.h> 28 #include <net.h> 29 #include <asm/io.h> 30 #include <pci.h> 31 32 #if 0 33 #define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */ 34 #endif 35 36 #if PCNET_DEBUG_LEVEL > 0 37 #define PCNET_DEBUG1(fmt,args...) printf (fmt ,##args) 38 #if PCNET_DEBUG_LEVEL > 1 39 #define PCNET_DEBUG2(fmt,args...) printf (fmt ,##args) 40 #else 41 #define PCNET_DEBUG2(fmt,args...) 42 #endif 43 #else 44 #define PCNET_DEBUG1(fmt,args...) 45 #define PCNET_DEBUG2(fmt,args...) 46 #endif 47 48 #if !defined(CONF_PCNET_79C973) && defined(CONF_PCNET_79C975) 49 #error "Macro for PCnet chip version is not defined!" 50 #endif 51 52 /* 53 * Set the number of Tx and Rx buffers, using Log_2(# buffers). 54 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers. 55 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4). 56 */ 57 #define PCNET_LOG_TX_BUFFERS 0 58 #define PCNET_LOG_RX_BUFFERS 2 59 60 #define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS)) 61 #define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12) 62 63 #define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS)) 64 #define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4) 65 66 #define PKT_BUF_SZ 1544 67 68 /* The PCNET Rx and Tx ring descriptors. */ 69 struct pcnet_rx_head { 70 u32 base; 71 s16 buf_length; 72 s16 status; 73 u32 msg_length; 74 u32 reserved; 75 }; 76 77 struct pcnet_tx_head { 78 u32 base; 79 s16 length; 80 s16 status; 81 u32 misc; 82 u32 reserved; 83 }; 84 85 /* The PCNET 32-Bit initialization block, described in databook. */ 86 struct pcnet_init_block { 87 u16 mode; 88 u16 tlen_rlen; 89 u8 phys_addr[6]; 90 u16 reserved; 91 u32 filter[2]; 92 /* Receive and transmit ring base, along with extra bits. */ 93 u32 rx_ring; 94 u32 tx_ring; 95 u32 reserved2; 96 }; 97 98 typedef struct pcnet_priv { 99 struct pcnet_rx_head rx_ring[RX_RING_SIZE]; 100 struct pcnet_tx_head tx_ring[TX_RING_SIZE]; 101 struct pcnet_init_block init_block; 102 /* Receive Buffer space */ 103 unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4]; 104 int cur_rx; 105 int cur_tx; 106 } pcnet_priv_t; 107 108 static pcnet_priv_t *lp; 109 110 /* Offsets from base I/O address for WIO mode */ 111 #define PCNET_RDP 0x10 112 #define PCNET_RAP 0x12 113 #define PCNET_RESET 0x14 114 #define PCNET_BDP 0x16 115 116 static u16 pcnet_read_csr (struct eth_device *dev, int index) 117 { 118 outw (index, dev->iobase + PCNET_RAP); 119 return inw (dev->iobase + PCNET_RDP); 120 } 121 122 static void pcnet_write_csr (struct eth_device *dev, int index, u16 val) 123 { 124 outw (index, dev->iobase + PCNET_RAP); 125 outw (val, dev->iobase + PCNET_RDP); 126 } 127 128 static u16 pcnet_read_bcr (struct eth_device *dev, int index) 129 { 130 outw (index, dev->iobase + PCNET_RAP); 131 return inw (dev->iobase + PCNET_BDP); 132 } 133 134 static void pcnet_write_bcr (struct eth_device *dev, int index, u16 val) 135 { 136 outw (index, dev->iobase + PCNET_RAP); 137 outw (val, dev->iobase + PCNET_BDP); 138 } 139 140 static void pcnet_reset (struct eth_device *dev) 141 { 142 inw (dev->iobase + PCNET_RESET); 143 } 144 145 static int pcnet_check (struct eth_device *dev) 146 { 147 outw (88, dev->iobase + PCNET_RAP); 148 return (inw (dev->iobase + PCNET_RAP) == 88); 149 } 150 151 static int pcnet_init (struct eth_device *dev, bd_t * bis); 152 static int pcnet_send (struct eth_device *dev, volatile void *packet, 153 int length); 154 static int pcnet_recv (struct eth_device *dev); 155 static void pcnet_halt (struct eth_device *dev); 156 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num); 157 158 #define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a)) 159 #define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a))) 160 161 static struct pci_device_id supported[] = { 162 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE}, 163 {} 164 }; 165 166 167 int pcnet_initialize (bd_t * bis) 168 { 169 pci_dev_t devbusfn; 170 struct eth_device *dev; 171 u16 command, status; 172 int dev_nr = 0; 173 174 PCNET_DEBUG1 ("\npcnet_initialize...\n"); 175 176 for (dev_nr = 0;; dev_nr++) { 177 178 /* 179 * Find the PCnet PCI device(s). 180 */ 181 if ((devbusfn = pci_find_devices (supported, dev_nr)) < 0) { 182 break; 183 } 184 185 /* 186 * Allocate and pre-fill the device structure. 187 */ 188 dev = (struct eth_device *) malloc (sizeof *dev); 189 dev->priv = (void *) devbusfn; 190 sprintf (dev->name, "pcnet#%d", dev_nr); 191 192 /* 193 * Setup the PCI device. 194 */ 195 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, 196 (unsigned int *) &dev->iobase); 197 dev->iobase=pci_io_to_phys (devbusfn, dev->iobase); 198 dev->iobase &= ~0xf; 199 200 PCNET_DEBUG1 ("%s: devbusfn=0x%x iobase=0x%x: ", 201 dev->name, devbusfn, dev->iobase); 202 203 command = PCI_COMMAND_IO | PCI_COMMAND_MASTER; 204 pci_write_config_word (devbusfn, PCI_COMMAND, command); 205 pci_read_config_word (devbusfn, PCI_COMMAND, &status); 206 if ((status & command) != command) { 207 printf ("%s: Couldn't enable IO access or Bus Mastering\n", dev->name); 208 free (dev); 209 continue; 210 } 211 212 pci_write_config_byte (devbusfn, PCI_LATENCY_TIMER, 0x40); 213 214 /* 215 * Probe the PCnet chip. 216 */ 217 if (pcnet_probe (dev, bis, dev_nr) < 0) { 218 free (dev); 219 continue; 220 } 221 222 /* 223 * Setup device structure and register the driver. 224 */ 225 dev->init = pcnet_init; 226 dev->halt = pcnet_halt; 227 dev->send = pcnet_send; 228 dev->recv = pcnet_recv; 229 230 eth_register (dev); 231 } 232 233 udelay (10 * 1000); 234 235 return dev_nr; 236 } 237 238 static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_nr) 239 { 240 int chip_version; 241 char *chipname; 242 243 #ifdef PCNET_HAS_PROM 244 int i; 245 #endif 246 247 /* Reset the PCnet controller */ 248 pcnet_reset (dev); 249 250 /* Check if register access is working */ 251 if (pcnet_read_csr (dev, 0) != 4 || !pcnet_check (dev)) { 252 printf ("%s: CSR register access check failed\n", dev->name); 253 return -1; 254 } 255 256 /* Identify the chip */ 257 chip_version = 258 pcnet_read_csr (dev, 88) | (pcnet_read_csr (dev, 89) << 16); 259 if ((chip_version & 0xfff) != 0x003) 260 return -1; 261 chip_version = (chip_version >> 12) & 0xffff; 262 switch (chip_version) { 263 case 0x2621: 264 chipname = "PCnet/PCI II 79C970A"; /* PCI */ 265 break; 266 #ifdef CONFIG_PCNET_79C973 267 case 0x2625: 268 chipname = "PCnet/FAST III 79C973"; /* PCI */ 269 break; 270 #endif 271 #ifdef CONFIG_PCNET_79C975 272 case 0x2627: 273 chipname = "PCnet/FAST III 79C975"; /* PCI */ 274 break; 275 #endif 276 default: 277 printf ("%s: PCnet version %#x not supported\n", 278 dev->name, chip_version); 279 return -1; 280 } 281 282 PCNET_DEBUG1 ("AMD %s\n", chipname); 283 284 #ifdef PCNET_HAS_PROM 285 /* 286 * In most chips, after a chip reset, the ethernet address is read from 287 * the station address PROM at the base address and programmed into the 288 * "Physical Address Registers" CSR12-14. 289 */ 290 for (i = 0; i < 3; i++) { 291 unsigned int val; 292 293 val = pcnet_read_csr (dev, i + 12) & 0x0ffff; 294 /* There may be endianness issues here. */ 295 dev->enetaddr[2 * i] = val & 0x0ff; 296 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff; 297 } 298 #endif /* PCNET_HAS_PROM */ 299 300 return 0; 301 } 302 303 static int pcnet_init (struct eth_device *dev, bd_t * bis) 304 { 305 int i, val; 306 u32 addr; 307 308 PCNET_DEBUG1 ("%s: pcnet_init...\n", dev->name); 309 310 /* Switch pcnet to 32bit mode */ 311 pcnet_write_bcr (dev, 20, 2); 312 313 #ifdef CONFIG_PN62 314 /* Setup LED registers */ 315 val = pcnet_read_bcr (dev, 2) | 0x1000; 316 pcnet_write_bcr (dev, 2, val); /* enable LEDPE */ 317 pcnet_write_bcr (dev, 4, 0x5080); /* 100MBit */ 318 pcnet_write_bcr (dev, 5, 0x40c0); /* LNKSE */ 319 pcnet_write_bcr (dev, 6, 0x4090); /* TX Activity */ 320 pcnet_write_bcr (dev, 7, 0x4084); /* RX Activity */ 321 #endif 322 323 /* Set/reset autoselect bit */ 324 val = pcnet_read_bcr (dev, 2) & ~2; 325 val |= 2; 326 pcnet_write_bcr (dev, 2, val); 327 328 /* Enable auto negotiate, setup, disable fd */ 329 val = pcnet_read_bcr (dev, 32) & ~0x98; 330 val |= 0x20; 331 pcnet_write_bcr (dev, 32, val); 332 333 /* 334 * We only maintain one structure because the drivers will never 335 * be used concurrently. In 32bit mode the RX and TX ring entries 336 * must be aligned on 16-byte boundaries. 337 */ 338 if (lp == NULL) { 339 addr = (u32) malloc (sizeof (pcnet_priv_t) + 0x10); 340 addr = (addr + 0xf) & ~0xf; 341 lp = (pcnet_priv_t *) addr; 342 } 343 344 lp->init_block.mode = cpu_to_le16 (0x0000); 345 lp->init_block.filter[0] = 0x00000000; 346 lp->init_block.filter[1] = 0x00000000; 347 348 /* 349 * Initialize the Rx ring. 350 */ 351 lp->cur_rx = 0; 352 for (i = 0; i < RX_RING_SIZE; i++) { 353 lp->rx_ring[i].base = PCI_TO_MEM_LE (dev, lp->rx_buf[i]); 354 lp->rx_ring[i].buf_length = cpu_to_le16 (-PKT_BUF_SZ); 355 lp->rx_ring[i].status = cpu_to_le16 (0x8000); 356 PCNET_DEBUG1 357 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i, 358 lp->rx_ring[i].base, lp->rx_ring[i].buf_length, 359 lp->rx_ring[i].status); 360 } 361 362 /* 363 * Initialize the Tx ring. The Tx buffer address is filled in as 364 * needed, but we do need to clear the upper ownership bit. 365 */ 366 lp->cur_tx = 0; 367 for (i = 0; i < TX_RING_SIZE; i++) { 368 lp->tx_ring[i].base = 0; 369 lp->tx_ring[i].status = 0; 370 } 371 372 /* 373 * Setup Init Block. 374 */ 375 PCNET_DEBUG1 ("Init block at 0x%p: MAC", &lp->init_block); 376 377 for (i = 0; i < 6; i++) { 378 lp->init_block.phys_addr[i] = dev->enetaddr[i]; 379 PCNET_DEBUG1 (" %02x", lp->init_block.phys_addr[i]); 380 } 381 382 lp->init_block.tlen_rlen = cpu_to_le16 (TX_RING_LEN_BITS | 383 RX_RING_LEN_BITS); 384 lp->init_block.rx_ring = PCI_TO_MEM_LE (dev, lp->rx_ring); 385 lp->init_block.tx_ring = PCI_TO_MEM_LE (dev, lp->tx_ring); 386 387 PCNET_DEBUG1 ("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n", 388 lp->init_block.tlen_rlen, 389 lp->init_block.rx_ring, lp->init_block.tx_ring); 390 391 /* 392 * Tell the controller where the Init Block is located. 393 */ 394 addr = PCI_TO_MEM (dev, &lp->init_block); 395 pcnet_write_csr (dev, 1, addr & 0xffff); 396 pcnet_write_csr (dev, 2, (addr >> 16) & 0xffff); 397 398 pcnet_write_csr (dev, 4, 0x0915); 399 pcnet_write_csr (dev, 0, 0x0001); /* start */ 400 401 /* Wait for Init Done bit */ 402 for (i = 10000; i > 0; i--) { 403 if (pcnet_read_csr (dev, 0) & 0x0100) 404 break; 405 udelay (10); 406 } 407 if (i <= 0) { 408 printf ("%s: TIMEOUT: controller init failed\n", dev->name); 409 pcnet_reset (dev); 410 return -1; 411 } 412 413 /* 414 * Finally start network controller operation. 415 */ 416 pcnet_write_csr (dev, 0, 0x0002); 417 418 return 0; 419 } 420 421 static int pcnet_send (struct eth_device *dev, volatile void *packet, 422 int pkt_len) 423 { 424 int i, status; 425 struct pcnet_tx_head *entry = &lp->tx_ring[lp->cur_tx]; 426 427 PCNET_DEBUG2 ("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len, 428 packet); 429 430 /* Wait for completion by testing the OWN bit */ 431 for (i = 1000; i > 0; i--) { 432 status = le16_to_cpu (entry->status); 433 if ((status & 0x8000) == 0) 434 break; 435 udelay (100); 436 PCNET_DEBUG2 ("."); 437 } 438 if (i <= 0) { 439 printf ("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n", 440 dev->name, lp->cur_tx, status); 441 pkt_len = 0; 442 goto failure; 443 } 444 445 /* 446 * Setup Tx ring. Caution: the write order is important here, 447 * set the status with the "ownership" bits last. 448 */ 449 status = 0x8300; 450 entry->length = le16_to_cpu (-pkt_len); 451 entry->misc = 0x00000000; 452 entry->base = PCI_TO_MEM_LE (dev, packet); 453 entry->status = le16_to_cpu (status); 454 455 /* Trigger an immediate send poll. */ 456 pcnet_write_csr (dev, 0, 0x0008); 457 458 failure: 459 if (++lp->cur_tx >= TX_RING_SIZE) 460 lp->cur_tx = 0; 461 462 PCNET_DEBUG2 ("done\n"); 463 return pkt_len; 464 } 465 466 static int pcnet_recv (struct eth_device *dev) 467 { 468 struct pcnet_rx_head *entry; 469 int pkt_len = 0; 470 u16 status; 471 472 while (1) { 473 entry = &lp->rx_ring[lp->cur_rx]; 474 /* 475 * If we own the next entry, it's a new packet. Send it up. 476 */ 477 if (((status = le16_to_cpu (entry->status)) & 0x8000) != 0) { 478 break; 479 } 480 status >>= 8; 481 482 if (status != 0x03) { /* There was an error. */ 483 484 printf ("%s: Rx%d", dev->name, lp->cur_rx); 485 PCNET_DEBUG1 (" (status=0x%x)", status); 486 if (status & 0x20) 487 printf (" Frame"); 488 if (status & 0x10) 489 printf (" Overflow"); 490 if (status & 0x08) 491 printf (" CRC"); 492 if (status & 0x04) 493 printf (" Fifo"); 494 printf (" Error\n"); 495 entry->status &= le16_to_cpu (0x03ff); 496 497 } else { 498 499 pkt_len = 500 (le32_to_cpu (entry->msg_length) & 0xfff) - 4; 501 if (pkt_len < 60) { 502 printf ("%s: Rx%d: invalid packet length %d\n", dev->name, lp->cur_rx, pkt_len); 503 } else { 504 NetReceive (lp->rx_buf[lp->cur_rx], pkt_len); 505 PCNET_DEBUG2 ("Rx%d: %d bytes from 0x%p\n", 506 lp->cur_rx, pkt_len, 507 lp->rx_buf[lp->cur_rx]); 508 } 509 } 510 entry->status |= cpu_to_le16 (0x8000); 511 512 if (++lp->cur_rx >= RX_RING_SIZE) 513 lp->cur_rx = 0; 514 } 515 return pkt_len; 516 } 517 518 static void pcnet_halt (struct eth_device *dev) 519 { 520 int i; 521 522 PCNET_DEBUG1 ("%s: pcnet_halt...\n", dev->name); 523 524 /* Reset the PCnet controller */ 525 pcnet_reset (dev); 526 527 /* Wait for Stop bit */ 528 for (i = 1000; i > 0; i--) { 529 if (pcnet_read_csr (dev, 0) & 0x4) 530 break; 531 udelay (10); 532 } 533 if (i <= 0) { 534 printf ("%s: TIMEOUT: controller reset failed\n", dev->name); 535 } 536 } 537