xref: /openbmc/u-boot/drivers/net/pch_gbe.h (revision b6152676)
1 /*
2  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3  *
4  * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
5  * Adapted from linux drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #ifndef _PCH_GBE_H_
11 #define _PCH_GBE_H_
12 
13 #define PCH_GBE_TIMEOUT		(3 * CONFIG_SYS_HZ)
14 
15 #define PCH_GBE_DESC_NUM	4
16 #define PCH_GBE_ALIGN_SIZE	64
17 
18 /*
19  * Topcliff GBE MAC supports receiving ethernet frames with normal frame size
20  * (64-1518 bytes) as well as up to 10318 bytes, however it does not have a
21  * register bit to turn off receiving 'jumbo frame', so we have to allocate
22  * our own buffer to store the received frames instead of using U-Boot's own.
23  */
24 #define PCH_GBE_RX_FRAME_LEN	ROUND(10318, PCH_GBE_ALIGN_SIZE)
25 
26 /* Interrupt Status */
27 /* Interrupt Status Hold */
28 /* Interrupt Enable */
29 #define PCH_GBE_INT_RX_DMA_CMPLT	0x00000001
30 #define PCH_GBE_INT_RX_VALID		0x00000002
31 #define PCH_GBE_INT_RX_FRAME_ERR	0x00000004
32 #define PCH_GBE_INT_RX_FIFO_ERR		0x00000008
33 #define PCH_GBE_INT_RX_DMA_ERR		0x00000010
34 #define PCH_GBE_INT_RX_DSC_EMP		0x00000020
35 #define PCH_GBE_INT_TX_CMPLT		0x00000100
36 #define PCH_GBE_INT_TX_DMA_CMPLT	0x00000200
37 #define PCH_GBE_INT_TX_FIFO_ERR		0x00000400
38 #define PCH_GBE_INT_TX_DMA_ERR		0x00000800
39 #define PCH_GBE_INT_PAUSE_CMPLT		0x00001000
40 #define PCH_GBE_INT_MIIM_CMPLT		0x00010000
41 #define PCH_GBE_INT_PHY_INT		0x00100000
42 #define PCH_GBE_INT_WOL_DET		0x01000000
43 #define PCH_GBE_INT_TCPIP_ERR		0x10000000
44 
45 /* Mode */
46 #define PCH_GBE_MODE_MII_ETHER		0x00000000
47 #define PCH_GBE_MODE_GMII_ETHER		0x80000000
48 #define PCH_GBE_MODE_HALF_DUPLEX	0x00000000
49 #define PCH_GBE_MODE_FULL_DUPLEX	0x40000000
50 #define PCH_GBE_MODE_FR_BST		0x04000000
51 
52 /* Reset */
53 #define PCH_GBE_ALL_RST			0x80000000
54 #define PCH_GBE_TX_RST			0x00008000
55 #define PCH_GBE_RX_RST			0x00004000
56 
57 /* TCP/IP Accelerator Control */
58 #define PCH_GBE_EX_LIST_EN		0x00000008
59 #define PCH_GBE_RX_TCPIPACC_OFF		0x00000004
60 #define PCH_GBE_TX_TCPIPACC_EN		0x00000002
61 #define PCH_GBE_RX_TCPIPACC_EN		0x00000001
62 
63 /* MAC RX Enable */
64 #define PCH_GBE_MRE_MAC_RX_EN		0x00000001
65 
66 /* RX Flow Control */
67 #define PCH_GBE_FL_CTRL_EN		0x80000000
68 
69 /* RX Mode */
70 #define PCH_GBE_ADD_FIL_EN		0x80000000
71 #define PCH_GBE_MLT_FIL_EN		0x40000000
72 #define PCH_GBE_RH_ALM_EMP_4		0x00000000
73 #define PCH_GBE_RH_ALM_EMP_8		0x00004000
74 #define PCH_GBE_RH_ALM_EMP_16		0x00008000
75 #define PCH_GBE_RH_ALM_EMP_32		0x0000c000
76 #define PCH_GBE_RH_ALM_FULL_4		0x00000000
77 #define PCH_GBE_RH_ALM_FULL_8		0x00001000
78 #define PCH_GBE_RH_ALM_FULL_16		0x00002000
79 #define PCH_GBE_RH_ALM_FULL_32		0x00003000
80 #define PCH_GBE_RH_RD_TRG_4		0x00000000
81 #define PCH_GBE_RH_RD_TRG_8		0x00000200
82 #define PCH_GBE_RH_RD_TRG_16		0x00000400
83 #define PCH_GBE_RH_RD_TRG_32		0x00000600
84 #define PCH_GBE_RH_RD_TRG_64		0x00000800
85 #define PCH_GBE_RH_RD_TRG_128		0x00000a00
86 #define PCH_GBE_RH_RD_TRG_256		0x00000c00
87 #define PCH_GBE_RH_RD_TRG_512		0x00000e00
88 
89 /* TX Mode */
90 #define PCH_GBE_TM_NO_RTRY		0x80000000
91 #define PCH_GBE_TM_LONG_PKT		0x40000000
92 #define PCH_GBE_TM_ST_AND_FD		0x20000000
93 #define PCH_GBE_TM_SHORT_PKT		0x10000000
94 #define PCH_GBE_TM_LTCOL_RETX		0x08000000
95 #define PCH_GBE_TM_TH_TX_STRT_4		0x00000000
96 #define PCH_GBE_TM_TH_TX_STRT_8		0x00004000
97 #define PCH_GBE_TM_TH_TX_STRT_16	0x00008000
98 #define PCH_GBE_TM_TH_TX_STRT_32	0x0000c000
99 #define PCH_GBE_TM_TH_ALM_EMP_4		0x00000000
100 #define PCH_GBE_TM_TH_ALM_EMP_8		0x00000800
101 #define PCH_GBE_TM_TH_ALM_EMP_16	0x00001000
102 #define PCH_GBE_TM_TH_ALM_EMP_32	0x00001800
103 #define PCH_GBE_TM_TH_ALM_EMP_64	0x00002000
104 #define PCH_GBE_TM_TH_ALM_EMP_128	0x00002800
105 #define PCH_GBE_TM_TH_ALM_EMP_256	0x00003000
106 #define PCH_GBE_TM_TH_ALM_EMP_512	0x00003800
107 #define PCH_GBE_TM_TH_ALM_FULL_4	0x00000000
108 #define PCH_GBE_TM_TH_ALM_FULL_8	0x00000200
109 #define PCH_GBE_TM_TH_ALM_FULL_16	0x00000400
110 #define PCH_GBE_TM_TH_ALM_FULL_32	0x00000600
111 
112 /* MAC Address Mask */
113 #define PCH_GBE_BUSY			0x80000000
114 
115 /* MIIM  */
116 #define PCH_GBE_MIIM_OPER_WRITE		0x04000000
117 #define PCH_GBE_MIIM_OPER_READ		0x00000000
118 #define PCH_GBE_MIIM_OPER_READY		0x04000000
119 #define PCH_GBE_MIIM_PHY_ADDR_SHIFT	21
120 #define PCH_GBE_MIIM_REG_ADDR_SHIFT	16
121 
122 /* RGMII Control */
123 #define PCH_GBE_CRS_SEL			0x00000010
124 #define PCH_GBE_RGMII_RATE_125M		0x00000000
125 #define PCH_GBE_RGMII_RATE_25M		0x00000008
126 #define PCH_GBE_RGMII_RATE_2_5M		0x0000000c
127 #define PCH_GBE_RGMII_MODE_GMII		0x00000000
128 #define PCH_GBE_RGMII_MODE_RGMII	0x00000002
129 #define PCH_GBE_CHIP_TYPE_EXTERNAL	0x00000000
130 #define PCH_GBE_CHIP_TYPE_INTERNAL	0x00000001
131 
132 /* DMA Control */
133 #define PCH_GBE_RX_DMA_EN		0x00000002
134 #define PCH_GBE_TX_DMA_EN		0x00000001
135 
136 /* Receive Descriptor bit definitions */
137 #define PCH_GBE_RXD_ACC_STAT_BCAST	0x00000400
138 #define PCH_GBE_RXD_ACC_STAT_MCAST	0x00000200
139 #define PCH_GBE_RXD_ACC_STAT_UCAST	0x00000100
140 #define PCH_GBE_RXD_ACC_STAT_TCPIPOK	0x000000c0
141 #define PCH_GBE_RXD_ACC_STAT_IPOK	0x00000080
142 #define PCH_GBE_RXD_ACC_STAT_TCPOK	0x00000040
143 #define PCH_GBE_RXD_ACC_STAT_IP6ERR	0x00000020
144 #define PCH_GBE_RXD_ACC_STAT_OFLIST	0x00000010
145 #define PCH_GBE_RXD_ACC_STAT_TYPEIP	0x00000008
146 #define PCH_GBE_RXD_ACC_STAT_MACL	0x00000004
147 #define PCH_GBE_RXD_ACC_STAT_PPPOE	0x00000002
148 #define PCH_GBE_RXD_ACC_STAT_VTAGT	0x00000001
149 #define PCH_GBE_RXD_GMAC_STAT_PAUSE	0x0200
150 #define PCH_GBE_RXD_GMAC_STAT_MARBR	0x0100
151 #define PCH_GBE_RXD_GMAC_STAT_MARMLT	0x0080
152 #define PCH_GBE_RXD_GMAC_STAT_MARIND	0x0040
153 #define PCH_GBE_RXD_GMAC_STAT_MARNOTMT	0x0020
154 #define PCH_GBE_RXD_GMAC_STAT_TLONG	0x0010
155 #define PCH_GBE_RXD_GMAC_STAT_TSHRT	0x0008
156 #define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL	0x0004
157 #define PCH_GBE_RXD_GMAC_STAT_NBLERR	0x0002
158 #define PCH_GBE_RXD_GMAC_STAT_CRCERR	0x0001
159 
160 /* Transmit Descriptor bit definitions */
161 #define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF	0x0008
162 #define PCH_GBE_TXD_CTRL_ITAG		0x0004
163 #define PCH_GBE_TXD_CTRL_ICRC		0x0002
164 #define PCH_GBE_TXD_CTRL_APAD		0x0001
165 #define PCH_GBE_TXD_WORDS_SHIFT		2
166 #define PCH_GBE_TXD_GMAC_STAT_CMPLT	0x2000
167 #define PCH_GBE_TXD_GMAC_STAT_ABT	0x1000
168 #define PCH_GBE_TXD_GMAC_STAT_EXCOL	0x0800
169 #define PCH_GBE_TXD_GMAC_STAT_SNGCOL	0x0400
170 #define PCH_GBE_TXD_GMAC_STAT_MLTCOL	0x0200
171 #define PCH_GBE_TXD_GMAC_STAT_CRSER	0x0100
172 #define PCH_GBE_TXD_GMAC_STAT_TLNG	0x0080
173 #define PCH_GBE_TXD_GMAC_STAT_TSHRT	0x0040
174 #define PCH_GBE_TXD_GMAC_STAT_LTCOL	0x0020
175 #define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW	0x0010
176 
177 /**
178  * struct pch_gbe_rx_desc - Receive Descriptor
179  * @buffer_addr:	RX Frame Buffer Address
180  * @tcp_ip_status:	TCP/IP Accelerator Status
181  * @rx_words_eob:	RX word count and Byte position
182  * @gbec_status:	GMAC Status
183  * @dma_status:		DMA Status
184  * @reserved1:		Reserved
185  * @reserved2:		Reserved
186  */
187 struct pch_gbe_rx_desc {
188 	u32 buffer_addr;
189 	u32 tcp_ip_status;
190 	u16 rx_words_eob;
191 	u16 gbec_status;
192 	u8 dma_status;
193 	u8 reserved1;
194 	u16 reserved2;
195 };
196 
197 /**
198  * struct pch_gbe_tx_desc - Transmit Descriptor
199  * @buffer_addr:	TX Frame Buffer Address
200  * @length:		Data buffer length
201  * @reserved1:		Reserved
202  * @tx_words_eob:	TX word count and Byte position
203  * @tx_frame_ctrl:	TX Frame Control
204  * @dma_status:		DMA Status
205  * @reserved2:		Reserved
206  * @gbec_status:	GMAC Status
207  */
208 struct pch_gbe_tx_desc {
209 	u32 buffer_addr;
210 	u16 length;
211 	u16 reserved1;
212 	u16 tx_words_eob;
213 	u16 tx_frame_ctrl;
214 	u8 dma_status;
215 	u8 reserved2;
216 	u16 gbec_status;
217 };
218 
219 /**
220  * pch_gbe_regs_mac_adr - structure holding values of mac address registers
221  *
222  * @high	Denotes the 1st to 4th byte from the initial of MAC address
223  * @low		Denotes the 5th to 6th byte from the initial of MAC address
224  */
225 struct pch_gbe_regs_mac_adr {
226 	u32 high;
227 	u32 low;
228 };
229 
230 /**
231  * pch_gbe_regs - structure holding values of MAC registers
232  */
233 struct pch_gbe_regs {
234 	u32 int_st;
235 	u32 int_en;
236 	u32 mode;
237 	u32 reset;
238 	u32 tcpip_acc;
239 	u32 ex_list;
240 	u32 int_st_hold;
241 	u32 phy_int_ctrl;
242 	u32 mac_rx_en;
243 	u32 rx_fctrl;
244 	u32 pause_req;
245 	u32 rx_mode;
246 	u32 tx_mode;
247 	u32 rx_fifo_st;
248 	u32 tx_fifo_st;
249 	u32 tx_fid;
250 	u32 tx_result;
251 	u32 pause_pkt1;
252 	u32 pause_pkt2;
253 	u32 pause_pkt3;
254 	u32 pause_pkt4;
255 	u32 pause_pkt5;
256 	u32 reserve[2];
257 	struct pch_gbe_regs_mac_adr mac_adr[16];
258 	u32 addr_mask;
259 	u32 miim;
260 	u32 mac_addr_load;
261 	u32 rgmii_st;
262 	u32 rgmii_ctrl;
263 	u32 reserve3[3];
264 	u32 dma_ctrl;
265 	u32 reserve4[3];
266 	u32 rx_dsc_base;
267 	u32 rx_dsc_size;
268 	u32 rx_dsc_hw_p;
269 	u32 rx_dsc_hw_p_hld;
270 	u32 rx_dsc_sw_p;
271 	u32 reserve5[3];
272 	u32 tx_dsc_base;
273 	u32 tx_dsc_size;
274 	u32 tx_dsc_hw_p;
275 	u32 tx_dsc_hw_p_hld;
276 	u32 tx_dsc_sw_p;
277 	u32 reserve6[3];
278 	u32 rx_dma_st;
279 	u32 tx_dma_st;
280 	u32 reserve7[2];
281 	u32 wol_st;
282 	u32 wol_ctrl;
283 	u32 wol_addr_mask;
284 };
285 
286 struct pch_gbe_priv {
287 	struct pch_gbe_rx_desc rx_desc[PCH_GBE_DESC_NUM];
288 	struct pch_gbe_tx_desc tx_desc[PCH_GBE_DESC_NUM];
289 	char rx_buff[PCH_GBE_DESC_NUM][PCH_GBE_RX_FRAME_LEN];
290 	struct phy_device *phydev;
291 	struct mii_dev *bus;
292 	struct pch_gbe_regs *mac_regs;
293 	struct udevice *dev;
294 	int rx_idx;
295 	int tx_idx;
296 };
297 
298 #endif /* _PCH_GBE_H_ */
299