1 /* 2 ns8382x.c: A U-Boot driver for the NatSemi DP8382[01]. 3 ported by: Mark A. Rakes (mark_rakes@vivato.net) 4 5 Adapted from: 6 1. an Etherboot driver for DP8381[56] written by: 7 Copyright (C) 2001 Entity Cyber, Inc. 8 9 This development of this Etherboot driver was funded by 10 Sicom Systems: http://www.sicompos.com/ 11 12 Author: Marty Connor (mdc@thinguin.org) 13 Adapted from a Linux driver which was written by Donald Becker 14 15 This software may be used and distributed according to the terms 16 of the GNU Public License (GPL), incorporated herein by reference. 17 18 2. A Linux driver by Donald Becker, ns820.c: 19 Written/copyright 1999-2002 by Donald Becker. 20 21 This software may be used and distributed according to the terms of 22 the GNU General Public License (GPL), incorporated herein by reference. 23 Drivers based on or derived from this code fall under the GPL and must 24 retain the authorship, copyright and license notice. This file is not 25 a complete program and may only be used when the entire operating 26 system is licensed under the GPL. License for under other terms may be 27 available. Contact the original author for details. 28 29 The original author may be reached as becker@scyld.com, or at 30 Scyld Computing Corporation 31 410 Severn Ave., Suite 210 32 Annapolis MD 21403 33 34 Support information and updates available at 35 http://www.scyld.com/network/netsemi.html 36 37 Datasheets available from: 38 http://www.national.com/pf/DP/DP83820.html 39 http://www.national.com/pf/DP/DP83821.html 40 */ 41 42 /* Revision History 43 * October 2002 mar 1.0 44 * Initial U-Boot Release. 45 * Tested with Netgear GA622T (83820) 46 * and SMC9452TX (83821) 47 * NOTE: custom boards with these chips may (likely) require 48 * a programmed EEPROM device (if present) in order to work 49 * correctly. 50 */ 51 52 /* Includes */ 53 #include <common.h> 54 #include <malloc.h> 55 #include <net.h> 56 #include <netdev.h> 57 #include <asm/io.h> 58 #include <pci.h> 59 60 /* defines */ 61 #define DSIZE 0x00000FFF 62 #define ETH_ALEN 6 63 #define CRC_SIZE 4 64 #define TOUT_LOOP 500000 65 #define TX_BUF_SIZE 1536 66 #define RX_BUF_SIZE 1536 67 #define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */ 68 69 enum register_offsets { 70 ChipCmd = 0x00, 71 ChipConfig = 0x04, 72 EECtrl = 0x08, 73 IntrMask = 0x14, 74 IntrEnable = 0x18, 75 TxRingPtr = 0x20, 76 TxRingPtrHi = 0x24, 77 TxConfig = 0x28, 78 RxRingPtr = 0x30, 79 RxRingPtrHi = 0x34, 80 RxConfig = 0x38, 81 PriQueue = 0x3C, 82 RxFilterAddr = 0x48, 83 RxFilterData = 0x4C, 84 ClkRun = 0xCC, 85 PCIPM = 0x44, 86 }; 87 88 enum ChipCmdBits { 89 ChipReset = 0x100, 90 RxReset = 0x20, 91 TxReset = 0x10, 92 RxOff = 0x08, 93 RxOn = 0x04, 94 TxOff = 0x02, 95 TxOn = 0x01 96 }; 97 98 enum ChipConfigBits { 99 LinkSts = 0x80000000, 100 GigSpeed = 0x40000000, 101 HundSpeed = 0x20000000, 102 FullDuplex = 0x10000000, 103 TBIEn = 0x01000000, 104 Mode1000 = 0x00400000, 105 T64En = 0x00004000, 106 D64En = 0x00001000, 107 M64En = 0x00000800, 108 PhyRst = 0x00000400, 109 PhyDis = 0x00000200, 110 ExtStEn = 0x00000100, 111 BEMode = 0x00000001, 112 }; 113 #define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex) 114 115 enum TxConfig_bits { 116 TxDrthMask = 0x000000ff, 117 TxFlthMask = 0x0000ff00, 118 TxMxdmaMask = 0x00700000, 119 TxMxdma_8 = 0x00100000, 120 TxMxdma_16 = 0x00200000, 121 TxMxdma_32 = 0x00300000, 122 TxMxdma_64 = 0x00400000, 123 TxMxdma_128 = 0x00500000, 124 TxMxdma_256 = 0x00600000, 125 TxMxdma_512 = 0x00700000, 126 TxMxdma_1024 = 0x00000000, 127 TxCollRetry = 0x00800000, 128 TxAutoPad = 0x10000000, 129 TxMacLoop = 0x20000000, 130 TxHeartIgn = 0x40000000, 131 TxCarrierIgn = 0x80000000 132 }; 133 134 enum RxConfig_bits { 135 RxDrthMask = 0x0000003e, 136 RxMxdmaMask = 0x00700000, 137 RxMxdma_8 = 0x00100000, 138 RxMxdma_16 = 0x00200000, 139 RxMxdma_32 = 0x00300000, 140 RxMxdma_64 = 0x00400000, 141 RxMxdma_128 = 0x00500000, 142 RxMxdma_256 = 0x00600000, 143 RxMxdma_512 = 0x00700000, 144 RxMxdma_1024 = 0x00000000, 145 RxAcceptLenErr = 0x04000000, 146 RxAcceptLong = 0x08000000, 147 RxAcceptTx = 0x10000000, 148 RxStripCRC = 0x20000000, 149 RxAcceptRunt = 0x40000000, 150 RxAcceptErr = 0x80000000, 151 }; 152 153 /* Bits in the RxMode register. */ 154 enum rx_mode_bits { 155 RxFilterEnable = 0x80000000, 156 AcceptAllBroadcast = 0x40000000, 157 AcceptAllMulticast = 0x20000000, 158 AcceptAllUnicast = 0x10000000, 159 AcceptPerfectMatch = 0x08000000, 160 }; 161 162 typedef struct _BufferDesc { 163 u32 link; 164 u32 bufptr; 165 vu_long cmdsts; 166 u32 extsts; /*not used here */ 167 } BufferDesc; 168 169 /* Bits in network_desc.status */ 170 enum desc_status_bits { 171 DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000, 172 DescNoCRC = 0x10000000, DescPktOK = 0x08000000, 173 DescSizeMask = 0xfff, 174 175 DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000, 176 DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000, 177 DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000, 178 DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000, 179 180 DescRxAbort = 0x04000000, DescRxOver = 0x02000000, 181 DescRxDest = 0x01800000, DescRxLong = 0x00400000, 182 DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000, 183 DescRxCRC = 0x00080000, DescRxAlign = 0x00040000, 184 DescRxLoop = 0x00020000, DesRxColl = 0x00010000, 185 }; 186 187 /* Bits in MEAR */ 188 enum mii_reg_bits { 189 MDIO_ShiftClk = 0x0040, 190 MDIO_EnbOutput = 0x0020, 191 MDIO_Data = 0x0010, 192 }; 193 194 /* PHY Register offsets. */ 195 enum phy_reg_offsets { 196 BMCR = 0x00, 197 BMSR = 0x01, 198 PHYIDR1 = 0x02, 199 PHYIDR2 = 0x03, 200 ANAR = 0x04, 201 KTCR = 0x09, 202 }; 203 204 /* basic mode control register bits */ 205 enum bmcr_bits { 206 Bmcr_Reset = 0x8000, 207 Bmcr_Loop = 0x4000, 208 Bmcr_Speed0 = 0x2000, 209 Bmcr_AutoNegEn = 0x1000, /*if set ignores Duplex, Speed[01] */ 210 Bmcr_RstAutoNeg = 0x0200, 211 Bmcr_Duplex = 0x0100, 212 Bmcr_Speed1 = 0x0040, 213 Bmcr_Force10H = 0x0000, 214 Bmcr_Force10F = 0x0100, 215 Bmcr_Force100H = 0x2000, 216 Bmcr_Force100F = 0x2100, 217 Bmcr_Force1000H = 0x0040, 218 Bmcr_Force1000F = 0x0140, 219 }; 220 221 /* auto negotiation advertisement register */ 222 enum anar_bits { 223 anar_adv_100F = 0x0100, 224 anar_adv_100H = 0x0080, 225 anar_adv_10F = 0x0040, 226 anar_adv_10H = 0x0020, 227 anar_ieee_8023 = 0x0001, 228 }; 229 230 /* 1K-base T control register */ 231 enum ktcr_bits { 232 ktcr_adv_1000H = 0x0100, 233 ktcr_adv_1000F = 0x0200, 234 }; 235 236 /* Globals */ 237 static u32 SavedClkRun; 238 static unsigned int cur_rx; 239 static unsigned int rx_config; 240 static unsigned int tx_config; 241 242 /* Note: transmit and receive buffers and descriptors must be 243 long long word aligned */ 244 static BufferDesc txd __attribute__ ((aligned(8))); 245 static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(8))); 246 static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(8))); 247 static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE] 248 __attribute__ ((aligned(8))); 249 250 /* Function Prototypes */ 251 static int mdio_read(struct eth_device *dev, int phy_id, int addr); 252 static void mdio_write(struct eth_device *dev, int phy_id, int addr, int value); 253 static void mdio_sync(struct eth_device *dev, u32 offset); 254 static int ns8382x_init(struct eth_device *dev, bd_t * bis); 255 static void ns8382x_reset(struct eth_device *dev); 256 static void ns8382x_init_rxfilter(struct eth_device *dev); 257 static void ns8382x_init_txd(struct eth_device *dev); 258 static void ns8382x_init_rxd(struct eth_device *dev); 259 static void ns8382x_set_rx_mode(struct eth_device *dev); 260 static void ns8382x_check_duplex(struct eth_device *dev); 261 static int ns8382x_send(struct eth_device *dev, volatile void *packet, 262 int length); 263 static int ns8382x_poll(struct eth_device *dev); 264 static void ns8382x_disable(struct eth_device *dev); 265 266 static struct pci_device_id supported[] = { 267 {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83820}, 268 {} 269 }; 270 271 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a) 272 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a) 273 274 static inline int 275 INW(struct eth_device *dev, u_long addr) 276 { 277 return le16_to_cpu(*(vu_short *) (addr + dev->iobase)); 278 } 279 280 static int 281 INL(struct eth_device *dev, u_long addr) 282 { 283 return le32_to_cpu(*(vu_long *) (addr + dev->iobase)); 284 } 285 286 static inline void 287 OUTW(struct eth_device *dev, int command, u_long addr) 288 { 289 *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command); 290 } 291 292 static inline void 293 OUTL(struct eth_device *dev, int command, u_long addr) 294 { 295 *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command); 296 } 297 298 /* Function: ns8382x_initialize 299 * Description: Retrieves the MAC address of the card, and sets up some 300 * globals required by other routines, and initializes the NIC, making it 301 * ready to send and receive packets. 302 * Side effects: initializes ns8382xs, ready to receive packets. 303 * Returns: int: number of cards found 304 */ 305 306 int 307 ns8382x_initialize(bd_t * bis) 308 { 309 pci_dev_t devno; 310 int card_number = 0; 311 struct eth_device *dev; 312 u32 iobase, status; 313 int i, idx = 0; 314 u32 phyAddress; 315 u32 tmp; 316 u32 chip_config; 317 318 while (1) { /* Find PCI device(s) */ 319 if ((devno = pci_find_devices(supported, idx++)) < 0) 320 break; 321 322 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase); 323 iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */ 324 325 debug("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase); 326 327 pci_write_config_dword(devno, PCI_COMMAND, 328 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 329 330 /* Check if I/O accesses and Bus Mastering are enabled. */ 331 pci_read_config_dword(devno, PCI_COMMAND, &status); 332 if (!(status & PCI_COMMAND_MEMORY)) { 333 printf("Error: Can not enable MEM access.\n"); 334 continue; 335 } else if (!(status & PCI_COMMAND_MASTER)) { 336 printf("Error: Can not enable Bus Mastering.\n"); 337 continue; 338 } 339 340 dev = (struct eth_device *) malloc(sizeof *dev); 341 if (!dev) { 342 printf("ns8382x: Can not allocate memory\n"); 343 break; 344 } 345 memset(dev, 0, sizeof(*dev)); 346 347 sprintf(dev->name, "dp8382x#%d", card_number); 348 dev->iobase = bus_to_phys(iobase); 349 dev->priv = (void *) devno; 350 dev->init = ns8382x_init; 351 dev->halt = ns8382x_disable; 352 dev->send = ns8382x_send; 353 dev->recv = ns8382x_poll; 354 355 /* ns8382x has a non-standard PM control register 356 * in PCI config space. Some boards apparently need 357 * to be brought to D0 in this manner. */ 358 pci_read_config_dword(devno, PCIPM, &tmp); 359 if (tmp & (0x03 | 0x100)) { /* D0 state, disable PME assertion */ 360 u32 newtmp = tmp & ~(0x03 | 0x100); 361 pci_write_config_dword(devno, PCIPM, newtmp); 362 } 363 364 /* get MAC address */ 365 for (i = 0; i < 3; i++) { 366 u32 data; 367 char *mac = (char *)&dev->enetaddr[i * 2]; 368 369 OUTL(dev, i * 2, RxFilterAddr); 370 data = INL(dev, RxFilterData); 371 *mac++ = data; 372 *mac++ = data >> 8; 373 } 374 /* get PHY address, can't be zero */ 375 for (phyAddress = 1; phyAddress < 32; phyAddress++) { 376 u32 rev, phy1; 377 378 phy1 = mdio_read(dev, phyAddress, PHYIDR1); 379 if (phy1 == 0x2000) { /*check for 83861/91 */ 380 rev = mdio_read(dev, phyAddress, PHYIDR2); 381 if ((rev & ~(0x000f)) == 0x00005c50 || 382 (rev & ~(0x000f)) == 0x00005c60) { 383 debug("phy rev is %x\n", rev); 384 debug("phy address is %x\n", 385 phyAddress); 386 break; 387 } 388 } 389 } 390 391 /* set phy to autonegotiate && advertise everything */ 392 mdio_write(dev, phyAddress, KTCR, 393 (ktcr_adv_1000H | ktcr_adv_1000F)); 394 mdio_write(dev, phyAddress, ANAR, 395 (anar_adv_100F | anar_adv_100H | anar_adv_10H | 396 anar_adv_10F | anar_ieee_8023)); 397 mdio_write(dev, phyAddress, BMCR, 0x0); /*restore */ 398 mdio_write(dev, phyAddress, BMCR, 399 (Bmcr_AutoNegEn | Bmcr_RstAutoNeg)); 400 /* Reset the chip to erase any previous misconfiguration. */ 401 OUTL(dev, (ChipReset), ChipCmd); 402 403 chip_config = INL(dev, ChipConfig); 404 /* reset the phy */ 405 OUTL(dev, (chip_config | PhyRst), ChipConfig); 406 /* power up and initialize transceiver */ 407 OUTL(dev, (chip_config & ~(PhyDis)), ChipConfig); 408 409 mdio_sync(dev, EECtrl); 410 411 { 412 u32 chpcfg = 413 INL(dev, ChipConfig) ^ SpeedStatus_Polarity; 414 415 debug("%s: Transceiver 10%s %s duplex.\n", dev->name, 416 (chpcfg & GigSpeed) ? "00" : (chpcfg & HundSpeed) 417 ? "0" : "", 418 chpcfg & FullDuplex ? "full" : "half"); 419 debug("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name, 420 dev->enetaddr[0], dev->enetaddr[1], 421 dev->enetaddr[2], dev->enetaddr[3], 422 dev->enetaddr[4], dev->enetaddr[5]); 423 } 424 425 /* Disable PME: 426 * The PME bit is initialized from the EEPROM contents. 427 * PCI cards probably have PME disabled, but motherboard 428 * implementations may have PME set to enable WakeOnLan. 429 * With PME set the chip will scan incoming packets but 430 * nothing will be written to memory. */ 431 SavedClkRun = INL(dev, ClkRun); 432 OUTL(dev, SavedClkRun & ~0x100, ClkRun); 433 434 eth_register(dev); 435 436 card_number++; 437 438 pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x60); 439 440 udelay(10 * 1000); 441 } 442 return card_number; 443 } 444 445 /* MII transceiver control section. 446 Read and write MII registers using software-generated serial MDIO 447 protocol. See the MII specifications or DP83840A data sheet for details. 448 449 The maximum data clock rate is 2.5 MHz. To meet minimum timing we 450 must flush writes to the PCI bus with a PCI read. */ 451 #define mdio_delay(mdio_addr) INL(dev, mdio_addr) 452 453 #define MDIO_EnbIn (0) 454 #define MDIO_WRITE0 (MDIO_EnbOutput) 455 #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput) 456 457 /* Generate the preamble required for initial synchronization and 458 a few older transceivers. */ 459 static void 460 mdio_sync(struct eth_device *dev, u32 offset) 461 { 462 int bits = 32; 463 464 /* Establish sync by sending at least 32 logic ones. */ 465 while (--bits >= 0) { 466 OUTL(dev, MDIO_WRITE1, offset); 467 mdio_delay(offset); 468 OUTL(dev, MDIO_WRITE1 | MDIO_ShiftClk, offset); 469 mdio_delay(offset); 470 } 471 } 472 473 static int 474 mdio_read(struct eth_device *dev, int phy_id, int addr) 475 { 476 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | addr; 477 int i, retval = 0; 478 479 /* Shift the read command bits out. */ 480 for (i = 15; i >= 0; i--) { 481 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; 482 483 OUTL(dev, dataval, EECtrl); 484 mdio_delay(EECtrl); 485 OUTL(dev, dataval | MDIO_ShiftClk, EECtrl); 486 mdio_delay(EECtrl); 487 } 488 /* Read the two transition, 16 data, and wire-idle bits. */ 489 for (i = 19; i > 0; i--) { 490 OUTL(dev, MDIO_EnbIn, EECtrl); 491 mdio_delay(EECtrl); 492 retval = 493 (retval << 1) | ((INL(dev, EECtrl) & MDIO_Data) ? 1 : 0); 494 OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl); 495 mdio_delay(EECtrl); 496 } 497 return (retval >> 1) & 0xffff; 498 } 499 500 static void 501 mdio_write(struct eth_device *dev, int phy_id, int addr, int value) 502 { 503 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (addr << 18) | value; 504 int i; 505 506 /* Shift the command bits out. */ 507 for (i = 31; i >= 0; i--) { 508 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0; 509 510 OUTL(dev, dataval, EECtrl); 511 mdio_delay(EECtrl); 512 OUTL(dev, dataval | MDIO_ShiftClk, EECtrl); 513 mdio_delay(EECtrl); 514 } 515 /* Clear out extra bits. */ 516 for (i = 2; i > 0; i--) { 517 OUTL(dev, MDIO_EnbIn, EECtrl); 518 mdio_delay(EECtrl); 519 OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl); 520 mdio_delay(EECtrl); 521 } 522 return; 523 } 524 525 /* Function: ns8382x_init 526 * Description: resets the ethernet controller chip and configures 527 * registers and data structures required for sending and receiving packets. 528 * Arguments: struct eth_device *dev: NIC data structure 529 * returns: int. 530 */ 531 532 static int 533 ns8382x_init(struct eth_device *dev, bd_t * bis) 534 { 535 u32 config; 536 537 ns8382x_reset(dev); 538 539 /* Disable PME: 540 * The PME bit is initialized from the EEPROM contents. 541 * PCI cards probably have PME disabled, but motherboard 542 * implementations may have PME set to enable WakeOnLan. 543 * With PME set the chip will scan incoming packets but 544 * nothing will be written to memory. */ 545 OUTL(dev, SavedClkRun & ~0x100, ClkRun); 546 547 ns8382x_init_rxfilter(dev); 548 ns8382x_init_txd(dev); 549 ns8382x_init_rxd(dev); 550 551 /*set up ChipConfig */ 552 config = INL(dev, ChipConfig); 553 /*turn off 64 bit ops && Ten-bit interface 554 * && big-endian mode && extended status */ 555 config &= ~(TBIEn | Mode1000 | T64En | D64En | M64En | BEMode | PhyDis | ExtStEn); 556 OUTL(dev, config, ChipConfig); 557 558 /* Configure the PCI bus bursts and FIFO thresholds. */ 559 tx_config = TxCarrierIgn | TxHeartIgn | TxAutoPad 560 | TxCollRetry | TxMxdma_1024 | (0x1002); 561 rx_config = RxMxdma_1024 | 0x20; 562 563 debug("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config); 564 debug("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config); 565 566 OUTL(dev, tx_config, TxConfig); 567 OUTL(dev, rx_config, RxConfig); 568 569 /*turn off priority queueing */ 570 OUTL(dev, 0x0, PriQueue); 571 572 ns8382x_check_duplex(dev); 573 ns8382x_set_rx_mode(dev); 574 575 OUTL(dev, (RxOn | TxOn), ChipCmd); 576 return 1; 577 } 578 579 /* Function: ns8382x_reset 580 * Description: soft resets the controller chip 581 * Arguments: struct eth_device *dev: NIC data structure 582 * Returns: void. 583 */ 584 static void 585 ns8382x_reset(struct eth_device *dev) 586 { 587 OUTL(dev, ChipReset, ChipCmd); 588 while (INL(dev, ChipCmd)) 589 /*wait until done */ ; 590 OUTL(dev, 0, IntrMask); 591 OUTL(dev, 0, IntrEnable); 592 } 593 594 /* Function: ns8382x_init_rxfilter 595 * Description: sets receive filter address to our MAC address 596 * Arguments: struct eth_device *dev: NIC data structure 597 * returns: void. 598 */ 599 600 static void 601 ns8382x_init_rxfilter(struct eth_device *dev) 602 { 603 int i; 604 605 for (i = 0; i < ETH_ALEN; i += 2) { 606 OUTL(dev, i, RxFilterAddr); 607 OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8), 608 RxFilterData); 609 } 610 } 611 612 /* Function: ns8382x_init_txd 613 * Description: initializes the Tx descriptor 614 * Arguments: struct eth_device *dev: NIC data structure 615 * returns: void. 616 */ 617 618 static void 619 ns8382x_init_txd(struct eth_device *dev) 620 { 621 txd.link = (u32) 0; 622 txd.bufptr = cpu_to_le32((u32) & txb[0]); 623 txd.cmdsts = (u32) 0; 624 txd.extsts = (u32) 0; 625 626 OUTL(dev, 0x0, TxRingPtrHi); 627 OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr); 628 629 debug("ns8382x_init_txd: TX descriptor register loaded with: %#08X (&txd: %p)\n", 630 INL(dev, TxRingPtr), &txd); 631 } 632 633 /* Function: ns8382x_init_rxd 634 * Description: initializes the Rx descriptor ring 635 * Arguments: struct eth_device *dev: NIC data structure 636 * Returns: void. 637 */ 638 639 static void 640 ns8382x_init_rxd(struct eth_device *dev) 641 { 642 int i; 643 644 OUTL(dev, 0x0, RxRingPtrHi); 645 646 cur_rx = 0; 647 for (i = 0; i < NUM_RX_DESC; i++) { 648 rxd[i].link = 649 cpu_to_le32((i + 1 < 650 NUM_RX_DESC) ? (u32) & rxd[i + 651 1] : (u32) & 652 rxd[0]); 653 rxd[i].extsts = cpu_to_le32((u32) 0x0); 654 rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE); 655 rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]); 656 657 debug 658 ("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n", 659 i, &rxd[i], le32_to_cpu(rxd[i].link), 660 le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr)); 661 } 662 OUTL(dev, phys_to_bus((u32) & rxd), RxRingPtr); 663 664 debug("ns8382x_init_rxd: RX descriptor register loaded with: %X\n", 665 INL(dev, RxRingPtr)); 666 } 667 668 /* Function: ns8382x_set_rx_mode 669 * Description: 670 * sets the receive mode to accept all broadcast packets and packets 671 * with our MAC address, and reject all multicast packets. 672 * Arguments: struct eth_device *dev: NIC data structure 673 * Returns: void. 674 */ 675 676 static void 677 ns8382x_set_rx_mode(struct eth_device *dev) 678 { 679 u32 rx_mode = 0x0; 680 /*spec says RxFilterEnable has to be 0 for rest of 681 * this stuff to be properly configured. Linux driver 682 * seems to support this*/ 683 /* OUTL(dev, rx_mode, RxFilterAddr);*/ 684 rx_mode = (RxFilterEnable | AcceptAllBroadcast | AcceptPerfectMatch); 685 OUTL(dev, rx_mode, RxFilterAddr); 686 printf("ns8382x_set_rx_mode: set to %X\n", rx_mode); 687 /*now we turn RxFilterEnable back on */ 688 /*rx_mode |= RxFilterEnable; 689 OUTL(dev, rx_mode, RxFilterAddr);*/ 690 } 691 692 static void 693 ns8382x_check_duplex(struct eth_device *dev) 694 { 695 int gig = 0; 696 int hun = 0; 697 int duplex = 0; 698 int config = (INL(dev, ChipConfig) ^ SpeedStatus_Polarity); 699 700 duplex = (config & FullDuplex) ? 1 : 0; 701 gig = (config & GigSpeed) ? 1 : 0; 702 hun = (config & HundSpeed) ? 1 : 0; 703 704 debug("%s: Setting 10%s %s-duplex based on negotiated link" 705 " capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "", 706 duplex ? "full" : "half"); 707 708 if (duplex) { 709 rx_config |= RxAcceptTx; 710 tx_config |= (TxCarrierIgn | TxHeartIgn); 711 } else { 712 rx_config &= ~RxAcceptTx; 713 tx_config &= ~(TxCarrierIgn | TxHeartIgn); 714 } 715 716 debug("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config); 717 debug("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config); 718 719 OUTL(dev, tx_config, TxConfig); 720 OUTL(dev, rx_config, RxConfig); 721 722 /*if speed is 10 or 100, remove MODE1000, 723 * if it's 1000, then set it */ 724 config = INL(dev, ChipConfig); 725 if (gig) 726 config |= Mode1000; 727 else 728 config &= ~Mode1000; 729 730 debug("%s: %setting Mode1000\n", dev->name, (gig) ? "S" : "Uns"); 731 732 OUTL(dev, config, ChipConfig); 733 } 734 735 /* Function: ns8382x_send 736 * Description: transmits a packet and waits for completion or timeout. 737 * Returns: void. */ 738 static int 739 ns8382x_send(struct eth_device *dev, volatile void *packet, int length) 740 { 741 u32 i, status = 0; 742 vu_long tx_stat = 0; 743 744 /* Stop the transmitter */ 745 OUTL(dev, TxOff, ChipCmd); 746 747 debug("ns8382x_send: sending %d bytes\n", (int)length); 748 749 /* set the transmit buffer descriptor and enable Transmit State Machine */ 750 txd.link = cpu_to_le32(0x0); 751 txd.bufptr = cpu_to_le32(phys_to_bus((u32)packet)); 752 txd.extsts = cpu_to_le32(0x0); 753 txd.cmdsts = cpu_to_le32(DescOwn | length); 754 755 /* load Transmit Descriptor Register */ 756 OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr); 757 758 debug("ns8382x_send: TX descriptor register loaded with: %#08X\n", 759 INL(dev, TxRingPtr)); 760 debug("\ttxd.link:%X\tbufp:%X\texsts:%X\tcmdsts:%X\n", 761 le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr), 762 le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts)); 763 764 /* restart the transmitter */ 765 OUTL(dev, TxOn, ChipCmd); 766 767 for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) { 768 if (i >= TOUT_LOOP) { 769 printf ("%s: tx error buffer not ready: txd.cmdsts %#lX\n", 770 dev->name, tx_stat); 771 goto Done; 772 } 773 } 774 775 if (!(tx_stat & DescPktOK)) { 776 printf("ns8382x_send: Transmit error, Tx status %lX.\n", tx_stat); 777 goto Done; 778 } 779 780 debug("ns8382x_send: tx_stat: %#08lX\n", tx_stat); 781 782 status = 1; 783 Done: 784 return status; 785 } 786 787 /* Function: ns8382x_poll 788 * Description: checks for a received packet and returns it if found. 789 * Arguments: struct eth_device *dev: NIC data structure 790 * Returns: 1 if packet was received. 791 * 0 if no packet was received. 792 * Side effects: 793 * Returns (copies) the packet to the array dev->packet. 794 * Returns the length of the packet. 795 */ 796 797 static int 798 ns8382x_poll(struct eth_device *dev) 799 { 800 int retstat = 0; 801 int length = 0; 802 vu_long rx_status = le32_to_cpu(rxd[cur_rx].cmdsts); 803 804 if (!(rx_status & (u32) DescOwn)) 805 return retstat; 806 807 debug("ns8382x_poll: got a packet: cur_rx:%u, status:%lx\n", 808 cur_rx, rx_status); 809 810 length = (rx_status & DSIZE) - CRC_SIZE; 811 812 if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) { 813 /* corrupted packet received */ 814 printf("ns8382x_poll: Corrupted packet, status:%lx\n", rx_status); 815 retstat = 0; 816 } else { 817 /* give packet to higher level routine */ 818 NetReceive((rxb + cur_rx * RX_BUF_SIZE), length); 819 retstat = 1; 820 } 821 822 /* return the descriptor and buffer to receive ring */ 823 rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE); 824 rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]); 825 826 if (++cur_rx == NUM_RX_DESC) 827 cur_rx = 0; 828 829 /* re-enable the potentially idle receive state machine */ 830 OUTL(dev, RxOn, ChipCmd); 831 832 return retstat; 833 } 834 835 /* Function: ns8382x_disable 836 * Description: Turns off interrupts and stops Tx and Rx engines 837 * Arguments: struct eth_device *dev: NIC data structure 838 * Returns: void. 839 */ 840 841 static void 842 ns8382x_disable(struct eth_device *dev) 843 { 844 /* Disable interrupts using the mask. */ 845 OUTL(dev, 0, IntrMask); 846 OUTL(dev, 0, IntrEnable); 847 848 /* Stop the chip's Tx and Rx processes. */ 849 OUTL(dev, (RxOff | TxOff), ChipCmd); 850 851 /* Restore PME enable bit */ 852 OUTL(dev, SavedClkRun, ClkRun); 853 } 854