1 /* 2 Ported to U-Boot by Christian Pellegrin <chri@ascensit.com> 3 4 Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and 5 eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world 6 are GPL, so this is, of course, GPL. 7 8 9 ========================================================================== 10 11 dev/dp83902a.h 12 13 National Semiconductor DP83902a ethernet chip 14 15 ========================================================================== 16 ####ECOSGPLCOPYRIGHTBEGIN#### 17 ------------------------------------------- 18 This file is part of eCos, the Embedded Configurable Operating System. 19 Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. 20 21 eCos is free software; you can redistribute it and/or modify it under 22 the terms of the GNU General Public License as published by the Free 23 Software Foundation; either version 2 or (at your option) any later version. 24 25 eCos is distributed in the hope that it will be useful, but WITHOUT ANY 26 WARRANTY; without even the implied warranty of MERCHANTABILITY or 27 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 28 for more details. 29 30 You should have received a copy of the GNU General Public License along 31 with eCos; if not, write to the Free Software Foundation, Inc., 32 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. 33 34 As a special exception, if other files instantiate templates or use macros 35 or inline functions from this file, or you compile this file and link it 36 with other works to produce a work based on this file, this file does not 37 by itself cause the resulting work to be covered by the GNU General Public 38 License. However the source code for this file must still be made available 39 in accordance with section (3) of the GNU General Public License. 40 41 This exception does not invalidate any other reasons why a work based on 42 this file might be covered by the GNU General Public License. 43 44 Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. 45 at http://sources.redhat.com/ecos/ecos-license/ 46 ------------------------------------------- 47 ####ECOSGPLCOPYRIGHTEND#### 48 ####BSDCOPYRIGHTBEGIN#### 49 50 ------------------------------------------- 51 52 Portions of this software may have been derived from OpenBSD or other sources, 53 and are covered by the appropriate copyright disclaimers included herein. 54 55 ------------------------------------------- 56 57 ####BSDCOPYRIGHTEND#### 58 ========================================================================== 59 #####DESCRIPTIONBEGIN#### 60 61 Author(s): gthomas 62 Contributors: gthomas, jskov 63 Date: 2001-06-13 64 Purpose: 65 Description: 66 67 ####DESCRIPTIONEND#### 68 69 ========================================================================== 70 71 */ 72 73 /* 74 ------------------------------------------------------------------------ 75 Macros for accessing DP registers 76 These can be overridden by the platform header 77 */ 78 79 #ifndef __NE2000_BASE_H__ 80 #define __NE2000_BASE_H__ 81 82 /* 83 * Debugging details 84 * 85 * Set to perms of: 86 * 0 disables all debug output 87 * 1 for process debug output 88 * 2 for added data IO output: get_reg, put_reg 89 * 4 for packet allocation/free output 90 * 8 for only startup status, so we can tell we're installed OK 91 */ 92 #if 0 93 #define DEBUG 0xf 94 #else 95 #define DEBUG 0 96 #endif 97 98 #if DEBUG & 1 99 #define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0) 100 #define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0) 101 #define PRINTK(args...) printf(args) 102 #else 103 #define DEBUG_FUNCTION() do {} while(0) 104 #define DEBUG_LINE() do {} while(0) 105 #define PRINTK(args...) 106 #endif 107 108 /* timeout for tx/rx in s */ 109 #define TOUT 5 110 /* Ether MAC address size */ 111 #define ETHER_ADDR_LEN 6 112 113 114 #define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1 115 #define CYGACC_CALL_IF_DELAY_US(X) udelay(X) 116 117 /* H/W infomation struct */ 118 typedef struct hw_info_t { 119 u32 offset; 120 u8 a0, a1, a2; 121 u32 flags; 122 } hw_info_t; 123 124 typedef struct dp83902a_priv_data { 125 u8* base; 126 u8* data; 127 u8* reset; 128 int tx_next; /* First free Tx page */ 129 int tx_int; /* Expecting interrupt from this buffer */ 130 int rx_next; /* First free Rx page */ 131 int tx1, tx2; /* Page numbers for Tx buffers */ 132 u32 tx1_key, tx2_key; /* Used to ack when packet sent */ 133 int tx1_len, tx2_len; 134 bool tx_started, running, hardwired_esa; 135 u8 esa[6]; 136 void* plf_priv; 137 138 /* Buffer allocation */ 139 int tx_buf1, tx_buf2; 140 int rx_buf_start, rx_buf_end; 141 } dp83902a_priv_data_t; 142 143 /* ------------------------------------------------------------------------ */ 144 /* Register offsets */ 145 146 #define DP_CR 0x00 147 #define DP_CLDA0 0x01 148 #define DP_PSTART 0x01 /* write */ 149 #define DP_CLDA1 0x02 150 #define DP_PSTOP 0x02 /* write */ 151 #define DP_BNDRY 0x03 152 #define DP_TSR 0x04 153 #define DP_TPSR 0x04 /* write */ 154 #define DP_NCR 0x05 155 #define DP_TBCL 0x05 /* write */ 156 #define DP_FIFO 0x06 157 #define DP_TBCH 0x06 /* write */ 158 #define DP_ISR 0x07 159 #define DP_CRDA0 0x08 160 #define DP_RSAL 0x08 /* write */ 161 #define DP_CRDA1 0x09 162 #define DP_RSAH 0x09 /* write */ 163 #define DP_RBCL 0x0a /* write */ 164 #define DP_RBCH 0x0b /* write */ 165 #define DP_RSR 0x0c 166 #define DP_RCR 0x0c /* write */ 167 #define DP_FER 0x0d 168 #define DP_TCR 0x0d /* write */ 169 #define DP_CER 0x0e 170 #define DP_DCR 0x0e /* write */ 171 #define DP_MISSED 0x0f 172 #define DP_IMR 0x0f /* write */ 173 #define DP_DATAPORT 0x10 /* "eprom" data port */ 174 175 #define DP_P1_CR 0x00 176 #define DP_P1_PAR0 0x01 177 #define DP_P1_PAR1 0x02 178 #define DP_P1_PAR2 0x03 179 #define DP_P1_PAR3 0x04 180 #define DP_P1_PAR4 0x05 181 #define DP_P1_PAR5 0x06 182 #define DP_P1_CURP 0x07 183 #define DP_P1_MAR0 0x08 184 #define DP_P1_MAR1 0x09 185 #define DP_P1_MAR2 0x0a 186 #define DP_P1_MAR3 0x0b 187 #define DP_P1_MAR4 0x0c 188 #define DP_P1_MAR5 0x0d 189 #define DP_P1_MAR6 0x0e 190 #define DP_P1_MAR7 0x0f 191 192 #define DP_P2_CR 0x00 193 #define DP_P2_PSTART 0x01 194 #define DP_P2_CLDA0 0x01 /* write */ 195 #define DP_P2_PSTOP 0x02 196 #define DP_P2_CLDA1 0x02 /* write */ 197 #define DP_P2_RNPP 0x03 198 #define DP_P2_TPSR 0x04 199 #define DP_P2_LNPP 0x05 200 #define DP_P2_ACH 0x06 201 #define DP_P2_ACL 0x07 202 #define DP_P2_RCR 0x0c 203 #define DP_P2_TCR 0x0d 204 #define DP_P2_DCR 0x0e 205 #define DP_P2_IMR 0x0f 206 207 /* Command register - common to all pages */ 208 209 #define DP_CR_STOP 0x01 /* Stop: software reset */ 210 #define DP_CR_START 0x02 /* Start: initialize device */ 211 #define DP_CR_TXPKT 0x04 /* Transmit packet */ 212 #define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */ 213 #define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */ 214 #define DP_CR_SEND 0x18 /* Send packet */ 215 #define DP_CR_NODMA 0x20 /* Remote (or no) DMA */ 216 #define DP_CR_PAGE0 0x00 /* Page select */ 217 #define DP_CR_PAGE1 0x40 218 #define DP_CR_PAGE2 0x80 219 #define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */ 220 221 /* Data configuration register */ 222 223 #define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */ 224 #define DP_DCR_BOS 0x02 /* 1=Little Endian */ 225 #define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */ 226 #define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */ 227 #define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */ 228 #define DP_DCR_FIFO_1 0x00 /* FIFO threshold */ 229 #define DP_DCR_FIFO_2 0x20 230 #define DP_DCR_FIFO_4 0x40 231 #define DP_DCR_FIFO_6 0x60 232 233 #define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4) 234 235 /* Interrupt status register */ 236 237 #define DP_ISR_RxP 0x01 /* Packet received */ 238 #define DP_ISR_TxP 0x02 /* Packet transmitted */ 239 #define DP_ISR_RxE 0x04 /* Receive error */ 240 #define DP_ISR_TxE 0x08 /* Transmit error */ 241 #define DP_ISR_OFLW 0x10 /* Receive overflow */ 242 #define DP_ISR_CNT 0x20 /* Tally counters need emptying */ 243 #define DP_ISR_RDC 0x40 /* Remote DMA complete */ 244 #define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */ 245 246 /* Interrupt mask register */ 247 248 #define DP_IMR_RxP 0x01 /* Packet received */ 249 #define DP_IMR_TxP 0x02 /* Packet transmitted */ 250 #define DP_IMR_RxE 0x04 /* Receive error */ 251 #define DP_IMR_TxE 0x08 /* Transmit error */ 252 #define DP_IMR_OFLW 0x10 /* Receive overflow */ 253 #define DP_IMR_CNT 0x20 /* Tall counters need emptying */ 254 #define DP_IMR_RDC 0x40 /* Remote DMA complete */ 255 256 #define DP_IMR_All 0x3F /* Everything but remote DMA */ 257 258 /* Receiver control register */ 259 260 #define DP_RCR_SEP 0x01 /* Save bad(error) packets */ 261 #define DP_RCR_AR 0x02 /* Accept runt packets */ 262 #define DP_RCR_AB 0x04 /* Accept broadcast packets */ 263 #define DP_RCR_AM 0x08 /* Accept multicast packets */ 264 #define DP_RCR_PROM 0x10 /* Promiscuous mode */ 265 #define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */ 266 267 /* Receiver status register */ 268 269 #define DP_RSR_RxP 0x01 /* Packet received */ 270 #define DP_RSR_CRC 0x02 /* CRC error */ 271 #define DP_RSR_FRAME 0x04 /* Framing error */ 272 #define DP_RSR_FO 0x08 /* FIFO overrun */ 273 #define DP_RSR_MISS 0x10 /* Missed packet */ 274 #define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */ 275 #define DP_RSR_DIS 0x40 /* Receiver disabled */ 276 #define DP_RSR_DFR 0x80 /* Receiver processing deferred */ 277 278 /* Transmitter control register */ 279 280 #define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */ 281 #define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */ 282 #define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */ 283 #define DP_TCR_INLOOP 0x04 /* Full internal loopback */ 284 #define DP_TCR_OUTLOOP 0x08 /* External loopback */ 285 #define DP_TCR_ATD 0x10 /* Auto transmit disable */ 286 #define DP_TCR_OFFSET 0x20 /* Collision offset adjust */ 287 288 /* Transmit status register */ 289 290 #define DP_TSR_TxP 0x01 /* Packet transmitted */ 291 #define DP_TSR_COL 0x04 /* Collision (at least one) */ 292 #define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */ 293 #define DP_TSR_CRS 0x10 /* Lost carrier */ 294 #define DP_TSR_FU 0x20 /* FIFO underrun */ 295 #define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */ 296 #define DP_TSR_OWC 0x80 /* Collision outside normal window */ 297 298 #define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */ 299 #define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */ 300 301 /* Functions */ 302 int get_prom(u8* mac_addr, u8* base_addr); 303 304 #endif /* __NE2000_BASE_H__ */ 305