1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 4 * 5 * U-Boot version: 6 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 7 * 8 * Based on the Linux version which is: 9 * Copyright (C) 2012 Marvell 10 * 11 * Rami Rosen <rosenr@marvell.com> 12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 13 */ 14 15 #include <common.h> 16 #include <dm.h> 17 #include <net.h> 18 #include <netdev.h> 19 #include <config.h> 20 #include <malloc.h> 21 #include <asm/io.h> 22 #include <linux/errno.h> 23 #include <phy.h> 24 #include <miiphy.h> 25 #include <watchdog.h> 26 #include <asm/arch/cpu.h> 27 #include <asm/arch/soc.h> 28 #include <linux/compat.h> 29 #include <linux/mbus.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 #if !defined(CONFIG_PHYLIB) 34 # error Marvell mvneta requires PHYLIB 35 #endif 36 37 #define CONFIG_NR_CPUS 1 38 #define ETH_HLEN 14 /* Total octets in header */ 39 40 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */ 41 #define WRAP (2 + ETH_HLEN + 4 + 32) 42 #define MTU 1500 43 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN)) 44 45 #define MVNETA_SMI_TIMEOUT 10000 46 47 /* Registers */ 48 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 49 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) 50 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 51 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 52 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 53 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 54 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 55 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 56 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 57 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 58 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 59 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 60 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 61 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 62 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 63 #define MVNETA_PORT_RX_RESET 0x1cc0 64 #define MVNETA_PORT_RX_DMA_RESET BIT(0) 65 #define MVNETA_PHY_ADDR 0x2000 66 #define MVNETA_PHY_ADDR_MASK 0x1f 67 #define MVNETA_SMI 0x2004 68 #define MVNETA_PHY_REG_MASK 0x1f 69 /* SMI register fields */ 70 #define MVNETA_SMI_DATA_OFFS 0 /* Data */ 71 #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS) 72 #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ 73 #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/ 74 #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ 75 #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS) 76 #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */ 77 #define MVNETA_SMI_BUSY (1 << 28) /* Busy */ 78 #define MVNETA_MBUS_RETRY 0x2010 79 #define MVNETA_UNIT_INTR_CAUSE 0x2080 80 #define MVNETA_UNIT_CONTROL 0x20B0 81 #define MVNETA_PHY_POLLING_ENABLE BIT(1) 82 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 83 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 84 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 85 #define MVNETA_WIN_SIZE_MASK (0xffff0000) 86 #define MVNETA_BASE_ADDR_ENABLE 0x2290 87 #define MVNETA_BASE_ADDR_ENABLE_BIT 0x1 88 #define MVNETA_PORT_ACCESS_PROTECT 0x2294 89 #define MVNETA_PORT_ACCESS_PROTECT_WIN0_RW 0x3 90 #define MVNETA_PORT_CONFIG 0x2400 91 #define MVNETA_UNI_PROMISC_MODE BIT(0) 92 #define MVNETA_DEF_RXQ(q) ((q) << 1) 93 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 94 #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 95 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 96 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 97 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 98 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 99 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 100 MVNETA_DEF_RXQ_ARP(q) | \ 101 MVNETA_DEF_RXQ_TCP(q) | \ 102 MVNETA_DEF_RXQ_UDP(q) | \ 103 MVNETA_DEF_RXQ_BPDU(q) | \ 104 MVNETA_TX_UNSET_ERR_SUM | \ 105 MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 106 #define MVNETA_PORT_CONFIG_EXTEND 0x2404 107 #define MVNETA_MAC_ADDR_LOW 0x2414 108 #define MVNETA_MAC_ADDR_HIGH 0x2418 109 #define MVNETA_SDMA_CONFIG 0x241c 110 #define MVNETA_SDMA_BRST_SIZE_16 4 111 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 112 #define MVNETA_RX_NO_DATA_SWAP BIT(4) 113 #define MVNETA_TX_NO_DATA_SWAP BIT(5) 114 #define MVNETA_DESC_SWAP BIT(6) 115 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 116 #define MVNETA_PORT_STATUS 0x2444 117 #define MVNETA_TX_IN_PRGRS BIT(1) 118 #define MVNETA_TX_FIFO_EMPTY BIT(8) 119 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 120 #define MVNETA_SERDES_CFG 0x24A0 121 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 122 #define MVNETA_QSGMII_SERDES_PROTO 0x0667 123 #define MVNETA_TYPE_PRIO 0x24bc 124 #define MVNETA_FORCE_UNI BIT(21) 125 #define MVNETA_TXQ_CMD_1 0x24e4 126 #define MVNETA_TXQ_CMD 0x2448 127 #define MVNETA_TXQ_DISABLE_SHIFT 8 128 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 129 #define MVNETA_ACC_MODE 0x2500 130 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 131 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 132 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 133 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 134 135 /* Exception Interrupt Port/Queue Cause register */ 136 137 #define MVNETA_INTR_NEW_CAUSE 0x25a0 138 #define MVNETA_INTR_NEW_MASK 0x25a4 139 140 /* bits 0..7 = TXQ SENT, one bit per queue. 141 * bits 8..15 = RXQ OCCUP, one bit per queue. 142 * bits 16..23 = RXQ FREE, one bit per queue. 143 * bit 29 = OLD_REG_SUM, see old reg ? 144 * bit 30 = TX_ERR_SUM, one bit for 4 ports 145 * bit 31 = MISC_SUM, one bit for 4 ports 146 */ 147 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 148 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 149 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 150 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 151 152 #define MVNETA_INTR_OLD_CAUSE 0x25a8 153 #define MVNETA_INTR_OLD_MASK 0x25ac 154 155 /* Data Path Port/Queue Cause Register */ 156 #define MVNETA_INTR_MISC_CAUSE 0x25b0 157 #define MVNETA_INTR_MISC_MASK 0x25b4 158 #define MVNETA_INTR_ENABLE 0x25b8 159 160 #define MVNETA_RXQ_CMD 0x2680 161 #define MVNETA_RXQ_DISABLE_SHIFT 8 162 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 163 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 164 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 165 #define MVNETA_GMAC_CTRL_0 0x2c00 166 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 167 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 168 #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 169 #define MVNETA_GMAC_CTRL_2 0x2c08 170 #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 171 #define MVNETA_GMAC2_PORT_RGMII BIT(4) 172 #define MVNETA_GMAC2_PORT_RESET BIT(6) 173 #define MVNETA_GMAC_STATUS 0x2c10 174 #define MVNETA_GMAC_LINK_UP BIT(0) 175 #define MVNETA_GMAC_SPEED_1000 BIT(1) 176 #define MVNETA_GMAC_SPEED_100 BIT(2) 177 #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 178 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 179 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 180 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 181 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 182 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 183 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 184 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 185 #define MVNETA_GMAC_FORCE_LINK_UP (BIT(0) | BIT(1)) 186 #define MVNETA_GMAC_IB_BYPASS_AN_EN BIT(3) 187 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 188 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 189 #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 190 #define MVNETA_GMAC_SET_FC_EN BIT(8) 191 #define MVNETA_GMAC_ADVERT_FC_EN BIT(9) 192 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 193 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 194 #define MVNETA_GMAC_SAMPLE_TX_CFG_EN BIT(15) 195 #define MVNETA_MIB_COUNTERS_BASE 0x3080 196 #define MVNETA_MIB_LATE_COLLISION 0x7c 197 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 198 #define MVNETA_DA_FILT_OTH_MCAST 0x3500 199 #define MVNETA_DA_FILT_UCAST_BASE 0x3600 200 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 201 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 202 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 203 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 204 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 205 #define MVNETA_TXQ_DEC_SENT_SHIFT 16 206 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 207 #define MVNETA_TXQ_SENT_DESC_SHIFT 16 208 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 209 #define MVNETA_PORT_TX_RESET 0x3cf0 210 #define MVNETA_PORT_TX_DMA_RESET BIT(0) 211 #define MVNETA_TX_MTU 0x3e0c 212 #define MVNETA_TX_TOKEN_SIZE 0x3e14 213 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 214 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 215 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 216 217 /* Descriptor ring Macros */ 218 #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 219 (((index) < (q)->last_desc) ? ((index) + 1) : 0) 220 221 /* Various constants */ 222 223 /* Coalescing */ 224 #define MVNETA_TXDONE_COAL_PKTS 16 225 #define MVNETA_RX_COAL_PKTS 32 226 #define MVNETA_RX_COAL_USEC 100 227 228 /* The two bytes Marvell header. Either contains a special value used 229 * by Marvell switches when a specific hardware mode is enabled (not 230 * supported by this driver) or is filled automatically by zeroes on 231 * the RX side. Those two bytes being at the front of the Ethernet 232 * header, they allow to have the IP header aligned on a 4 bytes 233 * boundary automatically: the hardware skips those two bytes on its 234 * own. 235 */ 236 #define MVNETA_MH_SIZE 2 237 238 #define MVNETA_VLAN_TAG_LEN 4 239 240 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 241 #define MVNETA_TX_CSUM_MAX_SIZE 9800 242 #define MVNETA_ACC_MODE_EXT 1 243 244 /* Timeout constants */ 245 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 246 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 247 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 248 249 #define MVNETA_TX_MTU_MAX 0x3ffff 250 251 /* Max number of Rx descriptors */ 252 #define MVNETA_MAX_RXD 16 253 254 /* Max number of Tx descriptors */ 255 #define MVNETA_MAX_TXD 16 256 257 /* descriptor aligned size */ 258 #define MVNETA_DESC_ALIGNED_SIZE 32 259 260 struct mvneta_port { 261 void __iomem *base; 262 struct mvneta_rx_queue *rxqs; 263 struct mvneta_tx_queue *txqs; 264 265 u8 mcast_count[256]; 266 u16 tx_ring_size; 267 u16 rx_ring_size; 268 269 phy_interface_t phy_interface; 270 unsigned int link; 271 unsigned int duplex; 272 unsigned int speed; 273 274 int init; 275 int phyaddr; 276 struct phy_device *phydev; 277 struct mii_dev *bus; 278 }; 279 280 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 281 * layout of the transmit and reception DMA descriptors, and their 282 * layout is therefore defined by the hardware design 283 */ 284 285 #define MVNETA_TX_L3_OFF_SHIFT 0 286 #define MVNETA_TX_IP_HLEN_SHIFT 8 287 #define MVNETA_TX_L4_UDP BIT(16) 288 #define MVNETA_TX_L3_IP6 BIT(17) 289 #define MVNETA_TXD_IP_CSUM BIT(18) 290 #define MVNETA_TXD_Z_PAD BIT(19) 291 #define MVNETA_TXD_L_DESC BIT(20) 292 #define MVNETA_TXD_F_DESC BIT(21) 293 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 294 MVNETA_TXD_L_DESC | \ 295 MVNETA_TXD_F_DESC) 296 #define MVNETA_TX_L4_CSUM_FULL BIT(30) 297 #define MVNETA_TX_L4_CSUM_NOT BIT(31) 298 299 #define MVNETA_RXD_ERR_CRC 0x0 300 #define MVNETA_RXD_ERR_SUMMARY BIT(16) 301 #define MVNETA_RXD_ERR_OVERRUN BIT(17) 302 #define MVNETA_RXD_ERR_LEN BIT(18) 303 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 304 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 305 #define MVNETA_RXD_L3_IP4 BIT(25) 306 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) 307 #define MVNETA_RXD_L4_CSUM_OK BIT(30) 308 309 struct mvneta_tx_desc { 310 u32 command; /* Options used by HW for packet transmitting.*/ 311 u16 reserverd1; /* csum_l4 (for future use) */ 312 u16 data_size; /* Data size of transmitted packet in bytes */ 313 u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 314 u32 reserved2; /* hw_cmd - (for future use, PMT) */ 315 u32 reserved3[4]; /* Reserved - (for future use) */ 316 }; 317 318 struct mvneta_rx_desc { 319 u32 status; /* Info about received packet */ 320 u16 reserved1; /* pnc_info - (for future use, PnC) */ 321 u16 data_size; /* Size of received packet in bytes */ 322 323 u32 buf_phys_addr; /* Physical address of the buffer */ 324 u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 325 326 u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 327 u16 reserved3; /* prefetch_cmd, for future use */ 328 u16 reserved4; /* csum_l4 - (for future use, PnC) */ 329 330 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 331 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 332 }; 333 334 struct mvneta_tx_queue { 335 /* Number of this TX queue, in the range 0-7 */ 336 u8 id; 337 338 /* Number of TX DMA descriptors in the descriptor ring */ 339 int size; 340 341 /* Index of last TX DMA descriptor that was inserted */ 342 int txq_put_index; 343 344 /* Index of the TX DMA descriptor to be cleaned up */ 345 int txq_get_index; 346 347 /* Virtual address of the TX DMA descriptors array */ 348 struct mvneta_tx_desc *descs; 349 350 /* DMA address of the TX DMA descriptors array */ 351 dma_addr_t descs_phys; 352 353 /* Index of the last TX DMA descriptor */ 354 int last_desc; 355 356 /* Index of the next TX DMA descriptor to process */ 357 int next_desc_to_proc; 358 }; 359 360 struct mvneta_rx_queue { 361 /* rx queue number, in the range 0-7 */ 362 u8 id; 363 364 /* num of rx descriptors in the rx descriptor ring */ 365 int size; 366 367 /* Virtual address of the RX DMA descriptors array */ 368 struct mvneta_rx_desc *descs; 369 370 /* DMA address of the RX DMA descriptors array */ 371 dma_addr_t descs_phys; 372 373 /* Index of the last RX DMA descriptor */ 374 int last_desc; 375 376 /* Index of the next RX DMA descriptor to process */ 377 int next_desc_to_proc; 378 }; 379 380 /* U-Boot doesn't use the queues, so set the number to 1 */ 381 static int rxq_number = 1; 382 static int txq_number = 1; 383 static int rxq_def; 384 385 struct buffer_location { 386 struct mvneta_tx_desc *tx_descs; 387 struct mvneta_rx_desc *rx_descs; 388 u32 rx_buffers; 389 }; 390 391 /* 392 * All 4 interfaces use the same global buffer, since only one interface 393 * can be enabled at once 394 */ 395 static struct buffer_location buffer_loc; 396 397 /* 398 * Page table entries are set to 1MB, or multiples of 1MB 399 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 400 */ 401 #define BD_SPACE (1 << 20) 402 403 /* 404 * Dummy implementation that can be overwritten by a board 405 * specific function 406 */ 407 __weak int board_network_enable(struct mii_dev *bus) 408 { 409 return 0; 410 } 411 412 /* Utility/helper methods */ 413 414 /* Write helper method */ 415 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 416 { 417 writel(data, pp->base + offset); 418 } 419 420 /* Read helper method */ 421 static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 422 { 423 return readl(pp->base + offset); 424 } 425 426 /* Clear all MIB counters */ 427 static void mvneta_mib_counters_clear(struct mvneta_port *pp) 428 { 429 int i; 430 431 /* Perform dummy reads from MIB counters */ 432 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 433 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 434 } 435 436 /* Rx descriptors helper methods */ 437 438 /* Checks whether the RX descriptor having this status is both the first 439 * and the last descriptor for the RX packet. Each RX packet is currently 440 * received through a single RX descriptor, so not having each RX 441 * descriptor with its first and last bits set is an error 442 */ 443 static int mvneta_rxq_desc_is_first_last(u32 status) 444 { 445 return (status & MVNETA_RXD_FIRST_LAST_DESC) == 446 MVNETA_RXD_FIRST_LAST_DESC; 447 } 448 449 /* Add number of descriptors ready to receive new packets */ 450 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 451 struct mvneta_rx_queue *rxq, 452 int ndescs) 453 { 454 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 455 * be added at once 456 */ 457 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 458 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 459 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 460 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 461 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 462 } 463 464 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 465 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 466 } 467 468 /* Get number of RX descriptors occupied by received packets */ 469 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 470 struct mvneta_rx_queue *rxq) 471 { 472 u32 val; 473 474 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 475 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 476 } 477 478 /* Update num of rx desc called upon return from rx path or 479 * from mvneta_rxq_drop_pkts(). 480 */ 481 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 482 struct mvneta_rx_queue *rxq, 483 int rx_done, int rx_filled) 484 { 485 u32 val; 486 487 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 488 val = rx_done | 489 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 490 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 491 return; 492 } 493 494 /* Only 255 descriptors can be added at once */ 495 while ((rx_done > 0) || (rx_filled > 0)) { 496 if (rx_done <= 0xff) { 497 val = rx_done; 498 rx_done = 0; 499 } else { 500 val = 0xff; 501 rx_done -= 0xff; 502 } 503 if (rx_filled <= 0xff) { 504 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 505 rx_filled = 0; 506 } else { 507 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 508 rx_filled -= 0xff; 509 } 510 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 511 } 512 } 513 514 /* Get pointer to next RX descriptor to be processed by SW */ 515 static struct mvneta_rx_desc * 516 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 517 { 518 int rx_desc = rxq->next_desc_to_proc; 519 520 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 521 return rxq->descs + rx_desc; 522 } 523 524 /* Tx descriptors helper methods */ 525 526 /* Update HW with number of TX descriptors to be sent */ 527 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 528 struct mvneta_tx_queue *txq, 529 int pend_desc) 530 { 531 u32 val; 532 533 /* Only 255 descriptors can be added at once ; Assume caller 534 * process TX descriptors in quanta less than 256 535 */ 536 val = pend_desc; 537 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 538 } 539 540 /* Get pointer to next TX descriptor to be processed (send) by HW */ 541 static struct mvneta_tx_desc * 542 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 543 { 544 int tx_desc = txq->next_desc_to_proc; 545 546 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 547 return txq->descs + tx_desc; 548 } 549 550 /* Set rxq buf size */ 551 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 552 struct mvneta_rx_queue *rxq, 553 int buf_size) 554 { 555 u32 val; 556 557 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 558 559 val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 560 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 561 562 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 563 } 564 565 static int mvneta_port_is_fixed_link(struct mvneta_port *pp) 566 { 567 /* phy_addr is set to invalid value for fixed link */ 568 return pp->phyaddr > PHY_MAX_ADDR; 569 } 570 571 572 /* Start the Ethernet port RX and TX activity */ 573 static void mvneta_port_up(struct mvneta_port *pp) 574 { 575 int queue; 576 u32 q_map; 577 578 /* Enable all initialized TXs. */ 579 mvneta_mib_counters_clear(pp); 580 q_map = 0; 581 for (queue = 0; queue < txq_number; queue++) { 582 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 583 if (txq->descs != NULL) 584 q_map |= (1 << queue); 585 } 586 mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 587 588 /* Enable all initialized RXQs. */ 589 q_map = 0; 590 for (queue = 0; queue < rxq_number; queue++) { 591 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 592 if (rxq->descs != NULL) 593 q_map |= (1 << queue); 594 } 595 mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 596 } 597 598 /* Stop the Ethernet port activity */ 599 static void mvneta_port_down(struct mvneta_port *pp) 600 { 601 u32 val; 602 int count; 603 604 /* Stop Rx port activity. Check port Rx activity. */ 605 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 606 607 /* Issue stop command for active channels only */ 608 if (val != 0) 609 mvreg_write(pp, MVNETA_RXQ_CMD, 610 val << MVNETA_RXQ_DISABLE_SHIFT); 611 612 /* Wait for all Rx activity to terminate. */ 613 count = 0; 614 do { 615 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 616 netdev_warn(pp->dev, 617 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", 618 val); 619 break; 620 } 621 mdelay(1); 622 623 val = mvreg_read(pp, MVNETA_RXQ_CMD); 624 } while (val & 0xff); 625 626 /* Stop Tx port activity. Check port Tx activity. Issue stop 627 * command for active channels only 628 */ 629 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 630 631 if (val != 0) 632 mvreg_write(pp, MVNETA_TXQ_CMD, 633 (val << MVNETA_TXQ_DISABLE_SHIFT)); 634 635 /* Wait for all Tx activity to terminate. */ 636 count = 0; 637 do { 638 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 639 netdev_warn(pp->dev, 640 "TIMEOUT for TX stopped status=0x%08x\n", 641 val); 642 break; 643 } 644 mdelay(1); 645 646 /* Check TX Command reg that all Txqs are stopped */ 647 val = mvreg_read(pp, MVNETA_TXQ_CMD); 648 649 } while (val & 0xff); 650 651 /* Double check to verify that TX FIFO is empty */ 652 count = 0; 653 do { 654 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 655 netdev_warn(pp->dev, 656 "TX FIFO empty timeout status=0x08%x\n", 657 val); 658 break; 659 } 660 mdelay(1); 661 662 val = mvreg_read(pp, MVNETA_PORT_STATUS); 663 } while (!(val & MVNETA_TX_FIFO_EMPTY) && 664 (val & MVNETA_TX_IN_PRGRS)); 665 666 udelay(200); 667 } 668 669 /* Enable the port by setting the port enable bit of the MAC control register */ 670 static void mvneta_port_enable(struct mvneta_port *pp) 671 { 672 u32 val; 673 674 /* Enable port */ 675 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 676 val |= MVNETA_GMAC0_PORT_ENABLE; 677 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 678 } 679 680 /* Disable the port and wait for about 200 usec before retuning */ 681 static void mvneta_port_disable(struct mvneta_port *pp) 682 { 683 u32 val; 684 685 /* Reset the Enable bit in the Serial Control Register */ 686 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 687 val &= ~MVNETA_GMAC0_PORT_ENABLE; 688 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 689 690 udelay(200); 691 } 692 693 /* Multicast tables methods */ 694 695 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 696 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 697 { 698 int offset; 699 u32 val; 700 701 if (queue == -1) { 702 val = 0; 703 } else { 704 val = 0x1 | (queue << 1); 705 val |= (val << 24) | (val << 16) | (val << 8); 706 } 707 708 for (offset = 0; offset <= 0xc; offset += 4) 709 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 710 } 711 712 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 713 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 714 { 715 int offset; 716 u32 val; 717 718 if (queue == -1) { 719 val = 0; 720 } else { 721 val = 0x1 | (queue << 1); 722 val |= (val << 24) | (val << 16) | (val << 8); 723 } 724 725 for (offset = 0; offset <= 0xfc; offset += 4) 726 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 727 } 728 729 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 730 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 731 { 732 int offset; 733 u32 val; 734 735 if (queue == -1) { 736 memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 737 val = 0; 738 } else { 739 memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 740 val = 0x1 | (queue << 1); 741 val |= (val << 24) | (val << 16) | (val << 8); 742 } 743 744 for (offset = 0; offset <= 0xfc; offset += 4) 745 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 746 } 747 748 /* This method sets defaults to the NETA port: 749 * Clears interrupt Cause and Mask registers. 750 * Clears all MAC tables. 751 * Sets defaults to all registers. 752 * Resets RX and TX descriptor rings. 753 * Resets PHY. 754 * This method can be called after mvneta_port_down() to return the port 755 * settings to defaults. 756 */ 757 static void mvneta_defaults_set(struct mvneta_port *pp) 758 { 759 int cpu; 760 int queue; 761 u32 val; 762 763 /* Clear all Cause registers */ 764 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 765 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 766 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 767 768 /* Mask all interrupts */ 769 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 770 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 771 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 772 mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 773 774 /* Enable MBUS Retry bit16 */ 775 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 776 777 /* Set CPU queue access map - all CPUs have access to all RX 778 * queues and to all TX queues 779 */ 780 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) 781 mvreg_write(pp, MVNETA_CPU_MAP(cpu), 782 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | 783 MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); 784 785 /* Reset RX and TX DMAs */ 786 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 787 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 788 789 /* Disable Legacy WRR, Disable EJP, Release from reset */ 790 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 791 for (queue = 0; queue < txq_number; queue++) { 792 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 793 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 794 } 795 796 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 797 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 798 799 /* Set Port Acceleration Mode */ 800 val = MVNETA_ACC_MODE_EXT; 801 mvreg_write(pp, MVNETA_ACC_MODE, val); 802 803 /* Update val of portCfg register accordingly with all RxQueue types */ 804 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); 805 mvreg_write(pp, MVNETA_PORT_CONFIG, val); 806 807 val = 0; 808 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 809 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 810 811 /* Build PORT_SDMA_CONFIG_REG */ 812 val = 0; 813 814 /* Default burst size */ 815 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 816 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 817 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 818 819 /* Assign port SDMA configuration */ 820 mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 821 822 /* Enable PHY polling in hardware if not in fixed-link mode */ 823 if (!mvneta_port_is_fixed_link(pp)) { 824 val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 825 val |= MVNETA_PHY_POLLING_ENABLE; 826 mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 827 } 828 829 mvneta_set_ucast_table(pp, -1); 830 mvneta_set_special_mcast_table(pp, -1); 831 mvneta_set_other_mcast_table(pp, -1); 832 } 833 834 /* Set unicast address */ 835 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 836 int queue) 837 { 838 unsigned int unicast_reg; 839 unsigned int tbl_offset; 840 unsigned int reg_offset; 841 842 /* Locate the Unicast table entry */ 843 last_nibble = (0xf & last_nibble); 844 845 /* offset from unicast tbl base */ 846 tbl_offset = (last_nibble / 4) * 4; 847 848 /* offset within the above reg */ 849 reg_offset = last_nibble % 4; 850 851 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 852 853 if (queue == -1) { 854 /* Clear accepts frame bit at specified unicast DA tbl entry */ 855 unicast_reg &= ~(0xff << (8 * reg_offset)); 856 } else { 857 unicast_reg &= ~(0xff << (8 * reg_offset)); 858 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 859 } 860 861 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 862 } 863 864 /* Set mac address */ 865 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 866 int queue) 867 { 868 unsigned int mac_h; 869 unsigned int mac_l; 870 871 if (queue != -1) { 872 mac_l = (addr[4] << 8) | (addr[5]); 873 mac_h = (addr[0] << 24) | (addr[1] << 16) | 874 (addr[2] << 8) | (addr[3] << 0); 875 876 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 877 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 878 } 879 880 /* Accept frames of this address */ 881 mvneta_set_ucast_addr(pp, addr[5], queue); 882 } 883 884 static int mvneta_write_hwaddr(struct udevice *dev) 885 { 886 mvneta_mac_addr_set(dev_get_priv(dev), 887 ((struct eth_pdata *)dev_get_platdata(dev))->enetaddr, 888 rxq_def); 889 890 return 0; 891 } 892 893 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 894 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 895 u32 phys_addr, u32 cookie) 896 { 897 rx_desc->buf_cookie = cookie; 898 rx_desc->buf_phys_addr = phys_addr; 899 } 900 901 /* Decrement sent descriptors counter */ 902 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 903 struct mvneta_tx_queue *txq, 904 int sent_desc) 905 { 906 u32 val; 907 908 /* Only 255 TX descriptors can be updated at once */ 909 while (sent_desc > 0xff) { 910 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 911 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 912 sent_desc = sent_desc - 0xff; 913 } 914 915 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 916 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 917 } 918 919 /* Get number of TX descriptors already sent by HW */ 920 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 921 struct mvneta_tx_queue *txq) 922 { 923 u32 val; 924 int sent_desc; 925 926 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 927 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 928 MVNETA_TXQ_SENT_DESC_SHIFT; 929 930 return sent_desc; 931 } 932 933 /* Display more error info */ 934 static void mvneta_rx_error(struct mvneta_port *pp, 935 struct mvneta_rx_desc *rx_desc) 936 { 937 u32 status = rx_desc->status; 938 939 if (!mvneta_rxq_desc_is_first_last(status)) { 940 netdev_err(pp->dev, 941 "bad rx status %08x (buffer oversize), size=%d\n", 942 status, rx_desc->data_size); 943 return; 944 } 945 946 switch (status & MVNETA_RXD_ERR_CODE_MASK) { 947 case MVNETA_RXD_ERR_CRC: 948 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 949 status, rx_desc->data_size); 950 break; 951 case MVNETA_RXD_ERR_OVERRUN: 952 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 953 status, rx_desc->data_size); 954 break; 955 case MVNETA_RXD_ERR_LEN: 956 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 957 status, rx_desc->data_size); 958 break; 959 case MVNETA_RXD_ERR_RESOURCE: 960 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 961 status, rx_desc->data_size); 962 break; 963 } 964 } 965 966 static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp, 967 int rxq) 968 { 969 return &pp->rxqs[rxq]; 970 } 971 972 973 /* Drop packets received by the RXQ and free buffers */ 974 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 975 struct mvneta_rx_queue *rxq) 976 { 977 int rx_done; 978 979 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 980 if (rx_done) 981 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 982 } 983 984 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 985 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 986 int num) 987 { 988 int i; 989 990 for (i = 0; i < num; i++) { 991 u32 addr; 992 993 /* U-Boot special: Fill in the rx buffer addresses */ 994 addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE); 995 mvneta_rx_desc_fill(rxq->descs + i, addr, addr); 996 } 997 998 /* Add this number of RX descriptors as non occupied (ready to 999 * get packets) 1000 */ 1001 mvneta_rxq_non_occup_desc_add(pp, rxq, i); 1002 1003 return 0; 1004 } 1005 1006 /* Rx/Tx queue initialization/cleanup methods */ 1007 1008 /* Create a specified RX queue */ 1009 static int mvneta_rxq_init(struct mvneta_port *pp, 1010 struct mvneta_rx_queue *rxq) 1011 1012 { 1013 rxq->size = pp->rx_ring_size; 1014 1015 /* Allocate memory for RX descriptors */ 1016 rxq->descs_phys = (dma_addr_t)rxq->descs; 1017 if (rxq->descs == NULL) 1018 return -ENOMEM; 1019 1020 WARN_ON(rxq->descs != PTR_ALIGN(rxq->descs, ARCH_DMA_MINALIGN)); 1021 1022 rxq->last_desc = rxq->size - 1; 1023 1024 /* Set Rx descriptors queue starting address */ 1025 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 1026 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 1027 1028 /* Fill RXQ with buffers from RX pool */ 1029 mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE); 1030 mvneta_rxq_fill(pp, rxq, rxq->size); 1031 1032 return 0; 1033 } 1034 1035 /* Cleanup Rx queue */ 1036 static void mvneta_rxq_deinit(struct mvneta_port *pp, 1037 struct mvneta_rx_queue *rxq) 1038 { 1039 mvneta_rxq_drop_pkts(pp, rxq); 1040 1041 rxq->descs = NULL; 1042 rxq->last_desc = 0; 1043 rxq->next_desc_to_proc = 0; 1044 rxq->descs_phys = 0; 1045 } 1046 1047 /* Create and initialize a tx queue */ 1048 static int mvneta_txq_init(struct mvneta_port *pp, 1049 struct mvneta_tx_queue *txq) 1050 { 1051 txq->size = pp->tx_ring_size; 1052 1053 /* Allocate memory for TX descriptors */ 1054 txq->descs_phys = (dma_addr_t)txq->descs; 1055 if (txq->descs == NULL) 1056 return -ENOMEM; 1057 1058 WARN_ON(txq->descs != PTR_ALIGN(txq->descs, ARCH_DMA_MINALIGN)); 1059 1060 txq->last_desc = txq->size - 1; 1061 1062 /* Set maximum bandwidth for enabled TXQs */ 1063 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 1064 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 1065 1066 /* Set Tx descriptors queue starting address */ 1067 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 1068 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 1069 1070 return 0; 1071 } 1072 1073 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 1074 static void mvneta_txq_deinit(struct mvneta_port *pp, 1075 struct mvneta_tx_queue *txq) 1076 { 1077 txq->descs = NULL; 1078 txq->last_desc = 0; 1079 txq->next_desc_to_proc = 0; 1080 txq->descs_phys = 0; 1081 1082 /* Set minimum bandwidth for disabled TXQs */ 1083 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 1084 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 1085 1086 /* Set Tx descriptors queue starting address and size */ 1087 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 1088 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 1089 } 1090 1091 /* Cleanup all Tx queues */ 1092 static void mvneta_cleanup_txqs(struct mvneta_port *pp) 1093 { 1094 int queue; 1095 1096 for (queue = 0; queue < txq_number; queue++) 1097 mvneta_txq_deinit(pp, &pp->txqs[queue]); 1098 } 1099 1100 /* Cleanup all Rx queues */ 1101 static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 1102 { 1103 int queue; 1104 1105 for (queue = 0; queue < rxq_number; queue++) 1106 mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 1107 } 1108 1109 1110 /* Init all Rx queues */ 1111 static int mvneta_setup_rxqs(struct mvneta_port *pp) 1112 { 1113 int queue; 1114 1115 for (queue = 0; queue < rxq_number; queue++) { 1116 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 1117 if (err) { 1118 netdev_err(pp->dev, "%s: can't create rxq=%d\n", 1119 __func__, queue); 1120 mvneta_cleanup_rxqs(pp); 1121 return err; 1122 } 1123 } 1124 1125 return 0; 1126 } 1127 1128 /* Init all tx queues */ 1129 static int mvneta_setup_txqs(struct mvneta_port *pp) 1130 { 1131 int queue; 1132 1133 for (queue = 0; queue < txq_number; queue++) { 1134 int err = mvneta_txq_init(pp, &pp->txqs[queue]); 1135 if (err) { 1136 netdev_err(pp->dev, "%s: can't create txq=%d\n", 1137 __func__, queue); 1138 mvneta_cleanup_txqs(pp); 1139 return err; 1140 } 1141 } 1142 1143 return 0; 1144 } 1145 1146 static void mvneta_start_dev(struct mvneta_port *pp) 1147 { 1148 /* start the Rx/Tx activity */ 1149 mvneta_port_enable(pp); 1150 } 1151 1152 static void mvneta_adjust_link(struct udevice *dev) 1153 { 1154 struct mvneta_port *pp = dev_get_priv(dev); 1155 struct phy_device *phydev = pp->phydev; 1156 int status_change = 0; 1157 1158 if (mvneta_port_is_fixed_link(pp)) { 1159 debug("Using fixed link, skip link adjust\n"); 1160 return; 1161 } 1162 1163 if (phydev->link) { 1164 if ((pp->speed != phydev->speed) || 1165 (pp->duplex != phydev->duplex)) { 1166 u32 val; 1167 1168 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 1169 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | 1170 MVNETA_GMAC_CONFIG_GMII_SPEED | 1171 MVNETA_GMAC_CONFIG_FULL_DUPLEX | 1172 MVNETA_GMAC_AN_SPEED_EN | 1173 MVNETA_GMAC_AN_DUPLEX_EN); 1174 1175 if (phydev->duplex) 1176 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 1177 1178 if (phydev->speed == SPEED_1000) 1179 val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 1180 else 1181 val |= MVNETA_GMAC_CONFIG_MII_SPEED; 1182 1183 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1184 1185 pp->duplex = phydev->duplex; 1186 pp->speed = phydev->speed; 1187 } 1188 } 1189 1190 if (phydev->link != pp->link) { 1191 if (!phydev->link) { 1192 pp->duplex = -1; 1193 pp->speed = 0; 1194 } 1195 1196 pp->link = phydev->link; 1197 status_change = 1; 1198 } 1199 1200 if (status_change) { 1201 if (phydev->link) { 1202 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 1203 val |= (MVNETA_GMAC_FORCE_LINK_PASS | 1204 MVNETA_GMAC_FORCE_LINK_DOWN); 1205 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1206 mvneta_port_up(pp); 1207 } else { 1208 mvneta_port_down(pp); 1209 } 1210 } 1211 } 1212 1213 static int mvneta_open(struct udevice *dev) 1214 { 1215 struct mvneta_port *pp = dev_get_priv(dev); 1216 int ret; 1217 1218 ret = mvneta_setup_rxqs(pp); 1219 if (ret) 1220 return ret; 1221 1222 ret = mvneta_setup_txqs(pp); 1223 if (ret) 1224 return ret; 1225 1226 mvneta_adjust_link(dev); 1227 1228 mvneta_start_dev(pp); 1229 1230 return 0; 1231 } 1232 1233 /* Initialize hw */ 1234 static int mvneta_init2(struct mvneta_port *pp) 1235 { 1236 int queue; 1237 1238 /* Disable port */ 1239 mvneta_port_disable(pp); 1240 1241 /* Set port default values */ 1242 mvneta_defaults_set(pp); 1243 1244 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue), 1245 GFP_KERNEL); 1246 if (!pp->txqs) 1247 return -ENOMEM; 1248 1249 /* U-Boot special: use preallocated area */ 1250 pp->txqs[0].descs = buffer_loc.tx_descs; 1251 1252 /* Initialize TX descriptor rings */ 1253 for (queue = 0; queue < txq_number; queue++) { 1254 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1255 txq->id = queue; 1256 txq->size = pp->tx_ring_size; 1257 } 1258 1259 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue), 1260 GFP_KERNEL); 1261 if (!pp->rxqs) { 1262 kfree(pp->txqs); 1263 return -ENOMEM; 1264 } 1265 1266 /* U-Boot special: use preallocated area */ 1267 pp->rxqs[0].descs = buffer_loc.rx_descs; 1268 1269 /* Create Rx descriptor rings */ 1270 for (queue = 0; queue < rxq_number; queue++) { 1271 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 1272 rxq->id = queue; 1273 rxq->size = pp->rx_ring_size; 1274 } 1275 1276 return 0; 1277 } 1278 1279 /* platform glue : initialize decoding windows */ 1280 1281 /* 1282 * Not like A380, in Armada3700, there are two layers of decode windows for GBE: 1283 * First layer is: GbE Address window that resides inside the GBE unit, 1284 * Second layer is: Fabric address window which is located in the NIC400 1285 * (South Fabric). 1286 * To simplify the address decode configuration for Armada3700, we bypass the 1287 * first layer of GBE decode window by setting the first window to 4GB. 1288 */ 1289 static void mvneta_bypass_mbus_windows(struct mvneta_port *pp) 1290 { 1291 /* 1292 * Set window size to 4GB, to bypass GBE address decode, leave the 1293 * work to MBUS decode window 1294 */ 1295 mvreg_write(pp, MVNETA_WIN_SIZE(0), MVNETA_WIN_SIZE_MASK); 1296 1297 /* Enable GBE address decode window 0 by set bit 0 to 0 */ 1298 clrbits_le32(pp->base + MVNETA_BASE_ADDR_ENABLE, 1299 MVNETA_BASE_ADDR_ENABLE_BIT); 1300 1301 /* Set GBE address decode window 0 to full Access (read or write) */ 1302 setbits_le32(pp->base + MVNETA_PORT_ACCESS_PROTECT, 1303 MVNETA_PORT_ACCESS_PROTECT_WIN0_RW); 1304 } 1305 1306 static void mvneta_conf_mbus_windows(struct mvneta_port *pp) 1307 { 1308 const struct mbus_dram_target_info *dram; 1309 u32 win_enable; 1310 u32 win_protect; 1311 int i; 1312 1313 dram = mvebu_mbus_dram_info(); 1314 for (i = 0; i < 6; i++) { 1315 mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1316 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1317 1318 if (i < 4) 1319 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1320 } 1321 1322 win_enable = 0x3f; 1323 win_protect = 0; 1324 1325 for (i = 0; i < dram->num_cs; i++) { 1326 const struct mbus_dram_window *cs = dram->cs + i; 1327 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | 1328 (cs->mbus_attr << 8) | dram->mbus_dram_target_id); 1329 1330 mvreg_write(pp, MVNETA_WIN_SIZE(i), 1331 (cs->size - 1) & 0xffff0000); 1332 1333 win_enable &= ~(1 << i); 1334 win_protect |= 3 << (2 * i); 1335 } 1336 1337 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1338 } 1339 1340 /* Power up the port */ 1341 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 1342 { 1343 u32 ctrl; 1344 1345 /* MAC Cause register should be cleared */ 1346 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 1347 1348 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 1349 1350 /* Even though it might look weird, when we're configured in 1351 * SGMII or QSGMII mode, the RGMII bit needs to be set. 1352 */ 1353 switch (phy_mode) { 1354 case PHY_INTERFACE_MODE_QSGMII: 1355 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 1356 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 1357 break; 1358 case PHY_INTERFACE_MODE_SGMII: 1359 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 1360 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 1361 break; 1362 case PHY_INTERFACE_MODE_RGMII: 1363 case PHY_INTERFACE_MODE_RGMII_ID: 1364 ctrl |= MVNETA_GMAC2_PORT_RGMII; 1365 break; 1366 default: 1367 return -EINVAL; 1368 } 1369 1370 /* Cancel Port Reset */ 1371 ctrl &= ~MVNETA_GMAC2_PORT_RESET; 1372 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); 1373 1374 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 1375 MVNETA_GMAC2_PORT_RESET) != 0) 1376 continue; 1377 1378 return 0; 1379 } 1380 1381 /* Device initialization routine */ 1382 static int mvneta_init(struct udevice *dev) 1383 { 1384 struct eth_pdata *pdata = dev_get_platdata(dev); 1385 struct mvneta_port *pp = dev_get_priv(dev); 1386 int err; 1387 1388 pp->tx_ring_size = MVNETA_MAX_TXD; 1389 pp->rx_ring_size = MVNETA_MAX_RXD; 1390 1391 err = mvneta_init2(pp); 1392 if (err < 0) { 1393 dev_err(&pdev->dev, "can't init eth hal\n"); 1394 return err; 1395 } 1396 1397 mvneta_mac_addr_set(pp, pdata->enetaddr, rxq_def); 1398 1399 err = mvneta_port_power_up(pp, pp->phy_interface); 1400 if (err < 0) { 1401 dev_err(&pdev->dev, "can't power up port\n"); 1402 return err; 1403 } 1404 1405 /* Call open() now as it needs to be done before runing send() */ 1406 mvneta_open(dev); 1407 1408 return 0; 1409 } 1410 1411 /* U-Boot only functions follow here */ 1412 1413 /* SMI / MDIO functions */ 1414 1415 static int smi_wait_ready(struct mvneta_port *pp) 1416 { 1417 u32 timeout = MVNETA_SMI_TIMEOUT; 1418 u32 smi_reg; 1419 1420 /* wait till the SMI is not busy */ 1421 do { 1422 /* read smi register */ 1423 smi_reg = mvreg_read(pp, MVNETA_SMI); 1424 if (timeout-- == 0) { 1425 printf("Error: SMI busy timeout\n"); 1426 return -EFAULT; 1427 } 1428 } while (smi_reg & MVNETA_SMI_BUSY); 1429 1430 return 0; 1431 } 1432 1433 /* 1434 * mvneta_mdio_read - miiphy_read callback function. 1435 * 1436 * Returns 16bit phy register value, or 0xffff on error 1437 */ 1438 static int mvneta_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) 1439 { 1440 struct mvneta_port *pp = bus->priv; 1441 u32 smi_reg; 1442 u32 timeout; 1443 1444 /* check parameters */ 1445 if (addr > MVNETA_PHY_ADDR_MASK) { 1446 printf("Error: Invalid PHY address %d\n", addr); 1447 return -EFAULT; 1448 } 1449 1450 if (reg > MVNETA_PHY_REG_MASK) { 1451 printf("Err: Invalid register offset %d\n", reg); 1452 return -EFAULT; 1453 } 1454 1455 /* wait till the SMI is not busy */ 1456 if (smi_wait_ready(pp) < 0) 1457 return -EFAULT; 1458 1459 /* fill the phy address and regiser offset and read opcode */ 1460 smi_reg = (addr << MVNETA_SMI_DEV_ADDR_OFFS) 1461 | (reg << MVNETA_SMI_REG_ADDR_OFFS) 1462 | MVNETA_SMI_OPCODE_READ; 1463 1464 /* write the smi register */ 1465 mvreg_write(pp, MVNETA_SMI, smi_reg); 1466 1467 /* wait till read value is ready */ 1468 timeout = MVNETA_SMI_TIMEOUT; 1469 1470 do { 1471 /* read smi register */ 1472 smi_reg = mvreg_read(pp, MVNETA_SMI); 1473 if (timeout-- == 0) { 1474 printf("Err: SMI read ready timeout\n"); 1475 return -EFAULT; 1476 } 1477 } while (!(smi_reg & MVNETA_SMI_READ_VALID)); 1478 1479 /* Wait for the data to update in the SMI register */ 1480 for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++) 1481 ; 1482 1483 return mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK; 1484 } 1485 1486 /* 1487 * mvneta_mdio_write - miiphy_write callback function. 1488 * 1489 * Returns 0 if write succeed, -EINVAL on bad parameters 1490 * -ETIME on timeout 1491 */ 1492 static int mvneta_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, 1493 u16 value) 1494 { 1495 struct mvneta_port *pp = bus->priv; 1496 u32 smi_reg; 1497 1498 /* check parameters */ 1499 if (addr > MVNETA_PHY_ADDR_MASK) { 1500 printf("Error: Invalid PHY address %d\n", addr); 1501 return -EFAULT; 1502 } 1503 1504 if (reg > MVNETA_PHY_REG_MASK) { 1505 printf("Err: Invalid register offset %d\n", reg); 1506 return -EFAULT; 1507 } 1508 1509 /* wait till the SMI is not busy */ 1510 if (smi_wait_ready(pp) < 0) 1511 return -EFAULT; 1512 1513 /* fill the phy addr and reg offset and write opcode and data */ 1514 smi_reg = value << MVNETA_SMI_DATA_OFFS; 1515 smi_reg |= (addr << MVNETA_SMI_DEV_ADDR_OFFS) 1516 | (reg << MVNETA_SMI_REG_ADDR_OFFS); 1517 smi_reg &= ~MVNETA_SMI_OPCODE_READ; 1518 1519 /* write the smi register */ 1520 mvreg_write(pp, MVNETA_SMI, smi_reg); 1521 1522 return 0; 1523 } 1524 1525 static int mvneta_start(struct udevice *dev) 1526 { 1527 struct mvneta_port *pp = dev_get_priv(dev); 1528 struct phy_device *phydev; 1529 1530 mvneta_port_power_up(pp, pp->phy_interface); 1531 1532 if (!pp->init || pp->link == 0) { 1533 if (mvneta_port_is_fixed_link(pp)) { 1534 u32 val; 1535 1536 pp->init = 1; 1537 pp->link = 1; 1538 mvneta_init(dev); 1539 1540 val = MVNETA_GMAC_FORCE_LINK_UP | 1541 MVNETA_GMAC_IB_BYPASS_AN_EN | 1542 MVNETA_GMAC_SET_FC_EN | 1543 MVNETA_GMAC_ADVERT_FC_EN | 1544 MVNETA_GMAC_SAMPLE_TX_CFG_EN; 1545 1546 if (pp->duplex) 1547 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 1548 1549 if (pp->speed == SPEED_1000) 1550 val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 1551 else if (pp->speed == SPEED_100) 1552 val |= MVNETA_GMAC_CONFIG_MII_SPEED; 1553 1554 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1555 } else { 1556 /* Set phy address of the port */ 1557 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr); 1558 1559 phydev = phy_connect(pp->bus, pp->phyaddr, dev, 1560 pp->phy_interface); 1561 if (!phydev) { 1562 printf("phy_connect failed\n"); 1563 return -ENODEV; 1564 } 1565 1566 pp->phydev = phydev; 1567 phy_config(phydev); 1568 phy_startup(phydev); 1569 if (!phydev->link) { 1570 printf("%s: No link.\n", phydev->dev->name); 1571 return -1; 1572 } 1573 1574 /* Full init on first call */ 1575 mvneta_init(dev); 1576 pp->init = 1; 1577 return 0; 1578 } 1579 } 1580 1581 /* Upon all following calls, this is enough */ 1582 mvneta_port_up(pp); 1583 mvneta_port_enable(pp); 1584 1585 return 0; 1586 } 1587 1588 static int mvneta_send(struct udevice *dev, void *packet, int length) 1589 { 1590 struct mvneta_port *pp = dev_get_priv(dev); 1591 struct mvneta_tx_queue *txq = &pp->txqs[0]; 1592 struct mvneta_tx_desc *tx_desc; 1593 int sent_desc; 1594 u32 timeout = 0; 1595 1596 /* Get a descriptor for the first part of the packet */ 1597 tx_desc = mvneta_txq_next_desc_get(txq); 1598 1599 tx_desc->buf_phys_addr = (u32)(uintptr_t)packet; 1600 tx_desc->data_size = length; 1601 flush_dcache_range((ulong)packet, 1602 (ulong)packet + ALIGN(length, PKTALIGN)); 1603 1604 /* First and Last descriptor */ 1605 tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC; 1606 mvneta_txq_pend_desc_add(pp, txq, 1); 1607 1608 /* Wait for packet to be sent (queue might help with speed here) */ 1609 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1610 while (!sent_desc) { 1611 if (timeout++ > 10000) { 1612 printf("timeout: packet not sent\n"); 1613 return -1; 1614 } 1615 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1616 } 1617 1618 /* txDone has increased - hw sent packet */ 1619 mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1620 1621 return 0; 1622 } 1623 1624 static int mvneta_recv(struct udevice *dev, int flags, uchar **packetp) 1625 { 1626 struct mvneta_port *pp = dev_get_priv(dev); 1627 int rx_done; 1628 struct mvneta_rx_queue *rxq; 1629 int rx_bytes = 0; 1630 1631 /* get rx queue */ 1632 rxq = mvneta_rxq_handle_get(pp, rxq_def); 1633 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1634 1635 if (rx_done) { 1636 struct mvneta_rx_desc *rx_desc; 1637 unsigned char *data; 1638 u32 rx_status; 1639 1640 /* 1641 * No cache invalidation needed here, since the desc's are 1642 * located in a uncached memory region 1643 */ 1644 rx_desc = mvneta_rxq_next_desc_get(rxq); 1645 1646 rx_status = rx_desc->status; 1647 if (!mvneta_rxq_desc_is_first_last(rx_status) || 1648 (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 1649 mvneta_rx_error(pp, rx_desc); 1650 /* leave the descriptor untouched */ 1651 return -EIO; 1652 } 1653 1654 /* 2 bytes for marvell header. 4 bytes for crc */ 1655 rx_bytes = rx_desc->data_size - 6; 1656 1657 /* give packet to stack - skip on first 2 bytes */ 1658 data = (u8 *)(uintptr_t)rx_desc->buf_cookie + 2; 1659 /* 1660 * No cache invalidation needed here, since the rx_buffer's are 1661 * located in a uncached memory region 1662 */ 1663 *packetp = data; 1664 1665 /* 1666 * Only mark one descriptor as free 1667 * since only one was processed 1668 */ 1669 mvneta_rxq_desc_num_update(pp, rxq, 1, 1); 1670 } 1671 1672 return rx_bytes; 1673 } 1674 1675 static int mvneta_probe(struct udevice *dev) 1676 { 1677 struct eth_pdata *pdata = dev_get_platdata(dev); 1678 struct mvneta_port *pp = dev_get_priv(dev); 1679 void *blob = (void *)gd->fdt_blob; 1680 int node = dev_of_offset(dev); 1681 struct mii_dev *bus; 1682 unsigned long addr; 1683 void *bd_space; 1684 int ret; 1685 int fl_node; 1686 1687 /* 1688 * Allocate buffer area for descs and rx_buffers. This is only 1689 * done once for all interfaces. As only one interface can 1690 * be active. Make this area DMA safe by disabling the D-cache 1691 */ 1692 if (!buffer_loc.tx_descs) { 1693 u32 size; 1694 1695 /* Align buffer area for descs and rx_buffers to 1MiB */ 1696 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 1697 flush_dcache_range((ulong)bd_space, (ulong)bd_space + BD_SPACE); 1698 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space, BD_SPACE, 1699 DCACHE_OFF); 1700 buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space; 1701 size = roundup(MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc), 1702 ARCH_DMA_MINALIGN); 1703 memset(buffer_loc.tx_descs, 0, size); 1704 buffer_loc.rx_descs = (struct mvneta_rx_desc *) 1705 ((phys_addr_t)bd_space + size); 1706 size += roundup(MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc), 1707 ARCH_DMA_MINALIGN); 1708 buffer_loc.rx_buffers = (phys_addr_t)(bd_space + size); 1709 } 1710 1711 pp->base = (void __iomem *)pdata->iobase; 1712 1713 /* Configure MBUS address windows */ 1714 if (device_is_compatible(dev, "marvell,armada-3700-neta")) 1715 mvneta_bypass_mbus_windows(pp); 1716 else 1717 mvneta_conf_mbus_windows(pp); 1718 1719 /* PHY interface is already decoded in mvneta_ofdata_to_platdata() */ 1720 pp->phy_interface = pdata->phy_interface; 1721 1722 /* fetch 'fixed-link' property from 'neta' node */ 1723 fl_node = fdt_subnode_offset(blob, node, "fixed-link"); 1724 if (fl_node != -FDT_ERR_NOTFOUND) { 1725 /* set phy_addr to invalid value for fixed link */ 1726 pp->phyaddr = PHY_MAX_ADDR + 1; 1727 pp->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex"); 1728 pp->speed = fdtdec_get_int(blob, fl_node, "speed", 0); 1729 } else { 1730 /* Now read phyaddr from DT */ 1731 addr = fdtdec_get_int(blob, node, "phy", 0); 1732 addr = fdt_node_offset_by_phandle(blob, addr); 1733 pp->phyaddr = fdtdec_get_int(blob, addr, "reg", 0); 1734 } 1735 1736 bus = mdio_alloc(); 1737 if (!bus) { 1738 printf("Failed to allocate MDIO bus\n"); 1739 return -ENOMEM; 1740 } 1741 1742 bus->read = mvneta_mdio_read; 1743 bus->write = mvneta_mdio_write; 1744 snprintf(bus->name, sizeof(bus->name), dev->name); 1745 bus->priv = (void *)pp; 1746 pp->bus = bus; 1747 1748 ret = mdio_register(bus); 1749 if (ret) 1750 return ret; 1751 1752 return board_network_enable(bus); 1753 } 1754 1755 static void mvneta_stop(struct udevice *dev) 1756 { 1757 struct mvneta_port *pp = dev_get_priv(dev); 1758 1759 mvneta_port_down(pp); 1760 mvneta_port_disable(pp); 1761 } 1762 1763 static const struct eth_ops mvneta_ops = { 1764 .start = mvneta_start, 1765 .send = mvneta_send, 1766 .recv = mvneta_recv, 1767 .stop = mvneta_stop, 1768 .write_hwaddr = mvneta_write_hwaddr, 1769 }; 1770 1771 static int mvneta_ofdata_to_platdata(struct udevice *dev) 1772 { 1773 struct eth_pdata *pdata = dev_get_platdata(dev); 1774 const char *phy_mode; 1775 1776 pdata->iobase = devfdt_get_addr(dev); 1777 1778 /* Get phy-mode / phy_interface from DT */ 1779 pdata->phy_interface = -1; 1780 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 1781 NULL); 1782 if (phy_mode) 1783 pdata->phy_interface = phy_get_interface_by_name(phy_mode); 1784 if (pdata->phy_interface == -1) { 1785 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 1786 return -EINVAL; 1787 } 1788 1789 return 0; 1790 } 1791 1792 static const struct udevice_id mvneta_ids[] = { 1793 { .compatible = "marvell,armada-370-neta" }, 1794 { .compatible = "marvell,armada-xp-neta" }, 1795 { .compatible = "marvell,armada-3700-neta" }, 1796 { } 1797 }; 1798 1799 U_BOOT_DRIVER(mvneta) = { 1800 .name = "mvneta", 1801 .id = UCLASS_ETH, 1802 .of_match = mvneta_ids, 1803 .ofdata_to_platdata = mvneta_ofdata_to_platdata, 1804 .probe = mvneta_probe, 1805 .ops = &mvneta_ops, 1806 .priv_auto_alloc_size = sizeof(struct mvneta_port), 1807 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1808 }; 1809