1 /* 2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3 * 4 * U-Boot version: 5 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 6 * 7 * Based on the Linux version which is: 8 * Copyright (C) 2012 Marvell 9 * 10 * Rami Rosen <rosenr@marvell.com> 11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 12 * 13 * SPDX-License-Identifier: GPL-2.0 14 */ 15 16 #include <common.h> 17 #include <net.h> 18 #include <netdev.h> 19 #include <config.h> 20 #include <malloc.h> 21 #include <asm/io.h> 22 #include <asm/errno.h> 23 #include <phy.h> 24 #include <miiphy.h> 25 #include <watchdog.h> 26 #include <asm/arch/cpu.h> 27 #include <asm/arch/soc.h> 28 #include <linux/compat.h> 29 #include <linux/mbus.h> 30 31 #if !defined(CONFIG_PHYLIB) 32 # error Marvell mvneta requires PHYLIB 33 #endif 34 35 /* Some linux -> U-Boot compatibility stuff */ 36 #define netdev_err(dev, fmt, args...) \ 37 printf(fmt, ##args) 38 #define netdev_warn(dev, fmt, args...) \ 39 printf(fmt, ##args) 40 #define netdev_info(dev, fmt, args...) \ 41 printf(fmt, ##args) 42 43 #define CONFIG_NR_CPUS 1 44 #define BIT(nr) (1UL << (nr)) 45 #define ETH_HLEN 14 /* Total octets in header */ 46 47 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */ 48 #define WRAP (2 + ETH_HLEN + 4 + 32) 49 #define MTU 1500 50 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN)) 51 52 #define MVNETA_SMI_TIMEOUT 10000 53 54 /* Registers */ 55 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 56 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) 57 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 58 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 59 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 60 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 61 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 62 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 63 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 64 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 65 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 66 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 67 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 68 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 69 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 70 #define MVNETA_PORT_RX_RESET 0x1cc0 71 #define MVNETA_PORT_RX_DMA_RESET BIT(0) 72 #define MVNETA_PHY_ADDR 0x2000 73 #define MVNETA_PHY_ADDR_MASK 0x1f 74 #define MVNETA_SMI 0x2004 75 #define MVNETA_PHY_REG_MASK 0x1f 76 /* SMI register fields */ 77 #define MVNETA_SMI_DATA_OFFS 0 /* Data */ 78 #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS) 79 #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ 80 #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/ 81 #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ 82 #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS) 83 #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */ 84 #define MVNETA_SMI_BUSY (1 << 28) /* Busy */ 85 #define MVNETA_MBUS_RETRY 0x2010 86 #define MVNETA_UNIT_INTR_CAUSE 0x2080 87 #define MVNETA_UNIT_CONTROL 0x20B0 88 #define MVNETA_PHY_POLLING_ENABLE BIT(1) 89 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 90 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 91 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 92 #define MVNETA_BASE_ADDR_ENABLE 0x2290 93 #define MVNETA_PORT_CONFIG 0x2400 94 #define MVNETA_UNI_PROMISC_MODE BIT(0) 95 #define MVNETA_DEF_RXQ(q) ((q) << 1) 96 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 97 #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 98 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 99 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 100 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 101 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 102 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 103 MVNETA_DEF_RXQ_ARP(q) | \ 104 MVNETA_DEF_RXQ_TCP(q) | \ 105 MVNETA_DEF_RXQ_UDP(q) | \ 106 MVNETA_DEF_RXQ_BPDU(q) | \ 107 MVNETA_TX_UNSET_ERR_SUM | \ 108 MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 109 #define MVNETA_PORT_CONFIG_EXTEND 0x2404 110 #define MVNETA_MAC_ADDR_LOW 0x2414 111 #define MVNETA_MAC_ADDR_HIGH 0x2418 112 #define MVNETA_SDMA_CONFIG 0x241c 113 #define MVNETA_SDMA_BRST_SIZE_16 4 114 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 115 #define MVNETA_RX_NO_DATA_SWAP BIT(4) 116 #define MVNETA_TX_NO_DATA_SWAP BIT(5) 117 #define MVNETA_DESC_SWAP BIT(6) 118 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 119 #define MVNETA_PORT_STATUS 0x2444 120 #define MVNETA_TX_IN_PRGRS BIT(1) 121 #define MVNETA_TX_FIFO_EMPTY BIT(8) 122 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 123 #define MVNETA_SERDES_CFG 0x24A0 124 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 125 #define MVNETA_QSGMII_SERDES_PROTO 0x0667 126 #define MVNETA_TYPE_PRIO 0x24bc 127 #define MVNETA_FORCE_UNI BIT(21) 128 #define MVNETA_TXQ_CMD_1 0x24e4 129 #define MVNETA_TXQ_CMD 0x2448 130 #define MVNETA_TXQ_DISABLE_SHIFT 8 131 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 132 #define MVNETA_ACC_MODE 0x2500 133 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 134 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 135 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 136 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 137 138 /* Exception Interrupt Port/Queue Cause register */ 139 140 #define MVNETA_INTR_NEW_CAUSE 0x25a0 141 #define MVNETA_INTR_NEW_MASK 0x25a4 142 143 /* bits 0..7 = TXQ SENT, one bit per queue. 144 * bits 8..15 = RXQ OCCUP, one bit per queue. 145 * bits 16..23 = RXQ FREE, one bit per queue. 146 * bit 29 = OLD_REG_SUM, see old reg ? 147 * bit 30 = TX_ERR_SUM, one bit for 4 ports 148 * bit 31 = MISC_SUM, one bit for 4 ports 149 */ 150 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 151 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 152 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 153 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 154 155 #define MVNETA_INTR_OLD_CAUSE 0x25a8 156 #define MVNETA_INTR_OLD_MASK 0x25ac 157 158 /* Data Path Port/Queue Cause Register */ 159 #define MVNETA_INTR_MISC_CAUSE 0x25b0 160 #define MVNETA_INTR_MISC_MASK 0x25b4 161 #define MVNETA_INTR_ENABLE 0x25b8 162 163 #define MVNETA_RXQ_CMD 0x2680 164 #define MVNETA_RXQ_DISABLE_SHIFT 8 165 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 166 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 167 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 168 #define MVNETA_GMAC_CTRL_0 0x2c00 169 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 170 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 171 #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 172 #define MVNETA_GMAC_CTRL_2 0x2c08 173 #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 174 #define MVNETA_GMAC2_PORT_RGMII BIT(4) 175 #define MVNETA_GMAC2_PORT_RESET BIT(6) 176 #define MVNETA_GMAC_STATUS 0x2c10 177 #define MVNETA_GMAC_LINK_UP BIT(0) 178 #define MVNETA_GMAC_SPEED_1000 BIT(1) 179 #define MVNETA_GMAC_SPEED_100 BIT(2) 180 #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 181 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 182 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 183 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 184 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 185 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 186 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 187 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 188 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 189 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 190 #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 191 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 192 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 193 #define MVNETA_MIB_COUNTERS_BASE 0x3080 194 #define MVNETA_MIB_LATE_COLLISION 0x7c 195 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 196 #define MVNETA_DA_FILT_OTH_MCAST 0x3500 197 #define MVNETA_DA_FILT_UCAST_BASE 0x3600 198 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 199 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 200 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 201 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 202 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 203 #define MVNETA_TXQ_DEC_SENT_SHIFT 16 204 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 205 #define MVNETA_TXQ_SENT_DESC_SHIFT 16 206 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 207 #define MVNETA_PORT_TX_RESET 0x3cf0 208 #define MVNETA_PORT_TX_DMA_RESET BIT(0) 209 #define MVNETA_TX_MTU 0x3e0c 210 #define MVNETA_TX_TOKEN_SIZE 0x3e14 211 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 212 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 213 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 214 215 /* Descriptor ring Macros */ 216 #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 217 (((index) < (q)->last_desc) ? ((index) + 1) : 0) 218 219 /* Various constants */ 220 221 /* Coalescing */ 222 #define MVNETA_TXDONE_COAL_PKTS 16 223 #define MVNETA_RX_COAL_PKTS 32 224 #define MVNETA_RX_COAL_USEC 100 225 226 /* The two bytes Marvell header. Either contains a special value used 227 * by Marvell switches when a specific hardware mode is enabled (not 228 * supported by this driver) or is filled automatically by zeroes on 229 * the RX side. Those two bytes being at the front of the Ethernet 230 * header, they allow to have the IP header aligned on a 4 bytes 231 * boundary automatically: the hardware skips those two bytes on its 232 * own. 233 */ 234 #define MVNETA_MH_SIZE 2 235 236 #define MVNETA_VLAN_TAG_LEN 4 237 238 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 239 #define MVNETA_TX_CSUM_MAX_SIZE 9800 240 #define MVNETA_ACC_MODE_EXT 1 241 242 /* Timeout constants */ 243 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 244 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 245 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 246 247 #define MVNETA_TX_MTU_MAX 0x3ffff 248 249 /* Max number of Rx descriptors */ 250 #define MVNETA_MAX_RXD 16 251 252 /* Max number of Tx descriptors */ 253 #define MVNETA_MAX_TXD 16 254 255 /* descriptor aligned size */ 256 #define MVNETA_DESC_ALIGNED_SIZE 32 257 258 struct mvneta_port { 259 void __iomem *base; 260 struct mvneta_rx_queue *rxqs; 261 struct mvneta_tx_queue *txqs; 262 263 u8 mcast_count[256]; 264 u16 tx_ring_size; 265 u16 rx_ring_size; 266 267 phy_interface_t phy_interface; 268 unsigned int link; 269 unsigned int duplex; 270 unsigned int speed; 271 272 int init; 273 int phyaddr; 274 struct phy_device *phydev; 275 struct mii_dev *bus; 276 }; 277 278 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 279 * layout of the transmit and reception DMA descriptors, and their 280 * layout is therefore defined by the hardware design 281 */ 282 283 #define MVNETA_TX_L3_OFF_SHIFT 0 284 #define MVNETA_TX_IP_HLEN_SHIFT 8 285 #define MVNETA_TX_L4_UDP BIT(16) 286 #define MVNETA_TX_L3_IP6 BIT(17) 287 #define MVNETA_TXD_IP_CSUM BIT(18) 288 #define MVNETA_TXD_Z_PAD BIT(19) 289 #define MVNETA_TXD_L_DESC BIT(20) 290 #define MVNETA_TXD_F_DESC BIT(21) 291 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 292 MVNETA_TXD_L_DESC | \ 293 MVNETA_TXD_F_DESC) 294 #define MVNETA_TX_L4_CSUM_FULL BIT(30) 295 #define MVNETA_TX_L4_CSUM_NOT BIT(31) 296 297 #define MVNETA_RXD_ERR_CRC 0x0 298 #define MVNETA_RXD_ERR_SUMMARY BIT(16) 299 #define MVNETA_RXD_ERR_OVERRUN BIT(17) 300 #define MVNETA_RXD_ERR_LEN BIT(18) 301 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 302 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 303 #define MVNETA_RXD_L3_IP4 BIT(25) 304 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) 305 #define MVNETA_RXD_L4_CSUM_OK BIT(30) 306 307 struct mvneta_tx_desc { 308 u32 command; /* Options used by HW for packet transmitting.*/ 309 u16 reserverd1; /* csum_l4 (for future use) */ 310 u16 data_size; /* Data size of transmitted packet in bytes */ 311 u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 312 u32 reserved2; /* hw_cmd - (for future use, PMT) */ 313 u32 reserved3[4]; /* Reserved - (for future use) */ 314 }; 315 316 struct mvneta_rx_desc { 317 u32 status; /* Info about received packet */ 318 u16 reserved1; /* pnc_info - (for future use, PnC) */ 319 u16 data_size; /* Size of received packet in bytes */ 320 321 u32 buf_phys_addr; /* Physical address of the buffer */ 322 u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 323 324 u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 325 u16 reserved3; /* prefetch_cmd, for future use */ 326 u16 reserved4; /* csum_l4 - (for future use, PnC) */ 327 328 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 329 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 330 }; 331 332 struct mvneta_tx_queue { 333 /* Number of this TX queue, in the range 0-7 */ 334 u8 id; 335 336 /* Number of TX DMA descriptors in the descriptor ring */ 337 int size; 338 339 /* Index of last TX DMA descriptor that was inserted */ 340 int txq_put_index; 341 342 /* Index of the TX DMA descriptor to be cleaned up */ 343 int txq_get_index; 344 345 /* Virtual address of the TX DMA descriptors array */ 346 struct mvneta_tx_desc *descs; 347 348 /* DMA address of the TX DMA descriptors array */ 349 dma_addr_t descs_phys; 350 351 /* Index of the last TX DMA descriptor */ 352 int last_desc; 353 354 /* Index of the next TX DMA descriptor to process */ 355 int next_desc_to_proc; 356 }; 357 358 struct mvneta_rx_queue { 359 /* rx queue number, in the range 0-7 */ 360 u8 id; 361 362 /* num of rx descriptors in the rx descriptor ring */ 363 int size; 364 365 /* Virtual address of the RX DMA descriptors array */ 366 struct mvneta_rx_desc *descs; 367 368 /* DMA address of the RX DMA descriptors array */ 369 dma_addr_t descs_phys; 370 371 /* Index of the last RX DMA descriptor */ 372 int last_desc; 373 374 /* Index of the next RX DMA descriptor to process */ 375 int next_desc_to_proc; 376 }; 377 378 /* U-Boot doesn't use the queues, so set the number to 1 */ 379 static int rxq_number = 1; 380 static int txq_number = 1; 381 static int rxq_def; 382 383 struct buffer_location { 384 struct mvneta_tx_desc *tx_descs; 385 struct mvneta_rx_desc *rx_descs; 386 u32 rx_buffers; 387 }; 388 389 /* 390 * All 4 interfaces use the same global buffer, since only one interface 391 * can be enabled at once 392 */ 393 static struct buffer_location buffer_loc; 394 395 /* 396 * Page table entries are set to 1MB, or multiples of 1MB 397 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 398 */ 399 #define BD_SPACE (1 << 20) 400 401 /* Utility/helper methods */ 402 403 /* Write helper method */ 404 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 405 { 406 writel(data, pp->base + offset); 407 } 408 409 /* Read helper method */ 410 static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 411 { 412 return readl(pp->base + offset); 413 } 414 415 /* Clear all MIB counters */ 416 static void mvneta_mib_counters_clear(struct mvneta_port *pp) 417 { 418 int i; 419 420 /* Perform dummy reads from MIB counters */ 421 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 422 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 423 } 424 425 /* Rx descriptors helper methods */ 426 427 /* Checks whether the RX descriptor having this status is both the first 428 * and the last descriptor for the RX packet. Each RX packet is currently 429 * received through a single RX descriptor, so not having each RX 430 * descriptor with its first and last bits set is an error 431 */ 432 static int mvneta_rxq_desc_is_first_last(u32 status) 433 { 434 return (status & MVNETA_RXD_FIRST_LAST_DESC) == 435 MVNETA_RXD_FIRST_LAST_DESC; 436 } 437 438 /* Add number of descriptors ready to receive new packets */ 439 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 440 struct mvneta_rx_queue *rxq, 441 int ndescs) 442 { 443 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 444 * be added at once 445 */ 446 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 447 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 448 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 449 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 450 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 451 } 452 453 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 454 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 455 } 456 457 /* Get number of RX descriptors occupied by received packets */ 458 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 459 struct mvneta_rx_queue *rxq) 460 { 461 u32 val; 462 463 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 464 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 465 } 466 467 /* Update num of rx desc called upon return from rx path or 468 * from mvneta_rxq_drop_pkts(). 469 */ 470 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 471 struct mvneta_rx_queue *rxq, 472 int rx_done, int rx_filled) 473 { 474 u32 val; 475 476 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 477 val = rx_done | 478 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 479 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 480 return; 481 } 482 483 /* Only 255 descriptors can be added at once */ 484 while ((rx_done > 0) || (rx_filled > 0)) { 485 if (rx_done <= 0xff) { 486 val = rx_done; 487 rx_done = 0; 488 } else { 489 val = 0xff; 490 rx_done -= 0xff; 491 } 492 if (rx_filled <= 0xff) { 493 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 494 rx_filled = 0; 495 } else { 496 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 497 rx_filled -= 0xff; 498 } 499 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 500 } 501 } 502 503 /* Get pointer to next RX descriptor to be processed by SW */ 504 static struct mvneta_rx_desc * 505 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 506 { 507 int rx_desc = rxq->next_desc_to_proc; 508 509 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 510 return rxq->descs + rx_desc; 511 } 512 513 /* Tx descriptors helper methods */ 514 515 /* Update HW with number of TX descriptors to be sent */ 516 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 517 struct mvneta_tx_queue *txq, 518 int pend_desc) 519 { 520 u32 val; 521 522 /* Only 255 descriptors can be added at once ; Assume caller 523 * process TX desriptors in quanta less than 256 524 */ 525 val = pend_desc; 526 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 527 } 528 529 /* Get pointer to next TX descriptor to be processed (send) by HW */ 530 static struct mvneta_tx_desc * 531 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 532 { 533 int tx_desc = txq->next_desc_to_proc; 534 535 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 536 return txq->descs + tx_desc; 537 } 538 539 /* Set rxq buf size */ 540 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 541 struct mvneta_rx_queue *rxq, 542 int buf_size) 543 { 544 u32 val; 545 546 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 547 548 val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 549 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 550 551 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 552 } 553 554 /* Start the Ethernet port RX and TX activity */ 555 static void mvneta_port_up(struct mvneta_port *pp) 556 { 557 int queue; 558 u32 q_map; 559 560 /* Enable all initialized TXs. */ 561 mvneta_mib_counters_clear(pp); 562 q_map = 0; 563 for (queue = 0; queue < txq_number; queue++) { 564 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 565 if (txq->descs != NULL) 566 q_map |= (1 << queue); 567 } 568 mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 569 570 /* Enable all initialized RXQs. */ 571 q_map = 0; 572 for (queue = 0; queue < rxq_number; queue++) { 573 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 574 if (rxq->descs != NULL) 575 q_map |= (1 << queue); 576 } 577 mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 578 } 579 580 /* Stop the Ethernet port activity */ 581 static void mvneta_port_down(struct mvneta_port *pp) 582 { 583 u32 val; 584 int count; 585 586 /* Stop Rx port activity. Check port Rx activity. */ 587 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 588 589 /* Issue stop command for active channels only */ 590 if (val != 0) 591 mvreg_write(pp, MVNETA_RXQ_CMD, 592 val << MVNETA_RXQ_DISABLE_SHIFT); 593 594 /* Wait for all Rx activity to terminate. */ 595 count = 0; 596 do { 597 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 598 netdev_warn(pp->dev, 599 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", 600 val); 601 break; 602 } 603 mdelay(1); 604 605 val = mvreg_read(pp, MVNETA_RXQ_CMD); 606 } while (val & 0xff); 607 608 /* Stop Tx port activity. Check port Tx activity. Issue stop 609 * command for active channels only 610 */ 611 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 612 613 if (val != 0) 614 mvreg_write(pp, MVNETA_TXQ_CMD, 615 (val << MVNETA_TXQ_DISABLE_SHIFT)); 616 617 /* Wait for all Tx activity to terminate. */ 618 count = 0; 619 do { 620 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 621 netdev_warn(pp->dev, 622 "TIMEOUT for TX stopped status=0x%08x\n", 623 val); 624 break; 625 } 626 mdelay(1); 627 628 /* Check TX Command reg that all Txqs are stopped */ 629 val = mvreg_read(pp, MVNETA_TXQ_CMD); 630 631 } while (val & 0xff); 632 633 /* Double check to verify that TX FIFO is empty */ 634 count = 0; 635 do { 636 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 637 netdev_warn(pp->dev, 638 "TX FIFO empty timeout status=0x08%x\n", 639 val); 640 break; 641 } 642 mdelay(1); 643 644 val = mvreg_read(pp, MVNETA_PORT_STATUS); 645 } while (!(val & MVNETA_TX_FIFO_EMPTY) && 646 (val & MVNETA_TX_IN_PRGRS)); 647 648 udelay(200); 649 } 650 651 /* Enable the port by setting the port enable bit of the MAC control register */ 652 static void mvneta_port_enable(struct mvneta_port *pp) 653 { 654 u32 val; 655 656 /* Enable port */ 657 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 658 val |= MVNETA_GMAC0_PORT_ENABLE; 659 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 660 } 661 662 /* Disable the port and wait for about 200 usec before retuning */ 663 static void mvneta_port_disable(struct mvneta_port *pp) 664 { 665 u32 val; 666 667 /* Reset the Enable bit in the Serial Control Register */ 668 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 669 val &= ~MVNETA_GMAC0_PORT_ENABLE; 670 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 671 672 udelay(200); 673 } 674 675 /* Multicast tables methods */ 676 677 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 678 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 679 { 680 int offset; 681 u32 val; 682 683 if (queue == -1) { 684 val = 0; 685 } else { 686 val = 0x1 | (queue << 1); 687 val |= (val << 24) | (val << 16) | (val << 8); 688 } 689 690 for (offset = 0; offset <= 0xc; offset += 4) 691 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 692 } 693 694 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 695 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 696 { 697 int offset; 698 u32 val; 699 700 if (queue == -1) { 701 val = 0; 702 } else { 703 val = 0x1 | (queue << 1); 704 val |= (val << 24) | (val << 16) | (val << 8); 705 } 706 707 for (offset = 0; offset <= 0xfc; offset += 4) 708 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 709 } 710 711 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 712 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 713 { 714 int offset; 715 u32 val; 716 717 if (queue == -1) { 718 memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 719 val = 0; 720 } else { 721 memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 722 val = 0x1 | (queue << 1); 723 val |= (val << 24) | (val << 16) | (val << 8); 724 } 725 726 for (offset = 0; offset <= 0xfc; offset += 4) 727 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 728 } 729 730 /* This method sets defaults to the NETA port: 731 * Clears interrupt Cause and Mask registers. 732 * Clears all MAC tables. 733 * Sets defaults to all registers. 734 * Resets RX and TX descriptor rings. 735 * Resets PHY. 736 * This method can be called after mvneta_port_down() to return the port 737 * settings to defaults. 738 */ 739 static void mvneta_defaults_set(struct mvneta_port *pp) 740 { 741 int cpu; 742 int queue; 743 u32 val; 744 745 /* Clear all Cause registers */ 746 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 747 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 748 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 749 750 /* Mask all interrupts */ 751 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 752 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 753 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 754 mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 755 756 /* Enable MBUS Retry bit16 */ 757 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 758 759 /* Set CPU queue access map - all CPUs have access to all RX 760 * queues and to all TX queues 761 */ 762 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) 763 mvreg_write(pp, MVNETA_CPU_MAP(cpu), 764 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | 765 MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); 766 767 /* Reset RX and TX DMAs */ 768 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 769 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 770 771 /* Disable Legacy WRR, Disable EJP, Release from reset */ 772 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 773 for (queue = 0; queue < txq_number; queue++) { 774 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 775 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 776 } 777 778 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 779 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 780 781 /* Set Port Acceleration Mode */ 782 val = MVNETA_ACC_MODE_EXT; 783 mvreg_write(pp, MVNETA_ACC_MODE, val); 784 785 /* Update val of portCfg register accordingly with all RxQueue types */ 786 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); 787 mvreg_write(pp, MVNETA_PORT_CONFIG, val); 788 789 val = 0; 790 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 791 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 792 793 /* Build PORT_SDMA_CONFIG_REG */ 794 val = 0; 795 796 /* Default burst size */ 797 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 798 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 799 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 800 801 /* Assign port SDMA configuration */ 802 mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 803 804 /* Enable PHY polling in hardware for U-Boot */ 805 val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 806 val |= MVNETA_PHY_POLLING_ENABLE; 807 mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 808 809 mvneta_set_ucast_table(pp, -1); 810 mvneta_set_special_mcast_table(pp, -1); 811 mvneta_set_other_mcast_table(pp, -1); 812 } 813 814 /* Set unicast address */ 815 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 816 int queue) 817 { 818 unsigned int unicast_reg; 819 unsigned int tbl_offset; 820 unsigned int reg_offset; 821 822 /* Locate the Unicast table entry */ 823 last_nibble = (0xf & last_nibble); 824 825 /* offset from unicast tbl base */ 826 tbl_offset = (last_nibble / 4) * 4; 827 828 /* offset within the above reg */ 829 reg_offset = last_nibble % 4; 830 831 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 832 833 if (queue == -1) { 834 /* Clear accepts frame bit at specified unicast DA tbl entry */ 835 unicast_reg &= ~(0xff << (8 * reg_offset)); 836 } else { 837 unicast_reg &= ~(0xff << (8 * reg_offset)); 838 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 839 } 840 841 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 842 } 843 844 /* Set mac address */ 845 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 846 int queue) 847 { 848 unsigned int mac_h; 849 unsigned int mac_l; 850 851 if (queue != -1) { 852 mac_l = (addr[4] << 8) | (addr[5]); 853 mac_h = (addr[0] << 24) | (addr[1] << 16) | 854 (addr[2] << 8) | (addr[3] << 0); 855 856 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 857 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 858 } 859 860 /* Accept frames of this address */ 861 mvneta_set_ucast_addr(pp, addr[5], queue); 862 } 863 864 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 865 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 866 u32 phys_addr, u32 cookie) 867 { 868 rx_desc->buf_cookie = cookie; 869 rx_desc->buf_phys_addr = phys_addr; 870 } 871 872 /* Decrement sent descriptors counter */ 873 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 874 struct mvneta_tx_queue *txq, 875 int sent_desc) 876 { 877 u32 val; 878 879 /* Only 255 TX descriptors can be updated at once */ 880 while (sent_desc > 0xff) { 881 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 882 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 883 sent_desc = sent_desc - 0xff; 884 } 885 886 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 887 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 888 } 889 890 /* Get number of TX descriptors already sent by HW */ 891 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 892 struct mvneta_tx_queue *txq) 893 { 894 u32 val; 895 int sent_desc; 896 897 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 898 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 899 MVNETA_TXQ_SENT_DESC_SHIFT; 900 901 return sent_desc; 902 } 903 904 /* Display more error info */ 905 static void mvneta_rx_error(struct mvneta_port *pp, 906 struct mvneta_rx_desc *rx_desc) 907 { 908 u32 status = rx_desc->status; 909 910 if (!mvneta_rxq_desc_is_first_last(status)) { 911 netdev_err(pp->dev, 912 "bad rx status %08x (buffer oversize), size=%d\n", 913 status, rx_desc->data_size); 914 return; 915 } 916 917 switch (status & MVNETA_RXD_ERR_CODE_MASK) { 918 case MVNETA_RXD_ERR_CRC: 919 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 920 status, rx_desc->data_size); 921 break; 922 case MVNETA_RXD_ERR_OVERRUN: 923 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 924 status, rx_desc->data_size); 925 break; 926 case MVNETA_RXD_ERR_LEN: 927 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 928 status, rx_desc->data_size); 929 break; 930 case MVNETA_RXD_ERR_RESOURCE: 931 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 932 status, rx_desc->data_size); 933 break; 934 } 935 } 936 937 static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp, 938 int rxq) 939 { 940 return &pp->rxqs[rxq]; 941 } 942 943 944 /* Drop packets received by the RXQ and free buffers */ 945 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 946 struct mvneta_rx_queue *rxq) 947 { 948 int rx_done; 949 950 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 951 if (rx_done) 952 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 953 } 954 955 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 956 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 957 int num) 958 { 959 int i; 960 961 for (i = 0; i < num; i++) { 962 u32 addr; 963 964 /* U-Boot special: Fill in the rx buffer addresses */ 965 addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE); 966 mvneta_rx_desc_fill(rxq->descs + i, addr, addr); 967 } 968 969 /* Add this number of RX descriptors as non occupied (ready to 970 * get packets) 971 */ 972 mvneta_rxq_non_occup_desc_add(pp, rxq, i); 973 974 return 0; 975 } 976 977 /* Rx/Tx queue initialization/cleanup methods */ 978 979 /* Create a specified RX queue */ 980 static int mvneta_rxq_init(struct mvneta_port *pp, 981 struct mvneta_rx_queue *rxq) 982 983 { 984 rxq->size = pp->rx_ring_size; 985 986 /* Allocate memory for RX descriptors */ 987 rxq->descs_phys = (dma_addr_t)rxq->descs; 988 if (rxq->descs == NULL) 989 return -ENOMEM; 990 991 rxq->last_desc = rxq->size - 1; 992 993 /* Set Rx descriptors queue starting address */ 994 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 995 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 996 997 /* Fill RXQ with buffers from RX pool */ 998 mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE); 999 mvneta_rxq_fill(pp, rxq, rxq->size); 1000 1001 return 0; 1002 } 1003 1004 /* Cleanup Rx queue */ 1005 static void mvneta_rxq_deinit(struct mvneta_port *pp, 1006 struct mvneta_rx_queue *rxq) 1007 { 1008 mvneta_rxq_drop_pkts(pp, rxq); 1009 1010 rxq->descs = NULL; 1011 rxq->last_desc = 0; 1012 rxq->next_desc_to_proc = 0; 1013 rxq->descs_phys = 0; 1014 } 1015 1016 /* Create and initialize a tx queue */ 1017 static int mvneta_txq_init(struct mvneta_port *pp, 1018 struct mvneta_tx_queue *txq) 1019 { 1020 txq->size = pp->tx_ring_size; 1021 1022 /* Allocate memory for TX descriptors */ 1023 txq->descs_phys = (u32)txq->descs; 1024 if (txq->descs == NULL) 1025 return -ENOMEM; 1026 1027 txq->last_desc = txq->size - 1; 1028 1029 /* Set maximum bandwidth for enabled TXQs */ 1030 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 1031 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 1032 1033 /* Set Tx descriptors queue starting address */ 1034 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 1035 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 1036 1037 return 0; 1038 } 1039 1040 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 1041 static void mvneta_txq_deinit(struct mvneta_port *pp, 1042 struct mvneta_tx_queue *txq) 1043 { 1044 txq->descs = NULL; 1045 txq->last_desc = 0; 1046 txq->next_desc_to_proc = 0; 1047 txq->descs_phys = 0; 1048 1049 /* Set minimum bandwidth for disabled TXQs */ 1050 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 1051 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 1052 1053 /* Set Tx descriptors queue starting address and size */ 1054 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 1055 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 1056 } 1057 1058 /* Cleanup all Tx queues */ 1059 static void mvneta_cleanup_txqs(struct mvneta_port *pp) 1060 { 1061 int queue; 1062 1063 for (queue = 0; queue < txq_number; queue++) 1064 mvneta_txq_deinit(pp, &pp->txqs[queue]); 1065 } 1066 1067 /* Cleanup all Rx queues */ 1068 static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 1069 { 1070 int queue; 1071 1072 for (queue = 0; queue < rxq_number; queue++) 1073 mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 1074 } 1075 1076 1077 /* Init all Rx queues */ 1078 static int mvneta_setup_rxqs(struct mvneta_port *pp) 1079 { 1080 int queue; 1081 1082 for (queue = 0; queue < rxq_number; queue++) { 1083 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 1084 if (err) { 1085 netdev_err(pp->dev, "%s: can't create rxq=%d\n", 1086 __func__, queue); 1087 mvneta_cleanup_rxqs(pp); 1088 return err; 1089 } 1090 } 1091 1092 return 0; 1093 } 1094 1095 /* Init all tx queues */ 1096 static int mvneta_setup_txqs(struct mvneta_port *pp) 1097 { 1098 int queue; 1099 1100 for (queue = 0; queue < txq_number; queue++) { 1101 int err = mvneta_txq_init(pp, &pp->txqs[queue]); 1102 if (err) { 1103 netdev_err(pp->dev, "%s: can't create txq=%d\n", 1104 __func__, queue); 1105 mvneta_cleanup_txqs(pp); 1106 return err; 1107 } 1108 } 1109 1110 return 0; 1111 } 1112 1113 static void mvneta_start_dev(struct mvneta_port *pp) 1114 { 1115 /* start the Rx/Tx activity */ 1116 mvneta_port_enable(pp); 1117 } 1118 1119 static void mvneta_adjust_link(struct eth_device *dev) 1120 { 1121 struct mvneta_port *pp = dev->priv; 1122 struct phy_device *phydev = pp->phydev; 1123 int status_change = 0; 1124 1125 if (phydev->link) { 1126 if ((pp->speed != phydev->speed) || 1127 (pp->duplex != phydev->duplex)) { 1128 u32 val; 1129 1130 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 1131 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | 1132 MVNETA_GMAC_CONFIG_GMII_SPEED | 1133 MVNETA_GMAC_CONFIG_FULL_DUPLEX | 1134 MVNETA_GMAC_AN_SPEED_EN | 1135 MVNETA_GMAC_AN_DUPLEX_EN); 1136 1137 if (phydev->duplex) 1138 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 1139 1140 if (phydev->speed == SPEED_1000) 1141 val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 1142 else 1143 val |= MVNETA_GMAC_CONFIG_MII_SPEED; 1144 1145 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1146 1147 pp->duplex = phydev->duplex; 1148 pp->speed = phydev->speed; 1149 } 1150 } 1151 1152 if (phydev->link != pp->link) { 1153 if (!phydev->link) { 1154 pp->duplex = -1; 1155 pp->speed = 0; 1156 } 1157 1158 pp->link = phydev->link; 1159 status_change = 1; 1160 } 1161 1162 if (status_change) { 1163 if (phydev->link) { 1164 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 1165 val |= (MVNETA_GMAC_FORCE_LINK_PASS | 1166 MVNETA_GMAC_FORCE_LINK_DOWN); 1167 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1168 mvneta_port_up(pp); 1169 } else { 1170 mvneta_port_down(pp); 1171 } 1172 } 1173 } 1174 1175 static int mvneta_open(struct eth_device *dev) 1176 { 1177 struct mvneta_port *pp = dev->priv; 1178 int ret; 1179 1180 ret = mvneta_setup_rxqs(pp); 1181 if (ret) 1182 return ret; 1183 1184 ret = mvneta_setup_txqs(pp); 1185 if (ret) 1186 return ret; 1187 1188 mvneta_adjust_link(dev); 1189 1190 mvneta_start_dev(pp); 1191 1192 return 0; 1193 } 1194 1195 /* Initialize hw */ 1196 static int mvneta_init(struct mvneta_port *pp) 1197 { 1198 int queue; 1199 1200 /* Disable port */ 1201 mvneta_port_disable(pp); 1202 1203 /* Set port default values */ 1204 mvneta_defaults_set(pp); 1205 1206 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue), 1207 GFP_KERNEL); 1208 if (!pp->txqs) 1209 return -ENOMEM; 1210 1211 /* U-Boot special: use preallocated area */ 1212 pp->txqs[0].descs = buffer_loc.tx_descs; 1213 1214 /* Initialize TX descriptor rings */ 1215 for (queue = 0; queue < txq_number; queue++) { 1216 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1217 txq->id = queue; 1218 txq->size = pp->tx_ring_size; 1219 } 1220 1221 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue), 1222 GFP_KERNEL); 1223 if (!pp->rxqs) { 1224 kfree(pp->txqs); 1225 return -ENOMEM; 1226 } 1227 1228 /* U-Boot special: use preallocated area */ 1229 pp->rxqs[0].descs = buffer_loc.rx_descs; 1230 1231 /* Create Rx descriptor rings */ 1232 for (queue = 0; queue < rxq_number; queue++) { 1233 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 1234 rxq->id = queue; 1235 rxq->size = pp->rx_ring_size; 1236 } 1237 1238 return 0; 1239 } 1240 1241 /* platform glue : initialize decoding windows */ 1242 static void mvneta_conf_mbus_windows(struct mvneta_port *pp) 1243 { 1244 const struct mbus_dram_target_info *dram; 1245 u32 win_enable; 1246 u32 win_protect; 1247 int i; 1248 1249 dram = mvebu_mbus_dram_info(); 1250 for (i = 0; i < 6; i++) { 1251 mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1252 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1253 1254 if (i < 4) 1255 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1256 } 1257 1258 win_enable = 0x3f; 1259 win_protect = 0; 1260 1261 for (i = 0; i < dram->num_cs; i++) { 1262 const struct mbus_dram_window *cs = dram->cs + i; 1263 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | 1264 (cs->mbus_attr << 8) | dram->mbus_dram_target_id); 1265 1266 mvreg_write(pp, MVNETA_WIN_SIZE(i), 1267 (cs->size - 1) & 0xffff0000); 1268 1269 win_enable &= ~(1 << i); 1270 win_protect |= 3 << (2 * i); 1271 } 1272 1273 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1274 } 1275 1276 /* Power up the port */ 1277 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 1278 { 1279 u32 ctrl; 1280 1281 /* MAC Cause register should be cleared */ 1282 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 1283 1284 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 1285 1286 /* Even though it might look weird, when we're configured in 1287 * SGMII or QSGMII mode, the RGMII bit needs to be set. 1288 */ 1289 switch (phy_mode) { 1290 case PHY_INTERFACE_MODE_QSGMII: 1291 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 1292 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 1293 break; 1294 case PHY_INTERFACE_MODE_SGMII: 1295 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 1296 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 1297 break; 1298 case PHY_INTERFACE_MODE_RGMII: 1299 case PHY_INTERFACE_MODE_RGMII_ID: 1300 ctrl |= MVNETA_GMAC2_PORT_RGMII; 1301 break; 1302 default: 1303 return -EINVAL; 1304 } 1305 1306 /* Cancel Port Reset */ 1307 ctrl &= ~MVNETA_GMAC2_PORT_RESET; 1308 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); 1309 1310 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 1311 MVNETA_GMAC2_PORT_RESET) != 0) 1312 continue; 1313 1314 return 0; 1315 } 1316 1317 /* Device initialization routine */ 1318 static int mvneta_probe(struct eth_device *dev) 1319 { 1320 struct mvneta_port *pp = dev->priv; 1321 int err; 1322 1323 pp->tx_ring_size = MVNETA_MAX_TXD; 1324 pp->rx_ring_size = MVNETA_MAX_RXD; 1325 1326 err = mvneta_init(pp); 1327 if (err < 0) { 1328 dev_err(&pdev->dev, "can't init eth hal\n"); 1329 return err; 1330 } 1331 1332 mvneta_conf_mbus_windows(pp); 1333 1334 mvneta_mac_addr_set(pp, dev->enetaddr, rxq_def); 1335 1336 err = mvneta_port_power_up(pp, pp->phy_interface); 1337 if (err < 0) { 1338 dev_err(&pdev->dev, "can't power up port\n"); 1339 return err; 1340 } 1341 1342 /* Call open() now as it needs to be done before runing send() */ 1343 mvneta_open(dev); 1344 1345 return 0; 1346 } 1347 1348 /* U-Boot only functions follow here */ 1349 1350 /* SMI / MDIO functions */ 1351 1352 static int smi_wait_ready(struct mvneta_port *pp) 1353 { 1354 u32 timeout = MVNETA_SMI_TIMEOUT; 1355 u32 smi_reg; 1356 1357 /* wait till the SMI is not busy */ 1358 do { 1359 /* read smi register */ 1360 smi_reg = mvreg_read(pp, MVNETA_SMI); 1361 if (timeout-- == 0) { 1362 printf("Error: SMI busy timeout\n"); 1363 return -EFAULT; 1364 } 1365 } while (smi_reg & MVNETA_SMI_BUSY); 1366 1367 return 0; 1368 } 1369 1370 /* 1371 * smi_reg_read - miiphy_read callback function. 1372 * 1373 * Returns 16bit phy register value, or 0xffff on error 1374 */ 1375 static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) 1376 { 1377 struct eth_device *dev = eth_get_dev_by_name(devname); 1378 struct mvneta_port *pp = dev->priv; 1379 u32 smi_reg; 1380 u32 timeout; 1381 1382 /* check parameters */ 1383 if (phy_adr > MVNETA_PHY_ADDR_MASK) { 1384 printf("Error: Invalid PHY address %d\n", phy_adr); 1385 return -EFAULT; 1386 } 1387 1388 if (reg_ofs > MVNETA_PHY_REG_MASK) { 1389 printf("Err: Invalid register offset %d\n", reg_ofs); 1390 return -EFAULT; 1391 } 1392 1393 /* wait till the SMI is not busy */ 1394 if (smi_wait_ready(pp) < 0) 1395 return -EFAULT; 1396 1397 /* fill the phy address and regiser offset and read opcode */ 1398 smi_reg = (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS) 1399 | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS) 1400 | MVNETA_SMI_OPCODE_READ; 1401 1402 /* write the smi register */ 1403 mvreg_write(pp, MVNETA_SMI, smi_reg); 1404 1405 /*wait till read value is ready */ 1406 timeout = MVNETA_SMI_TIMEOUT; 1407 1408 do { 1409 /* read smi register */ 1410 smi_reg = mvreg_read(pp, MVNETA_SMI); 1411 if (timeout-- == 0) { 1412 printf("Err: SMI read ready timeout\n"); 1413 return -EFAULT; 1414 } 1415 } while (!(smi_reg & MVNETA_SMI_READ_VALID)); 1416 1417 /* Wait for the data to update in the SMI register */ 1418 for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++) 1419 ; 1420 1421 *data = (u16)(mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK); 1422 1423 return 0; 1424 } 1425 1426 /* 1427 * smi_reg_write - imiiphy_write callback function. 1428 * 1429 * Returns 0 if write succeed, -EINVAL on bad parameters 1430 * -ETIME on timeout 1431 */ 1432 static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) 1433 { 1434 struct eth_device *dev = eth_get_dev_by_name(devname); 1435 struct mvneta_port *pp = dev->priv; 1436 u32 smi_reg; 1437 1438 /* check parameters */ 1439 if (phy_adr > MVNETA_PHY_ADDR_MASK) { 1440 printf("Error: Invalid PHY address %d\n", phy_adr); 1441 return -EFAULT; 1442 } 1443 1444 if (reg_ofs > MVNETA_PHY_REG_MASK) { 1445 printf("Err: Invalid register offset %d\n", reg_ofs); 1446 return -EFAULT; 1447 } 1448 1449 /* wait till the SMI is not busy */ 1450 if (smi_wait_ready(pp) < 0) 1451 return -EFAULT; 1452 1453 /* fill the phy addr and reg offset and write opcode and data */ 1454 smi_reg = (data << MVNETA_SMI_DATA_OFFS); 1455 smi_reg |= (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS) 1456 | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS); 1457 smi_reg &= ~MVNETA_SMI_OPCODE_READ; 1458 1459 /* write the smi register */ 1460 mvreg_write(pp, MVNETA_SMI, smi_reg); 1461 1462 return 0; 1463 } 1464 1465 static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis) 1466 { 1467 struct mvneta_port *pp = dev->priv; 1468 struct phy_device *phydev; 1469 1470 mvneta_port_power_up(pp, pp->phy_interface); 1471 1472 if (!pp->init || pp->link == 0) { 1473 /* Set phy address of the port */ 1474 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr); 1475 phydev = phy_connect(pp->bus, pp->phyaddr, dev, 1476 pp->phy_interface); 1477 1478 pp->phydev = phydev; 1479 phy_config(phydev); 1480 phy_startup(phydev); 1481 if (!phydev->link) { 1482 printf("%s: No link.\n", phydev->dev->name); 1483 return -1; 1484 } 1485 1486 /* Full init on first call */ 1487 mvneta_probe(dev); 1488 pp->init = 1; 1489 } else { 1490 /* Upon all following calls, this is enough */ 1491 mvneta_port_up(pp); 1492 mvneta_port_enable(pp); 1493 } 1494 1495 return 0; 1496 } 1497 1498 static int mvneta_send(struct eth_device *dev, void *ptr, int len) 1499 { 1500 struct mvneta_port *pp = dev->priv; 1501 struct mvneta_tx_queue *txq = &pp->txqs[0]; 1502 struct mvneta_tx_desc *tx_desc; 1503 int sent_desc; 1504 u32 timeout = 0; 1505 1506 /* Get a descriptor for the first part of the packet */ 1507 tx_desc = mvneta_txq_next_desc_get(txq); 1508 1509 tx_desc->buf_phys_addr = (u32)ptr; 1510 tx_desc->data_size = len; 1511 flush_dcache_range((u32)ptr, (u32)ptr + len); 1512 1513 /* First and Last descriptor */ 1514 tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC; 1515 mvneta_txq_pend_desc_add(pp, txq, 1); 1516 1517 /* Wait for packet to be sent (queue might help with speed here) */ 1518 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1519 while (!sent_desc) { 1520 if (timeout++ > 10000) { 1521 printf("timeout: packet not sent\n"); 1522 return -1; 1523 } 1524 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1525 } 1526 1527 /* txDone has increased - hw sent packet */ 1528 mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1529 return 0; 1530 1531 return 0; 1532 } 1533 1534 static int mvneta_recv(struct eth_device *dev) 1535 { 1536 struct mvneta_port *pp = dev->priv; 1537 int rx_done; 1538 int packets_done; 1539 struct mvneta_rx_queue *rxq; 1540 1541 /* get rx queue */ 1542 rxq = mvneta_rxq_handle_get(pp, rxq_def); 1543 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1544 packets_done = rx_done; 1545 1546 while (packets_done--) { 1547 struct mvneta_rx_desc *rx_desc; 1548 unsigned char *data; 1549 u32 rx_status; 1550 int rx_bytes; 1551 1552 /* 1553 * No cache invalidation needed here, since the desc's are 1554 * located in a uncached memory region 1555 */ 1556 rx_desc = mvneta_rxq_next_desc_get(rxq); 1557 1558 rx_status = rx_desc->status; 1559 if (!mvneta_rxq_desc_is_first_last(rx_status) || 1560 (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 1561 mvneta_rx_error(pp, rx_desc); 1562 /* leave the descriptor untouched */ 1563 continue; 1564 } 1565 1566 /* 2 bytes for marvell header. 4 bytes for crc */ 1567 rx_bytes = rx_desc->data_size - 6; 1568 1569 /* give packet to stack - skip on first 2 bytes */ 1570 data = (u8 *)rx_desc->buf_cookie + 2; 1571 /* 1572 * No cache invalidation needed here, since the rx_buffer's are 1573 * located in a uncached memory region 1574 */ 1575 net_process_received_packet(data, rx_bytes); 1576 } 1577 1578 /* Update rxq management counters */ 1579 if (rx_done) 1580 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1581 1582 return 0; 1583 } 1584 1585 static void mvneta_halt(struct eth_device *dev) 1586 { 1587 struct mvneta_port *pp = dev->priv; 1588 1589 mvneta_port_down(pp); 1590 mvneta_port_disable(pp); 1591 } 1592 1593 int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr) 1594 { 1595 struct eth_device *dev; 1596 struct mvneta_port *pp; 1597 void *bd_space; 1598 1599 dev = calloc(1, sizeof(*dev)); 1600 if (dev == NULL) 1601 return -ENOMEM; 1602 1603 pp = calloc(1, sizeof(*pp)); 1604 if (pp == NULL) 1605 return -ENOMEM; 1606 1607 dev->priv = pp; 1608 1609 /* 1610 * Allocate buffer area for descs and rx_buffers. This is only 1611 * done once for all interfaces. As only one interface can 1612 * be active. Make this area DMA save by disabling the D-cache 1613 */ 1614 if (!buffer_loc.tx_descs) { 1615 /* Align buffer area for descs and rx_buffers to 1MiB */ 1616 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 1617 mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, 1618 DCACHE_OFF); 1619 buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space; 1620 buffer_loc.rx_descs = (struct mvneta_rx_desc *) 1621 ((u32)bd_space + 1622 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc)); 1623 buffer_loc.rx_buffers = (u32) 1624 (bd_space + 1625 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) + 1626 MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc)); 1627 } 1628 1629 sprintf(dev->name, "neta%d", devnum); 1630 1631 pp->base = (void __iomem *)base_addr; 1632 dev->iobase = base_addr; 1633 dev->init = mvneta_init_u_boot; 1634 dev->halt = mvneta_halt; 1635 dev->send = mvneta_send; 1636 dev->recv = mvneta_recv; 1637 dev->write_hwaddr = NULL; 1638 1639 /* 1640 * The PHY interface type is configured via the 1641 * board specific CONFIG_SYS_NETA_INTERFACE_TYPE 1642 * define. 1643 */ 1644 pp->phy_interface = CONFIG_SYS_NETA_INTERFACE_TYPE; 1645 1646 eth_register(dev); 1647 1648 pp->phyaddr = phy_addr; 1649 miiphy_register(dev->name, smi_reg_read, smi_reg_write); 1650 pp->bus = miiphy_get_dev_by_name(dev->name); 1651 1652 return 1; 1653 } 1654