1 /* 2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. 3 * 4 * U-Boot version: 5 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 6 * 7 * Based on the Linux version which is: 8 * Copyright (C) 2012 Marvell 9 * 10 * Rami Rosen <rosenr@marvell.com> 11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 12 * 13 * SPDX-License-Identifier: GPL-2.0 14 */ 15 16 #include <common.h> 17 #include <net.h> 18 #include <netdev.h> 19 #include <config.h> 20 #include <malloc.h> 21 #include <asm/io.h> 22 #include <asm/errno.h> 23 #include <phy.h> 24 #include <miiphy.h> 25 #include <watchdog.h> 26 #include <asm/arch/cpu.h> 27 #include <asm/arch/soc.h> 28 #include <linux/compat.h> 29 #include <linux/mbus.h> 30 31 #if !defined(CONFIG_PHYLIB) 32 # error Marvell mvneta requires PHYLIB 33 #endif 34 35 /* Some linux -> U-Boot compatibility stuff */ 36 #define netdev_err(dev, fmt, args...) \ 37 printf(fmt, ##args) 38 #define netdev_warn(dev, fmt, args...) \ 39 printf(fmt, ##args) 40 #define netdev_info(dev, fmt, args...) \ 41 printf(fmt, ##args) 42 43 #define CONFIG_NR_CPUS 1 44 #define ETH_HLEN 14 /* Total octets in header */ 45 46 /* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */ 47 #define WRAP (2 + ETH_HLEN + 4 + 32) 48 #define MTU 1500 49 #define RX_BUFFER_SIZE (ALIGN(MTU + WRAP, ARCH_DMA_MINALIGN)) 50 51 #define MVNETA_SMI_TIMEOUT 10000 52 53 /* Registers */ 54 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) 55 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1) 56 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) 57 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) 58 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) 59 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) 60 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) 61 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) 62 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 63 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) 64 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) 65 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff 66 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) 67 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 68 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 69 #define MVNETA_PORT_RX_RESET 0x1cc0 70 #define MVNETA_PORT_RX_DMA_RESET BIT(0) 71 #define MVNETA_PHY_ADDR 0x2000 72 #define MVNETA_PHY_ADDR_MASK 0x1f 73 #define MVNETA_SMI 0x2004 74 #define MVNETA_PHY_REG_MASK 0x1f 75 /* SMI register fields */ 76 #define MVNETA_SMI_DATA_OFFS 0 /* Data */ 77 #define MVNETA_SMI_DATA_MASK (0xffff << MVNETA_SMI_DATA_OFFS) 78 #define MVNETA_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ 79 #define MVNETA_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr*/ 80 #define MVNETA_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ 81 #define MVNETA_SMI_OPCODE_READ (1 << MVNETA_SMI_OPCODE_OFFS) 82 #define MVNETA_SMI_READ_VALID (1 << 27) /* Read Valid */ 83 #define MVNETA_SMI_BUSY (1 << 28) /* Busy */ 84 #define MVNETA_MBUS_RETRY 0x2010 85 #define MVNETA_UNIT_INTR_CAUSE 0x2080 86 #define MVNETA_UNIT_CONTROL 0x20B0 87 #define MVNETA_PHY_POLLING_ENABLE BIT(1) 88 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) 89 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) 90 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) 91 #define MVNETA_BASE_ADDR_ENABLE 0x2290 92 #define MVNETA_PORT_CONFIG 0x2400 93 #define MVNETA_UNI_PROMISC_MODE BIT(0) 94 #define MVNETA_DEF_RXQ(q) ((q) << 1) 95 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) 96 #define MVNETA_TX_UNSET_ERR_SUM BIT(12) 97 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) 98 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) 99 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) 100 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) 101 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ 102 MVNETA_DEF_RXQ_ARP(q) | \ 103 MVNETA_DEF_RXQ_TCP(q) | \ 104 MVNETA_DEF_RXQ_UDP(q) | \ 105 MVNETA_DEF_RXQ_BPDU(q) | \ 106 MVNETA_TX_UNSET_ERR_SUM | \ 107 MVNETA_RX_CSUM_WITH_PSEUDO_HDR) 108 #define MVNETA_PORT_CONFIG_EXTEND 0x2404 109 #define MVNETA_MAC_ADDR_LOW 0x2414 110 #define MVNETA_MAC_ADDR_HIGH 0x2418 111 #define MVNETA_SDMA_CONFIG 0x241c 112 #define MVNETA_SDMA_BRST_SIZE_16 4 113 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) 114 #define MVNETA_RX_NO_DATA_SWAP BIT(4) 115 #define MVNETA_TX_NO_DATA_SWAP BIT(5) 116 #define MVNETA_DESC_SWAP BIT(6) 117 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) 118 #define MVNETA_PORT_STATUS 0x2444 119 #define MVNETA_TX_IN_PRGRS BIT(1) 120 #define MVNETA_TX_FIFO_EMPTY BIT(8) 121 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c 122 #define MVNETA_SERDES_CFG 0x24A0 123 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 124 #define MVNETA_QSGMII_SERDES_PROTO 0x0667 125 #define MVNETA_TYPE_PRIO 0x24bc 126 #define MVNETA_FORCE_UNI BIT(21) 127 #define MVNETA_TXQ_CMD_1 0x24e4 128 #define MVNETA_TXQ_CMD 0x2448 129 #define MVNETA_TXQ_DISABLE_SHIFT 8 130 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff 131 #define MVNETA_ACC_MODE 0x2500 132 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) 133 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff 134 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 135 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) 136 137 /* Exception Interrupt Port/Queue Cause register */ 138 139 #define MVNETA_INTR_NEW_CAUSE 0x25a0 140 #define MVNETA_INTR_NEW_MASK 0x25a4 141 142 /* bits 0..7 = TXQ SENT, one bit per queue. 143 * bits 8..15 = RXQ OCCUP, one bit per queue. 144 * bits 16..23 = RXQ FREE, one bit per queue. 145 * bit 29 = OLD_REG_SUM, see old reg ? 146 * bit 30 = TX_ERR_SUM, one bit for 4 ports 147 * bit 31 = MISC_SUM, one bit for 4 ports 148 */ 149 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) 150 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) 151 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) 152 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) 153 154 #define MVNETA_INTR_OLD_CAUSE 0x25a8 155 #define MVNETA_INTR_OLD_MASK 0x25ac 156 157 /* Data Path Port/Queue Cause Register */ 158 #define MVNETA_INTR_MISC_CAUSE 0x25b0 159 #define MVNETA_INTR_MISC_MASK 0x25b4 160 #define MVNETA_INTR_ENABLE 0x25b8 161 162 #define MVNETA_RXQ_CMD 0x2680 163 #define MVNETA_RXQ_DISABLE_SHIFT 8 164 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff 165 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) 166 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) 167 #define MVNETA_GMAC_CTRL_0 0x2c00 168 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 169 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc 170 #define MVNETA_GMAC0_PORT_ENABLE BIT(0) 171 #define MVNETA_GMAC_CTRL_2 0x2c08 172 #define MVNETA_GMAC2_PCS_ENABLE BIT(3) 173 #define MVNETA_GMAC2_PORT_RGMII BIT(4) 174 #define MVNETA_GMAC2_PORT_RESET BIT(6) 175 #define MVNETA_GMAC_STATUS 0x2c10 176 #define MVNETA_GMAC_LINK_UP BIT(0) 177 #define MVNETA_GMAC_SPEED_1000 BIT(1) 178 #define MVNETA_GMAC_SPEED_100 BIT(2) 179 #define MVNETA_GMAC_FULL_DUPLEX BIT(3) 180 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) 181 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) 182 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) 183 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) 184 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c 185 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) 186 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) 187 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) 188 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) 189 #define MVNETA_GMAC_AN_SPEED_EN BIT(7) 190 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) 191 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) 192 #define MVNETA_MIB_COUNTERS_BASE 0x3080 193 #define MVNETA_MIB_LATE_COLLISION 0x7c 194 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 195 #define MVNETA_DA_FILT_OTH_MCAST 0x3500 196 #define MVNETA_DA_FILT_UCAST_BASE 0x3600 197 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) 198 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) 199 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 200 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) 201 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) 202 #define MVNETA_TXQ_DEC_SENT_SHIFT 16 203 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) 204 #define MVNETA_TXQ_SENT_DESC_SHIFT 16 205 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 206 #define MVNETA_PORT_TX_RESET 0x3cf0 207 #define MVNETA_PORT_TX_DMA_RESET BIT(0) 208 #define MVNETA_TX_MTU 0x3e0c 209 #define MVNETA_TX_TOKEN_SIZE 0x3e14 210 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff 211 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) 212 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff 213 214 /* Descriptor ring Macros */ 215 #define MVNETA_QUEUE_NEXT_DESC(q, index) \ 216 (((index) < (q)->last_desc) ? ((index) + 1) : 0) 217 218 /* Various constants */ 219 220 /* Coalescing */ 221 #define MVNETA_TXDONE_COAL_PKTS 16 222 #define MVNETA_RX_COAL_PKTS 32 223 #define MVNETA_RX_COAL_USEC 100 224 225 /* The two bytes Marvell header. Either contains a special value used 226 * by Marvell switches when a specific hardware mode is enabled (not 227 * supported by this driver) or is filled automatically by zeroes on 228 * the RX side. Those two bytes being at the front of the Ethernet 229 * header, they allow to have the IP header aligned on a 4 bytes 230 * boundary automatically: the hardware skips those two bytes on its 231 * own. 232 */ 233 #define MVNETA_MH_SIZE 2 234 235 #define MVNETA_VLAN_TAG_LEN 4 236 237 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 238 #define MVNETA_TX_CSUM_MAX_SIZE 9800 239 #define MVNETA_ACC_MODE_EXT 1 240 241 /* Timeout constants */ 242 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 243 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 244 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 245 246 #define MVNETA_TX_MTU_MAX 0x3ffff 247 248 /* Max number of Rx descriptors */ 249 #define MVNETA_MAX_RXD 16 250 251 /* Max number of Tx descriptors */ 252 #define MVNETA_MAX_TXD 16 253 254 /* descriptor aligned size */ 255 #define MVNETA_DESC_ALIGNED_SIZE 32 256 257 struct mvneta_port { 258 void __iomem *base; 259 struct mvneta_rx_queue *rxqs; 260 struct mvneta_tx_queue *txqs; 261 262 u8 mcast_count[256]; 263 u16 tx_ring_size; 264 u16 rx_ring_size; 265 266 phy_interface_t phy_interface; 267 unsigned int link; 268 unsigned int duplex; 269 unsigned int speed; 270 271 int init; 272 int phyaddr; 273 struct phy_device *phydev; 274 struct mii_dev *bus; 275 }; 276 277 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the 278 * layout of the transmit and reception DMA descriptors, and their 279 * layout is therefore defined by the hardware design 280 */ 281 282 #define MVNETA_TX_L3_OFF_SHIFT 0 283 #define MVNETA_TX_IP_HLEN_SHIFT 8 284 #define MVNETA_TX_L4_UDP BIT(16) 285 #define MVNETA_TX_L3_IP6 BIT(17) 286 #define MVNETA_TXD_IP_CSUM BIT(18) 287 #define MVNETA_TXD_Z_PAD BIT(19) 288 #define MVNETA_TXD_L_DESC BIT(20) 289 #define MVNETA_TXD_F_DESC BIT(21) 290 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ 291 MVNETA_TXD_L_DESC | \ 292 MVNETA_TXD_F_DESC) 293 #define MVNETA_TX_L4_CSUM_FULL BIT(30) 294 #define MVNETA_TX_L4_CSUM_NOT BIT(31) 295 296 #define MVNETA_RXD_ERR_CRC 0x0 297 #define MVNETA_RXD_ERR_SUMMARY BIT(16) 298 #define MVNETA_RXD_ERR_OVERRUN BIT(17) 299 #define MVNETA_RXD_ERR_LEN BIT(18) 300 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) 301 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) 302 #define MVNETA_RXD_L3_IP4 BIT(25) 303 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) 304 #define MVNETA_RXD_L4_CSUM_OK BIT(30) 305 306 struct mvneta_tx_desc { 307 u32 command; /* Options used by HW for packet transmitting.*/ 308 u16 reserverd1; /* csum_l4 (for future use) */ 309 u16 data_size; /* Data size of transmitted packet in bytes */ 310 u32 buf_phys_addr; /* Physical addr of transmitted buffer */ 311 u32 reserved2; /* hw_cmd - (for future use, PMT) */ 312 u32 reserved3[4]; /* Reserved - (for future use) */ 313 }; 314 315 struct mvneta_rx_desc { 316 u32 status; /* Info about received packet */ 317 u16 reserved1; /* pnc_info - (for future use, PnC) */ 318 u16 data_size; /* Size of received packet in bytes */ 319 320 u32 buf_phys_addr; /* Physical address of the buffer */ 321 u32 reserved2; /* pnc_flow_id (for future use, PnC) */ 322 323 u32 buf_cookie; /* cookie for access to RX buffer in rx path */ 324 u16 reserved3; /* prefetch_cmd, for future use */ 325 u16 reserved4; /* csum_l4 - (for future use, PnC) */ 326 327 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ 328 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ 329 }; 330 331 struct mvneta_tx_queue { 332 /* Number of this TX queue, in the range 0-7 */ 333 u8 id; 334 335 /* Number of TX DMA descriptors in the descriptor ring */ 336 int size; 337 338 /* Index of last TX DMA descriptor that was inserted */ 339 int txq_put_index; 340 341 /* Index of the TX DMA descriptor to be cleaned up */ 342 int txq_get_index; 343 344 /* Virtual address of the TX DMA descriptors array */ 345 struct mvneta_tx_desc *descs; 346 347 /* DMA address of the TX DMA descriptors array */ 348 dma_addr_t descs_phys; 349 350 /* Index of the last TX DMA descriptor */ 351 int last_desc; 352 353 /* Index of the next TX DMA descriptor to process */ 354 int next_desc_to_proc; 355 }; 356 357 struct mvneta_rx_queue { 358 /* rx queue number, in the range 0-7 */ 359 u8 id; 360 361 /* num of rx descriptors in the rx descriptor ring */ 362 int size; 363 364 /* Virtual address of the RX DMA descriptors array */ 365 struct mvneta_rx_desc *descs; 366 367 /* DMA address of the RX DMA descriptors array */ 368 dma_addr_t descs_phys; 369 370 /* Index of the last RX DMA descriptor */ 371 int last_desc; 372 373 /* Index of the next RX DMA descriptor to process */ 374 int next_desc_to_proc; 375 }; 376 377 /* U-Boot doesn't use the queues, so set the number to 1 */ 378 static int rxq_number = 1; 379 static int txq_number = 1; 380 static int rxq_def; 381 382 struct buffer_location { 383 struct mvneta_tx_desc *tx_descs; 384 struct mvneta_rx_desc *rx_descs; 385 u32 rx_buffers; 386 }; 387 388 /* 389 * All 4 interfaces use the same global buffer, since only one interface 390 * can be enabled at once 391 */ 392 static struct buffer_location buffer_loc; 393 394 /* 395 * Page table entries are set to 1MB, or multiples of 1MB 396 * (not < 1MB). driver uses less bd's so use 1MB bdspace. 397 */ 398 #define BD_SPACE (1 << 20) 399 400 /* Utility/helper methods */ 401 402 /* Write helper method */ 403 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) 404 { 405 writel(data, pp->base + offset); 406 } 407 408 /* Read helper method */ 409 static u32 mvreg_read(struct mvneta_port *pp, u32 offset) 410 { 411 return readl(pp->base + offset); 412 } 413 414 /* Clear all MIB counters */ 415 static void mvneta_mib_counters_clear(struct mvneta_port *pp) 416 { 417 int i; 418 419 /* Perform dummy reads from MIB counters */ 420 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) 421 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); 422 } 423 424 /* Rx descriptors helper methods */ 425 426 /* Checks whether the RX descriptor having this status is both the first 427 * and the last descriptor for the RX packet. Each RX packet is currently 428 * received through a single RX descriptor, so not having each RX 429 * descriptor with its first and last bits set is an error 430 */ 431 static int mvneta_rxq_desc_is_first_last(u32 status) 432 { 433 return (status & MVNETA_RXD_FIRST_LAST_DESC) == 434 MVNETA_RXD_FIRST_LAST_DESC; 435 } 436 437 /* Add number of descriptors ready to receive new packets */ 438 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, 439 struct mvneta_rx_queue *rxq, 440 int ndescs) 441 { 442 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can 443 * be added at once 444 */ 445 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { 446 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 447 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << 448 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 449 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; 450 } 451 452 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), 453 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); 454 } 455 456 /* Get number of RX descriptors occupied by received packets */ 457 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, 458 struct mvneta_rx_queue *rxq) 459 { 460 u32 val; 461 462 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); 463 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; 464 } 465 466 /* Update num of rx desc called upon return from rx path or 467 * from mvneta_rxq_drop_pkts(). 468 */ 469 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, 470 struct mvneta_rx_queue *rxq, 471 int rx_done, int rx_filled) 472 { 473 u32 val; 474 475 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { 476 val = rx_done | 477 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); 478 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 479 return; 480 } 481 482 /* Only 255 descriptors can be added at once */ 483 while ((rx_done > 0) || (rx_filled > 0)) { 484 if (rx_done <= 0xff) { 485 val = rx_done; 486 rx_done = 0; 487 } else { 488 val = 0xff; 489 rx_done -= 0xff; 490 } 491 if (rx_filled <= 0xff) { 492 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 493 rx_filled = 0; 494 } else { 495 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; 496 rx_filled -= 0xff; 497 } 498 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); 499 } 500 } 501 502 /* Get pointer to next RX descriptor to be processed by SW */ 503 static struct mvneta_rx_desc * 504 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) 505 { 506 int rx_desc = rxq->next_desc_to_proc; 507 508 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); 509 return rxq->descs + rx_desc; 510 } 511 512 /* Tx descriptors helper methods */ 513 514 /* Update HW with number of TX descriptors to be sent */ 515 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, 516 struct mvneta_tx_queue *txq, 517 int pend_desc) 518 { 519 u32 val; 520 521 /* Only 255 descriptors can be added at once ; Assume caller 522 * process TX desriptors in quanta less than 256 523 */ 524 val = pend_desc; 525 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 526 } 527 528 /* Get pointer to next TX descriptor to be processed (send) by HW */ 529 static struct mvneta_tx_desc * 530 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) 531 { 532 int tx_desc = txq->next_desc_to_proc; 533 534 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); 535 return txq->descs + tx_desc; 536 } 537 538 /* Set rxq buf size */ 539 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, 540 struct mvneta_rx_queue *rxq, 541 int buf_size) 542 { 543 u32 val; 544 545 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); 546 547 val &= ~MVNETA_RXQ_BUF_SIZE_MASK; 548 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); 549 550 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); 551 } 552 553 /* Start the Ethernet port RX and TX activity */ 554 static void mvneta_port_up(struct mvneta_port *pp) 555 { 556 int queue; 557 u32 q_map; 558 559 /* Enable all initialized TXs. */ 560 mvneta_mib_counters_clear(pp); 561 q_map = 0; 562 for (queue = 0; queue < txq_number; queue++) { 563 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 564 if (txq->descs != NULL) 565 q_map |= (1 << queue); 566 } 567 mvreg_write(pp, MVNETA_TXQ_CMD, q_map); 568 569 /* Enable all initialized RXQs. */ 570 q_map = 0; 571 for (queue = 0; queue < rxq_number; queue++) { 572 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 573 if (rxq->descs != NULL) 574 q_map |= (1 << queue); 575 } 576 mvreg_write(pp, MVNETA_RXQ_CMD, q_map); 577 } 578 579 /* Stop the Ethernet port activity */ 580 static void mvneta_port_down(struct mvneta_port *pp) 581 { 582 u32 val; 583 int count; 584 585 /* Stop Rx port activity. Check port Rx activity. */ 586 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; 587 588 /* Issue stop command for active channels only */ 589 if (val != 0) 590 mvreg_write(pp, MVNETA_RXQ_CMD, 591 val << MVNETA_RXQ_DISABLE_SHIFT); 592 593 /* Wait for all Rx activity to terminate. */ 594 count = 0; 595 do { 596 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { 597 netdev_warn(pp->dev, 598 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", 599 val); 600 break; 601 } 602 mdelay(1); 603 604 val = mvreg_read(pp, MVNETA_RXQ_CMD); 605 } while (val & 0xff); 606 607 /* Stop Tx port activity. Check port Tx activity. Issue stop 608 * command for active channels only 609 */ 610 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; 611 612 if (val != 0) 613 mvreg_write(pp, MVNETA_TXQ_CMD, 614 (val << MVNETA_TXQ_DISABLE_SHIFT)); 615 616 /* Wait for all Tx activity to terminate. */ 617 count = 0; 618 do { 619 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { 620 netdev_warn(pp->dev, 621 "TIMEOUT for TX stopped status=0x%08x\n", 622 val); 623 break; 624 } 625 mdelay(1); 626 627 /* Check TX Command reg that all Txqs are stopped */ 628 val = mvreg_read(pp, MVNETA_TXQ_CMD); 629 630 } while (val & 0xff); 631 632 /* Double check to verify that TX FIFO is empty */ 633 count = 0; 634 do { 635 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { 636 netdev_warn(pp->dev, 637 "TX FIFO empty timeout status=0x08%x\n", 638 val); 639 break; 640 } 641 mdelay(1); 642 643 val = mvreg_read(pp, MVNETA_PORT_STATUS); 644 } while (!(val & MVNETA_TX_FIFO_EMPTY) && 645 (val & MVNETA_TX_IN_PRGRS)); 646 647 udelay(200); 648 } 649 650 /* Enable the port by setting the port enable bit of the MAC control register */ 651 static void mvneta_port_enable(struct mvneta_port *pp) 652 { 653 u32 val; 654 655 /* Enable port */ 656 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 657 val |= MVNETA_GMAC0_PORT_ENABLE; 658 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 659 } 660 661 /* Disable the port and wait for about 200 usec before retuning */ 662 static void mvneta_port_disable(struct mvneta_port *pp) 663 { 664 u32 val; 665 666 /* Reset the Enable bit in the Serial Control Register */ 667 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); 668 val &= ~MVNETA_GMAC0_PORT_ENABLE; 669 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); 670 671 udelay(200); 672 } 673 674 /* Multicast tables methods */ 675 676 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ 677 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) 678 { 679 int offset; 680 u32 val; 681 682 if (queue == -1) { 683 val = 0; 684 } else { 685 val = 0x1 | (queue << 1); 686 val |= (val << 24) | (val << 16) | (val << 8); 687 } 688 689 for (offset = 0; offset <= 0xc; offset += 4) 690 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); 691 } 692 693 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ 694 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) 695 { 696 int offset; 697 u32 val; 698 699 if (queue == -1) { 700 val = 0; 701 } else { 702 val = 0x1 | (queue << 1); 703 val |= (val << 24) | (val << 16) | (val << 8); 704 } 705 706 for (offset = 0; offset <= 0xfc; offset += 4) 707 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); 708 } 709 710 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ 711 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) 712 { 713 int offset; 714 u32 val; 715 716 if (queue == -1) { 717 memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); 718 val = 0; 719 } else { 720 memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); 721 val = 0x1 | (queue << 1); 722 val |= (val << 24) | (val << 16) | (val << 8); 723 } 724 725 for (offset = 0; offset <= 0xfc; offset += 4) 726 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); 727 } 728 729 /* This method sets defaults to the NETA port: 730 * Clears interrupt Cause and Mask registers. 731 * Clears all MAC tables. 732 * Sets defaults to all registers. 733 * Resets RX and TX descriptor rings. 734 * Resets PHY. 735 * This method can be called after mvneta_port_down() to return the port 736 * settings to defaults. 737 */ 738 static void mvneta_defaults_set(struct mvneta_port *pp) 739 { 740 int cpu; 741 int queue; 742 u32 val; 743 744 /* Clear all Cause registers */ 745 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); 746 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); 747 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); 748 749 /* Mask all interrupts */ 750 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); 751 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); 752 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); 753 mvreg_write(pp, MVNETA_INTR_ENABLE, 0); 754 755 /* Enable MBUS Retry bit16 */ 756 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); 757 758 /* Set CPU queue access map - all CPUs have access to all RX 759 * queues and to all TX queues 760 */ 761 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) 762 mvreg_write(pp, MVNETA_CPU_MAP(cpu), 763 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK | 764 MVNETA_CPU_TXQ_ACCESS_ALL_MASK)); 765 766 /* Reset RX and TX DMAs */ 767 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); 768 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); 769 770 /* Disable Legacy WRR, Disable EJP, Release from reset */ 771 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); 772 for (queue = 0; queue < txq_number; queue++) { 773 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); 774 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); 775 } 776 777 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); 778 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); 779 780 /* Set Port Acceleration Mode */ 781 val = MVNETA_ACC_MODE_EXT; 782 mvreg_write(pp, MVNETA_ACC_MODE, val); 783 784 /* Update val of portCfg register accordingly with all RxQueue types */ 785 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def); 786 mvreg_write(pp, MVNETA_PORT_CONFIG, val); 787 788 val = 0; 789 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); 790 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); 791 792 /* Build PORT_SDMA_CONFIG_REG */ 793 val = 0; 794 795 /* Default burst size */ 796 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 797 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); 798 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; 799 800 /* Assign port SDMA configuration */ 801 mvreg_write(pp, MVNETA_SDMA_CONFIG, val); 802 803 /* Enable PHY polling in hardware for U-Boot */ 804 val = mvreg_read(pp, MVNETA_UNIT_CONTROL); 805 val |= MVNETA_PHY_POLLING_ENABLE; 806 mvreg_write(pp, MVNETA_UNIT_CONTROL, val); 807 808 mvneta_set_ucast_table(pp, -1); 809 mvneta_set_special_mcast_table(pp, -1); 810 mvneta_set_other_mcast_table(pp, -1); 811 } 812 813 /* Set unicast address */ 814 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, 815 int queue) 816 { 817 unsigned int unicast_reg; 818 unsigned int tbl_offset; 819 unsigned int reg_offset; 820 821 /* Locate the Unicast table entry */ 822 last_nibble = (0xf & last_nibble); 823 824 /* offset from unicast tbl base */ 825 tbl_offset = (last_nibble / 4) * 4; 826 827 /* offset within the above reg */ 828 reg_offset = last_nibble % 4; 829 830 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); 831 832 if (queue == -1) { 833 /* Clear accepts frame bit at specified unicast DA tbl entry */ 834 unicast_reg &= ~(0xff << (8 * reg_offset)); 835 } else { 836 unicast_reg &= ~(0xff << (8 * reg_offset)); 837 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); 838 } 839 840 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); 841 } 842 843 /* Set mac address */ 844 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, 845 int queue) 846 { 847 unsigned int mac_h; 848 unsigned int mac_l; 849 850 if (queue != -1) { 851 mac_l = (addr[4] << 8) | (addr[5]); 852 mac_h = (addr[0] << 24) | (addr[1] << 16) | 853 (addr[2] << 8) | (addr[3] << 0); 854 855 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); 856 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); 857 } 858 859 /* Accept frames of this address */ 860 mvneta_set_ucast_addr(pp, addr[5], queue); 861 } 862 863 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ 864 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, 865 u32 phys_addr, u32 cookie) 866 { 867 rx_desc->buf_cookie = cookie; 868 rx_desc->buf_phys_addr = phys_addr; 869 } 870 871 /* Decrement sent descriptors counter */ 872 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, 873 struct mvneta_tx_queue *txq, 874 int sent_desc) 875 { 876 u32 val; 877 878 /* Only 255 TX descriptors can be updated at once */ 879 while (sent_desc > 0xff) { 880 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; 881 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 882 sent_desc = sent_desc - 0xff; 883 } 884 885 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; 886 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); 887 } 888 889 /* Get number of TX descriptors already sent by HW */ 890 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, 891 struct mvneta_tx_queue *txq) 892 { 893 u32 val; 894 int sent_desc; 895 896 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); 897 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> 898 MVNETA_TXQ_SENT_DESC_SHIFT; 899 900 return sent_desc; 901 } 902 903 /* Display more error info */ 904 static void mvneta_rx_error(struct mvneta_port *pp, 905 struct mvneta_rx_desc *rx_desc) 906 { 907 u32 status = rx_desc->status; 908 909 if (!mvneta_rxq_desc_is_first_last(status)) { 910 netdev_err(pp->dev, 911 "bad rx status %08x (buffer oversize), size=%d\n", 912 status, rx_desc->data_size); 913 return; 914 } 915 916 switch (status & MVNETA_RXD_ERR_CODE_MASK) { 917 case MVNETA_RXD_ERR_CRC: 918 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", 919 status, rx_desc->data_size); 920 break; 921 case MVNETA_RXD_ERR_OVERRUN: 922 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", 923 status, rx_desc->data_size); 924 break; 925 case MVNETA_RXD_ERR_LEN: 926 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", 927 status, rx_desc->data_size); 928 break; 929 case MVNETA_RXD_ERR_RESOURCE: 930 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", 931 status, rx_desc->data_size); 932 break; 933 } 934 } 935 936 static struct mvneta_rx_queue *mvneta_rxq_handle_get(struct mvneta_port *pp, 937 int rxq) 938 { 939 return &pp->rxqs[rxq]; 940 } 941 942 943 /* Drop packets received by the RXQ and free buffers */ 944 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, 945 struct mvneta_rx_queue *rxq) 946 { 947 int rx_done; 948 949 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 950 if (rx_done) 951 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 952 } 953 954 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ 955 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, 956 int num) 957 { 958 int i; 959 960 for (i = 0; i < num; i++) { 961 u32 addr; 962 963 /* U-Boot special: Fill in the rx buffer addresses */ 964 addr = buffer_loc.rx_buffers + (i * RX_BUFFER_SIZE); 965 mvneta_rx_desc_fill(rxq->descs + i, addr, addr); 966 } 967 968 /* Add this number of RX descriptors as non occupied (ready to 969 * get packets) 970 */ 971 mvneta_rxq_non_occup_desc_add(pp, rxq, i); 972 973 return 0; 974 } 975 976 /* Rx/Tx queue initialization/cleanup methods */ 977 978 /* Create a specified RX queue */ 979 static int mvneta_rxq_init(struct mvneta_port *pp, 980 struct mvneta_rx_queue *rxq) 981 982 { 983 rxq->size = pp->rx_ring_size; 984 985 /* Allocate memory for RX descriptors */ 986 rxq->descs_phys = (dma_addr_t)rxq->descs; 987 if (rxq->descs == NULL) 988 return -ENOMEM; 989 990 rxq->last_desc = rxq->size - 1; 991 992 /* Set Rx descriptors queue starting address */ 993 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); 994 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); 995 996 /* Fill RXQ with buffers from RX pool */ 997 mvneta_rxq_buf_size_set(pp, rxq, RX_BUFFER_SIZE); 998 mvneta_rxq_fill(pp, rxq, rxq->size); 999 1000 return 0; 1001 } 1002 1003 /* Cleanup Rx queue */ 1004 static void mvneta_rxq_deinit(struct mvneta_port *pp, 1005 struct mvneta_rx_queue *rxq) 1006 { 1007 mvneta_rxq_drop_pkts(pp, rxq); 1008 1009 rxq->descs = NULL; 1010 rxq->last_desc = 0; 1011 rxq->next_desc_to_proc = 0; 1012 rxq->descs_phys = 0; 1013 } 1014 1015 /* Create and initialize a tx queue */ 1016 static int mvneta_txq_init(struct mvneta_port *pp, 1017 struct mvneta_tx_queue *txq) 1018 { 1019 txq->size = pp->tx_ring_size; 1020 1021 /* Allocate memory for TX descriptors */ 1022 txq->descs_phys = (u32)txq->descs; 1023 if (txq->descs == NULL) 1024 return -ENOMEM; 1025 1026 txq->last_desc = txq->size - 1; 1027 1028 /* Set maximum bandwidth for enabled TXQs */ 1029 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); 1030 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); 1031 1032 /* Set Tx descriptors queue starting address */ 1033 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); 1034 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); 1035 1036 return 0; 1037 } 1038 1039 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ 1040 static void mvneta_txq_deinit(struct mvneta_port *pp, 1041 struct mvneta_tx_queue *txq) 1042 { 1043 txq->descs = NULL; 1044 txq->last_desc = 0; 1045 txq->next_desc_to_proc = 0; 1046 txq->descs_phys = 0; 1047 1048 /* Set minimum bandwidth for disabled TXQs */ 1049 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); 1050 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); 1051 1052 /* Set Tx descriptors queue starting address and size */ 1053 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); 1054 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); 1055 } 1056 1057 /* Cleanup all Tx queues */ 1058 static void mvneta_cleanup_txqs(struct mvneta_port *pp) 1059 { 1060 int queue; 1061 1062 for (queue = 0; queue < txq_number; queue++) 1063 mvneta_txq_deinit(pp, &pp->txqs[queue]); 1064 } 1065 1066 /* Cleanup all Rx queues */ 1067 static void mvneta_cleanup_rxqs(struct mvneta_port *pp) 1068 { 1069 int queue; 1070 1071 for (queue = 0; queue < rxq_number; queue++) 1072 mvneta_rxq_deinit(pp, &pp->rxqs[queue]); 1073 } 1074 1075 1076 /* Init all Rx queues */ 1077 static int mvneta_setup_rxqs(struct mvneta_port *pp) 1078 { 1079 int queue; 1080 1081 for (queue = 0; queue < rxq_number; queue++) { 1082 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); 1083 if (err) { 1084 netdev_err(pp->dev, "%s: can't create rxq=%d\n", 1085 __func__, queue); 1086 mvneta_cleanup_rxqs(pp); 1087 return err; 1088 } 1089 } 1090 1091 return 0; 1092 } 1093 1094 /* Init all tx queues */ 1095 static int mvneta_setup_txqs(struct mvneta_port *pp) 1096 { 1097 int queue; 1098 1099 for (queue = 0; queue < txq_number; queue++) { 1100 int err = mvneta_txq_init(pp, &pp->txqs[queue]); 1101 if (err) { 1102 netdev_err(pp->dev, "%s: can't create txq=%d\n", 1103 __func__, queue); 1104 mvneta_cleanup_txqs(pp); 1105 return err; 1106 } 1107 } 1108 1109 return 0; 1110 } 1111 1112 static void mvneta_start_dev(struct mvneta_port *pp) 1113 { 1114 /* start the Rx/Tx activity */ 1115 mvneta_port_enable(pp); 1116 } 1117 1118 static void mvneta_adjust_link(struct eth_device *dev) 1119 { 1120 struct mvneta_port *pp = dev->priv; 1121 struct phy_device *phydev = pp->phydev; 1122 int status_change = 0; 1123 1124 if (phydev->link) { 1125 if ((pp->speed != phydev->speed) || 1126 (pp->duplex != phydev->duplex)) { 1127 u32 val; 1128 1129 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 1130 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | 1131 MVNETA_GMAC_CONFIG_GMII_SPEED | 1132 MVNETA_GMAC_CONFIG_FULL_DUPLEX | 1133 MVNETA_GMAC_AN_SPEED_EN | 1134 MVNETA_GMAC_AN_DUPLEX_EN); 1135 1136 if (phydev->duplex) 1137 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; 1138 1139 if (phydev->speed == SPEED_1000) 1140 val |= MVNETA_GMAC_CONFIG_GMII_SPEED; 1141 else 1142 val |= MVNETA_GMAC_CONFIG_MII_SPEED; 1143 1144 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1145 1146 pp->duplex = phydev->duplex; 1147 pp->speed = phydev->speed; 1148 } 1149 } 1150 1151 if (phydev->link != pp->link) { 1152 if (!phydev->link) { 1153 pp->duplex = -1; 1154 pp->speed = 0; 1155 } 1156 1157 pp->link = phydev->link; 1158 status_change = 1; 1159 } 1160 1161 if (status_change) { 1162 if (phydev->link) { 1163 u32 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); 1164 val |= (MVNETA_GMAC_FORCE_LINK_PASS | 1165 MVNETA_GMAC_FORCE_LINK_DOWN); 1166 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); 1167 mvneta_port_up(pp); 1168 } else { 1169 mvneta_port_down(pp); 1170 } 1171 } 1172 } 1173 1174 static int mvneta_open(struct eth_device *dev) 1175 { 1176 struct mvneta_port *pp = dev->priv; 1177 int ret; 1178 1179 ret = mvneta_setup_rxqs(pp); 1180 if (ret) 1181 return ret; 1182 1183 ret = mvneta_setup_txqs(pp); 1184 if (ret) 1185 return ret; 1186 1187 mvneta_adjust_link(dev); 1188 1189 mvneta_start_dev(pp); 1190 1191 return 0; 1192 } 1193 1194 /* Initialize hw */ 1195 static int mvneta_init(struct mvneta_port *pp) 1196 { 1197 int queue; 1198 1199 /* Disable port */ 1200 mvneta_port_disable(pp); 1201 1202 /* Set port default values */ 1203 mvneta_defaults_set(pp); 1204 1205 pp->txqs = kzalloc(txq_number * sizeof(struct mvneta_tx_queue), 1206 GFP_KERNEL); 1207 if (!pp->txqs) 1208 return -ENOMEM; 1209 1210 /* U-Boot special: use preallocated area */ 1211 pp->txqs[0].descs = buffer_loc.tx_descs; 1212 1213 /* Initialize TX descriptor rings */ 1214 for (queue = 0; queue < txq_number; queue++) { 1215 struct mvneta_tx_queue *txq = &pp->txqs[queue]; 1216 txq->id = queue; 1217 txq->size = pp->tx_ring_size; 1218 } 1219 1220 pp->rxqs = kzalloc(rxq_number * sizeof(struct mvneta_rx_queue), 1221 GFP_KERNEL); 1222 if (!pp->rxqs) { 1223 kfree(pp->txqs); 1224 return -ENOMEM; 1225 } 1226 1227 /* U-Boot special: use preallocated area */ 1228 pp->rxqs[0].descs = buffer_loc.rx_descs; 1229 1230 /* Create Rx descriptor rings */ 1231 for (queue = 0; queue < rxq_number; queue++) { 1232 struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; 1233 rxq->id = queue; 1234 rxq->size = pp->rx_ring_size; 1235 } 1236 1237 return 0; 1238 } 1239 1240 /* platform glue : initialize decoding windows */ 1241 static void mvneta_conf_mbus_windows(struct mvneta_port *pp) 1242 { 1243 const struct mbus_dram_target_info *dram; 1244 u32 win_enable; 1245 u32 win_protect; 1246 int i; 1247 1248 dram = mvebu_mbus_dram_info(); 1249 for (i = 0; i < 6; i++) { 1250 mvreg_write(pp, MVNETA_WIN_BASE(i), 0); 1251 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); 1252 1253 if (i < 4) 1254 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); 1255 } 1256 1257 win_enable = 0x3f; 1258 win_protect = 0; 1259 1260 for (i = 0; i < dram->num_cs; i++) { 1261 const struct mbus_dram_window *cs = dram->cs + i; 1262 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | 1263 (cs->mbus_attr << 8) | dram->mbus_dram_target_id); 1264 1265 mvreg_write(pp, MVNETA_WIN_SIZE(i), 1266 (cs->size - 1) & 0xffff0000); 1267 1268 win_enable &= ~(1 << i); 1269 win_protect |= 3 << (2 * i); 1270 } 1271 1272 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); 1273 } 1274 1275 /* Power up the port */ 1276 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) 1277 { 1278 u32 ctrl; 1279 1280 /* MAC Cause register should be cleared */ 1281 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); 1282 1283 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); 1284 1285 /* Even though it might look weird, when we're configured in 1286 * SGMII or QSGMII mode, the RGMII bit needs to be set. 1287 */ 1288 switch (phy_mode) { 1289 case PHY_INTERFACE_MODE_QSGMII: 1290 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); 1291 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 1292 break; 1293 case PHY_INTERFACE_MODE_SGMII: 1294 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); 1295 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; 1296 break; 1297 case PHY_INTERFACE_MODE_RGMII: 1298 case PHY_INTERFACE_MODE_RGMII_ID: 1299 ctrl |= MVNETA_GMAC2_PORT_RGMII; 1300 break; 1301 default: 1302 return -EINVAL; 1303 } 1304 1305 /* Cancel Port Reset */ 1306 ctrl &= ~MVNETA_GMAC2_PORT_RESET; 1307 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); 1308 1309 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & 1310 MVNETA_GMAC2_PORT_RESET) != 0) 1311 continue; 1312 1313 return 0; 1314 } 1315 1316 /* Device initialization routine */ 1317 static int mvneta_probe(struct eth_device *dev) 1318 { 1319 struct mvneta_port *pp = dev->priv; 1320 int err; 1321 1322 pp->tx_ring_size = MVNETA_MAX_TXD; 1323 pp->rx_ring_size = MVNETA_MAX_RXD; 1324 1325 err = mvneta_init(pp); 1326 if (err < 0) { 1327 dev_err(&pdev->dev, "can't init eth hal\n"); 1328 return err; 1329 } 1330 1331 mvneta_conf_mbus_windows(pp); 1332 1333 mvneta_mac_addr_set(pp, dev->enetaddr, rxq_def); 1334 1335 err = mvneta_port_power_up(pp, pp->phy_interface); 1336 if (err < 0) { 1337 dev_err(&pdev->dev, "can't power up port\n"); 1338 return err; 1339 } 1340 1341 /* Call open() now as it needs to be done before runing send() */ 1342 mvneta_open(dev); 1343 1344 return 0; 1345 } 1346 1347 /* U-Boot only functions follow here */ 1348 1349 /* SMI / MDIO functions */ 1350 1351 static int smi_wait_ready(struct mvneta_port *pp) 1352 { 1353 u32 timeout = MVNETA_SMI_TIMEOUT; 1354 u32 smi_reg; 1355 1356 /* wait till the SMI is not busy */ 1357 do { 1358 /* read smi register */ 1359 smi_reg = mvreg_read(pp, MVNETA_SMI); 1360 if (timeout-- == 0) { 1361 printf("Error: SMI busy timeout\n"); 1362 return -EFAULT; 1363 } 1364 } while (smi_reg & MVNETA_SMI_BUSY); 1365 1366 return 0; 1367 } 1368 1369 /* 1370 * smi_reg_read - miiphy_read callback function. 1371 * 1372 * Returns 16bit phy register value, or 0xffff on error 1373 */ 1374 static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) 1375 { 1376 struct eth_device *dev = eth_get_dev_by_name(devname); 1377 struct mvneta_port *pp = dev->priv; 1378 u32 smi_reg; 1379 u32 timeout; 1380 1381 /* check parameters */ 1382 if (phy_adr > MVNETA_PHY_ADDR_MASK) { 1383 printf("Error: Invalid PHY address %d\n", phy_adr); 1384 return -EFAULT; 1385 } 1386 1387 if (reg_ofs > MVNETA_PHY_REG_MASK) { 1388 printf("Err: Invalid register offset %d\n", reg_ofs); 1389 return -EFAULT; 1390 } 1391 1392 /* wait till the SMI is not busy */ 1393 if (smi_wait_ready(pp) < 0) 1394 return -EFAULT; 1395 1396 /* fill the phy address and regiser offset and read opcode */ 1397 smi_reg = (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS) 1398 | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS) 1399 | MVNETA_SMI_OPCODE_READ; 1400 1401 /* write the smi register */ 1402 mvreg_write(pp, MVNETA_SMI, smi_reg); 1403 1404 /*wait till read value is ready */ 1405 timeout = MVNETA_SMI_TIMEOUT; 1406 1407 do { 1408 /* read smi register */ 1409 smi_reg = mvreg_read(pp, MVNETA_SMI); 1410 if (timeout-- == 0) { 1411 printf("Err: SMI read ready timeout\n"); 1412 return -EFAULT; 1413 } 1414 } while (!(smi_reg & MVNETA_SMI_READ_VALID)); 1415 1416 /* Wait for the data to update in the SMI register */ 1417 for (timeout = 0; timeout < MVNETA_SMI_TIMEOUT; timeout++) 1418 ; 1419 1420 *data = (u16)(mvreg_read(pp, MVNETA_SMI) & MVNETA_SMI_DATA_MASK); 1421 1422 return 0; 1423 } 1424 1425 /* 1426 * smi_reg_write - imiiphy_write callback function. 1427 * 1428 * Returns 0 if write succeed, -EINVAL on bad parameters 1429 * -ETIME on timeout 1430 */ 1431 static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) 1432 { 1433 struct eth_device *dev = eth_get_dev_by_name(devname); 1434 struct mvneta_port *pp = dev->priv; 1435 u32 smi_reg; 1436 1437 /* check parameters */ 1438 if (phy_adr > MVNETA_PHY_ADDR_MASK) { 1439 printf("Error: Invalid PHY address %d\n", phy_adr); 1440 return -EFAULT; 1441 } 1442 1443 if (reg_ofs > MVNETA_PHY_REG_MASK) { 1444 printf("Err: Invalid register offset %d\n", reg_ofs); 1445 return -EFAULT; 1446 } 1447 1448 /* wait till the SMI is not busy */ 1449 if (smi_wait_ready(pp) < 0) 1450 return -EFAULT; 1451 1452 /* fill the phy addr and reg offset and write opcode and data */ 1453 smi_reg = (data << MVNETA_SMI_DATA_OFFS); 1454 smi_reg |= (phy_adr << MVNETA_SMI_DEV_ADDR_OFFS) 1455 | (reg_ofs << MVNETA_SMI_REG_ADDR_OFFS); 1456 smi_reg &= ~MVNETA_SMI_OPCODE_READ; 1457 1458 /* write the smi register */ 1459 mvreg_write(pp, MVNETA_SMI, smi_reg); 1460 1461 return 0; 1462 } 1463 1464 static int mvneta_init_u_boot(struct eth_device *dev, bd_t *bis) 1465 { 1466 struct mvneta_port *pp = dev->priv; 1467 struct phy_device *phydev; 1468 1469 mvneta_port_power_up(pp, pp->phy_interface); 1470 1471 if (!pp->init || pp->link == 0) { 1472 /* Set phy address of the port */ 1473 mvreg_write(pp, MVNETA_PHY_ADDR, pp->phyaddr); 1474 phydev = phy_connect(pp->bus, pp->phyaddr, dev, 1475 pp->phy_interface); 1476 1477 pp->phydev = phydev; 1478 phy_config(phydev); 1479 phy_startup(phydev); 1480 if (!phydev->link) { 1481 printf("%s: No link.\n", phydev->dev->name); 1482 return -1; 1483 } 1484 1485 /* Full init on first call */ 1486 mvneta_probe(dev); 1487 pp->init = 1; 1488 } else { 1489 /* Upon all following calls, this is enough */ 1490 mvneta_port_up(pp); 1491 mvneta_port_enable(pp); 1492 } 1493 1494 return 0; 1495 } 1496 1497 static int mvneta_send(struct eth_device *dev, void *ptr, int len) 1498 { 1499 struct mvneta_port *pp = dev->priv; 1500 struct mvneta_tx_queue *txq = &pp->txqs[0]; 1501 struct mvneta_tx_desc *tx_desc; 1502 int sent_desc; 1503 u32 timeout = 0; 1504 1505 /* Get a descriptor for the first part of the packet */ 1506 tx_desc = mvneta_txq_next_desc_get(txq); 1507 1508 tx_desc->buf_phys_addr = (u32)ptr; 1509 tx_desc->data_size = len; 1510 flush_dcache_range((u32)ptr, (u32)ptr + len); 1511 1512 /* First and Last descriptor */ 1513 tx_desc->command = MVNETA_TX_L4_CSUM_NOT | MVNETA_TXD_FLZ_DESC; 1514 mvneta_txq_pend_desc_add(pp, txq, 1); 1515 1516 /* Wait for packet to be sent (queue might help with speed here) */ 1517 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1518 while (!sent_desc) { 1519 if (timeout++ > 10000) { 1520 printf("timeout: packet not sent\n"); 1521 return -1; 1522 } 1523 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); 1524 } 1525 1526 /* txDone has increased - hw sent packet */ 1527 mvneta_txq_sent_desc_dec(pp, txq, sent_desc); 1528 return 0; 1529 1530 return 0; 1531 } 1532 1533 static int mvneta_recv(struct eth_device *dev) 1534 { 1535 struct mvneta_port *pp = dev->priv; 1536 int rx_done; 1537 int packets_done; 1538 struct mvneta_rx_queue *rxq; 1539 1540 /* get rx queue */ 1541 rxq = mvneta_rxq_handle_get(pp, rxq_def); 1542 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); 1543 packets_done = rx_done; 1544 1545 while (packets_done--) { 1546 struct mvneta_rx_desc *rx_desc; 1547 unsigned char *data; 1548 u32 rx_status; 1549 int rx_bytes; 1550 1551 /* 1552 * No cache invalidation needed here, since the desc's are 1553 * located in a uncached memory region 1554 */ 1555 rx_desc = mvneta_rxq_next_desc_get(rxq); 1556 1557 rx_status = rx_desc->status; 1558 if (!mvneta_rxq_desc_is_first_last(rx_status) || 1559 (rx_status & MVNETA_RXD_ERR_SUMMARY)) { 1560 mvneta_rx_error(pp, rx_desc); 1561 /* leave the descriptor untouched */ 1562 continue; 1563 } 1564 1565 /* 2 bytes for marvell header. 4 bytes for crc */ 1566 rx_bytes = rx_desc->data_size - 6; 1567 1568 /* give packet to stack - skip on first 2 bytes */ 1569 data = (u8 *)rx_desc->buf_cookie + 2; 1570 /* 1571 * No cache invalidation needed here, since the rx_buffer's are 1572 * located in a uncached memory region 1573 */ 1574 net_process_received_packet(data, rx_bytes); 1575 } 1576 1577 /* Update rxq management counters */ 1578 if (rx_done) 1579 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); 1580 1581 return 0; 1582 } 1583 1584 static void mvneta_halt(struct eth_device *dev) 1585 { 1586 struct mvneta_port *pp = dev->priv; 1587 1588 mvneta_port_down(pp); 1589 mvneta_port_disable(pp); 1590 } 1591 1592 int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr) 1593 { 1594 struct eth_device *dev; 1595 struct mvneta_port *pp; 1596 void *bd_space; 1597 1598 dev = calloc(1, sizeof(*dev)); 1599 if (dev == NULL) 1600 return -ENOMEM; 1601 1602 pp = calloc(1, sizeof(*pp)); 1603 if (pp == NULL) 1604 return -ENOMEM; 1605 1606 dev->priv = pp; 1607 1608 /* 1609 * Allocate buffer area for descs and rx_buffers. This is only 1610 * done once for all interfaces. As only one interface can 1611 * be active. Make this area DMA save by disabling the D-cache 1612 */ 1613 if (!buffer_loc.tx_descs) { 1614 /* Align buffer area for descs and rx_buffers to 1MiB */ 1615 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE); 1616 mmu_set_region_dcache_behaviour((u32)bd_space, BD_SPACE, 1617 DCACHE_OFF); 1618 buffer_loc.tx_descs = (struct mvneta_tx_desc *)bd_space; 1619 buffer_loc.rx_descs = (struct mvneta_rx_desc *) 1620 ((u32)bd_space + 1621 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc)); 1622 buffer_loc.rx_buffers = (u32) 1623 (bd_space + 1624 MVNETA_MAX_TXD * sizeof(struct mvneta_tx_desc) + 1625 MVNETA_MAX_RXD * sizeof(struct mvneta_rx_desc)); 1626 } 1627 1628 sprintf(dev->name, "neta%d", devnum); 1629 1630 pp->base = (void __iomem *)base_addr; 1631 dev->iobase = base_addr; 1632 dev->init = mvneta_init_u_boot; 1633 dev->halt = mvneta_halt; 1634 dev->send = mvneta_send; 1635 dev->recv = mvneta_recv; 1636 dev->write_hwaddr = NULL; 1637 1638 /* 1639 * The PHY interface type is configured via the 1640 * board specific CONFIG_SYS_NETA_INTERFACE_TYPE 1641 * define. 1642 */ 1643 pp->phy_interface = CONFIG_SYS_NETA_INTERFACE_TYPE; 1644 1645 eth_register(dev); 1646 1647 pp->phyaddr = phy_addr; 1648 miiphy_register(dev->name, smi_reg_read, smi_reg_write); 1649 pp->bus = miiphy_get_dev_by_name(dev->name); 1650 1651 return 1; 1652 } 1653