xref: /openbmc/u-boot/drivers/net/mvgbe.h (revision dcfe8638)
1  /*
2   * (C) Copyright 2009
3   * Marvell Semiconductor <www.marvell.com>
4   * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5   *
6   * based on - Driver for MV64360X ethernet ports
7   * Copyright (C) 2002 rabeeh@galileo.co.il
8   *
9   * See file CREDITS for list of people who contributed to this
10   * project.
11   *
12   * This program is free software; you can redistribute it and/or
13   * modify it under the terms of the GNU General Public License as
14   * published by the Free Software Foundation; either version 2 of
15   * the License, or (at your option) any later version.
16   *
17   * This program is distributed in the hope that it will be useful,
18   * but WITHOUT ANY WARRANTY; without even the implied warranty of
19   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20   * GNU General Public License for more details.
21   *
22   * You should have received a copy of the GNU General Public License
23   * along with this program; if not, write to the Free Software
24   * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
25   * MA 02110-1301 USA
26   */
27  
28  #ifndef __MVGBE_H__
29  #define __MVGBE_H__
30  
31  /* PHY_BASE_ADR is board specific and can be configured */
32  #if defined (CONFIG_PHY_BASE_ADR)
33  #define PHY_BASE_ADR		CONFIG_PHY_BASE_ADR
34  #else
35  #define PHY_BASE_ADR		0x08	/* default phy base addr */
36  #endif
37  
38  /* Constants */
39  #define INT_CAUSE_UNMASK_ALL		0x0007ffff
40  #define INT_CAUSE_UNMASK_ALL_EXT	0x0011ffff
41  #define MRU_MASK			0xfff1ffff
42  #define PHYADR_MASK			0x0000001f
43  #define PHYREG_MASK			0x0000001f
44  #define QTKNBKT_DEF_VAL			0x3fffffff
45  #define QMTBS_DEF_VAL			0x000003ff
46  #define QTKNRT_DEF_VAL			0x0000fcff
47  #define RXUQ	0 /* Used Rx queue */
48  #define TXUQ	0 /* Used Rx queue */
49  
50  #define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
51  #define MVGBE_REG_WR(adr, val)		writel(val, &adr)
52  #define MVGBE_REG_RD(adr)		readl(&adr)
53  #define MVGBE_REG_BITS_RESET(adr, val)	writel(readl(&adr) & ~(val), &adr)
54  #define MVGBE_REG_BITS_SET(adr, val)	writel(readl(&adr) | val, &adr)
55  
56  /* Default port configuration value */
57  #define PRT_CFG_VAL			( \
58  	MVGBE_UCAST_MOD_NRML		| \
59  	MVGBE_DFLT_RXQ(RXUQ)		| \
60  	MVGBE_DFLT_RX_ARPQ(RXUQ)	| \
61  	MVGBE_RX_BC_IF_NOT_IP_OR_ARP	| \
62  	MVGBE_RX_BC_IF_IP		| \
63  	MVGBE_RX_BC_IF_ARP		| \
64  	MVGBE_CPTR_TCP_FRMS_DIS		| \
65  	MVGBE_CPTR_UDP_FRMS_DIS		| \
66  	MVGBE_DFLT_RX_TCPQ(RXUQ)	| \
67  	MVGBE_DFLT_RX_UDPQ(RXUQ)	| \
68  	MVGBE_DFLT_RX_BPDUQ(RXUQ))
69  
70  /* Default port extend configuration value */
71  #define PORT_CFG_EXTEND_VALUE		\
72  	MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL	| \
73  	MVGBE_PARTITION_DIS		| \
74  	MVGBE_TX_CRC_GENERATION_EN
75  
76  #define GT_MVGBE_IPG_INT_RX(value)	((value & 0x3fff) << 8)
77  
78  /* Default sdma control value */
79  #define PORT_SDMA_CFG_VALUE		( \
80  	MVGBE_RX_BURST_SIZE_16_64BIT	| \
81  	MVGBE_BLM_RX_NO_SWAP		| \
82  	MVGBE_BLM_TX_NO_SWAP		| \
83  	GT_MVGBE_IPG_INT_RX(RXUQ)	| \
84  	MVGBE_TX_BURST_SIZE_16_64BIT)
85  
86  /* Default port serial control value */
87  #ifndef PORT_SERIAL_CONTROL_VALUE
88  #define PORT_SERIAL_CONTROL_VALUE		( \
89  	MVGBE_FORCE_LINK_PASS			| \
90  	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
91  	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
92  	MVGBE_ADV_NO_FLOW_CTRL			| \
93  	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
94  	MVGBE_FORCE_BP_MODE_NO_JAM		| \
95  	(1 << 9) /* Reserved bit has to be 1 */	| \
96  	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
97  	MVGBE_EN_AUTO_NEG_SPEED_GMII		| \
98  	MVGBE_DTE_ADV_0				| \
99  	MVGBE_MIIPHY_MAC_MODE			| \
100  	MVGBE_AUTO_NEG_NO_CHANGE		| \
101  	MVGBE_MAX_RX_PACKET_1552BYTE		| \
102  	MVGBE_CLR_EXT_LOOPBACK			| \
103  	MVGBE_SET_FULL_DUPLEX_MODE		| \
104  	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
105  #endif
106  
107  /* Tx WRR confoguration macros */
108  #define PORT_MAX_TRAN_UNIT	0x24	/* MTU register (default) 9KByte */
109  #define PORT_MAX_TOKEN_BUCKET_SIZE	0x_FFFF	/* PMTBS reg (default) */
110  #define PORT_TOKEN_RATE		1023	/* PTTBRC reg (default) */
111  /* MAC accepet/reject macros */
112  #define ACCEPT_MAC_ADDR		0
113  #define REJECT_MAC_ADDR		1
114  /* Size of a Tx/Rx descriptor used in chain list data structure */
115  #define MV_RXQ_DESC_ALIGNED_SIZE	\
116  	(((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
117  /* Buffer offset from buffer pointer */
118  #define RX_BUF_OFFSET		0x2
119  
120  /* Port serial status reg (PSR) */
121  #define MVGBE_INTERFACE_GMII_MII	0
122  #define MVGBE_INTERFACE_PCM		1
123  #define MVGBE_LINK_IS_DOWN		0
124  #define MVGBE_LINK_IS_UP		(1 << 1)
125  #define MVGBE_PORT_AT_HALF_DUPLEX	0
126  #define MVGBE_PORT_AT_FULL_DUPLEX	(1 << 2)
127  #define MVGBE_RX_FLOW_CTRL_DISD		0
128  #define MVGBE_RX_FLOW_CTRL_ENBALED	(1 << 3)
129  #define MVGBE_GMII_SPEED_100_10		0
130  #define MVGBE_GMII_SPEED_1000		(1 << 4)
131  #define MVGBE_MII_SPEED_10		0
132  #define MVGBE_MII_SPEED_100		(1 << 5)
133  #define MVGBE_NO_TX			0
134  #define MVGBE_TX_IN_PROGRESS		(1 << 7)
135  #define MVGBE_BYPASS_NO_ACTIVE		0
136  #define MVGBE_BYPASS_ACTIVE		(1 << 8)
137  #define MVGBE_PORT_NOT_AT_PARTN_STT	0
138  #define MVGBE_PORT_AT_PARTN_STT		(1 << 9)
139  #define MVGBE_PORT_TX_FIFO_NOT_EMPTY	0
140  #define MVGBE_PORT_TX_FIFO_EMPTY	(1 << 10)
141  
142  /* These macros describes the Port configuration reg (Px_cR) bits */
143  #define MVGBE_UCAST_MOD_NRML		0
144  #define MVGBE_UNICAST_PROMISCUOUS_MODE	1
145  #define MVGBE_DFLT_RXQ(_x)		(_x << 1)
146  #define MVGBE_DFLT_RX_ARPQ(_x)		(_x << 4)
147  #define MVGBE_RX_BC_IF_NOT_IP_OR_ARP	0
148  #define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
149  #define MVGBE_RX_BC_IF_IP		0
150  #define MVGBE_REJECT_BC_IF_IP		(1 << 8)
151  #define MVGBE_RX_BC_IF_ARP		0
152  #define MVGBE_REJECT_BC_IF_ARP		(1 << 9)
153  #define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY	(1 << 12)
154  #define MVGBE_CPTR_TCP_FRMS_DIS		0
155  #define MVGBE_CPTR_TCP_FRMS_EN		(1 << 14)
156  #define MVGBE_CPTR_UDP_FRMS_DIS		0
157  #define MVGBE_CPTR_UDP_FRMS_EN		(1 << 15)
158  #define MVGBE_DFLT_RX_TCPQ(_x)		(_x << 16)
159  #define MVGBE_DFLT_RX_UDPQ(_x)		(_x << 19)
160  #define MVGBE_DFLT_RX_BPDUQ(_x)		(_x << 22)
161  #define MVGBE_DFLT_RX_TCP_CHKSUM_MODE	(1 << 25)
162  
163  /* These macros describes the Port configuration extend reg (Px_cXR) bits*/
164  #define MVGBE_CLASSIFY_EN			1
165  #define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL	0
166  #define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7	(1 << 1)
167  #define MVGBE_PARTITION_DIS			0
168  #define MVGBE_PARTITION_EN			(1 << 2)
169  #define MVGBE_TX_CRC_GENERATION_EN		0
170  #define MVGBE_TX_CRC_GENERATION_DIS		(1 << 3)
171  
172  /* These macros describes the Port Sdma configuration reg (SDCR) bits */
173  #define MVGBE_RIFB				1
174  #define MVGBE_RX_BURST_SIZE_1_64BIT		0
175  #define MVGBE_RX_BURST_SIZE_2_64BIT		(1 << 1)
176  #define MVGBE_RX_BURST_SIZE_4_64BIT		(1 << 2)
177  #define MVGBE_RX_BURST_SIZE_8_64BIT		((1 << 2) | (1 << 1))
178  #define MVGBE_RX_BURST_SIZE_16_64BIT		(1 << 3)
179  #define MVGBE_BLM_RX_NO_SWAP			(1 << 4)
180  #define MVGBE_BLM_RX_BYTE_SWAP			0
181  #define MVGBE_BLM_TX_NO_SWAP			(1 << 5)
182  #define MVGBE_BLM_TX_BYTE_SWAP			0
183  #define MVGBE_DESCRIPTORS_BYTE_SWAP		(1 << 6)
184  #define MVGBE_DESCRIPTORS_NO_SWAP		0
185  #define MVGBE_TX_BURST_SIZE_1_64BIT		0
186  #define MVGBE_TX_BURST_SIZE_2_64BIT		(1 << 22)
187  #define MVGBE_TX_BURST_SIZE_4_64BIT		(1 << 23)
188  #define MVGBE_TX_BURST_SIZE_8_64BIT		((1 << 23) | (1 << 22))
189  #define MVGBE_TX_BURST_SIZE_16_64BIT		(1 << 24)
190  
191  /* These macros describes the Port serial control reg (PSCR) bits */
192  #define MVGBE_SERIAL_PORT_DIS			0
193  #define MVGBE_SERIAL_PORT_EN			1
194  #define MVGBE_FORCE_LINK_PASS			(1 << 1)
195  #define MVGBE_DO_NOT_FORCE_LINK_PASS		0
196  #define MVGBE_EN_AUTO_NEG_FOR_DUPLX		0
197  #define MVGBE_DIS_AUTO_NEG_FOR_DUPLX		(1 << 2)
198  #define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL		0
199  #define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	(1 << 3)
200  #define MVGBE_ADV_NO_FLOW_CTRL			0
201  #define MVGBE_ADV_SYMMETRIC_FLOW_CTRL		(1 << 4)
202  #define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	0
203  #define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS	(1 << 5)
204  #define MVGBE_FORCE_BP_MODE_NO_JAM		0
205  #define MVGBE_FORCE_BP_MODE_JAM_TX		(1 << 7)
206  #define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR	(1 << 8)
207  #define MVGBE_FORCE_LINK_FAIL			0
208  #define MVGBE_DO_NOT_FORCE_LINK_FAIL		(1 << 10)
209  #define MVGBE_DIS_AUTO_NEG_SPEED_GMII		(1 << 13)
210  #define MVGBE_EN_AUTO_NEG_SPEED_GMII		0
211  #define MVGBE_DTE_ADV_0				0
212  #define MVGBE_DTE_ADV_1				(1 << 14)
213  #define MVGBE_MIIPHY_MAC_MODE			0
214  #define MVGBE_MIIPHY_PHY_MODE			(1 << 15)
215  #define MVGBE_AUTO_NEG_NO_CHANGE		0
216  #define MVGBE_RESTART_AUTO_NEG			(1 << 16)
217  #define MVGBE_MAX_RX_PACKET_1518BYTE		0
218  #define MVGBE_MAX_RX_PACKET_1522BYTE		(1 << 17)
219  #define MVGBE_MAX_RX_PACKET_1552BYTE		(1 << 18)
220  #define MVGBE_MAX_RX_PACKET_9022BYTE		((1 << 18) | (1 << 17))
221  #define MVGBE_MAX_RX_PACKET_9192BYTE		(1 << 19)
222  #define MVGBE_MAX_RX_PACKET_9700BYTE		((1 << 19) | (1 << 17))
223  #define MVGBE_SET_EXT_LOOPBACK			(1 << 20)
224  #define MVGBE_CLR_EXT_LOOPBACK			0
225  #define MVGBE_SET_FULL_DUPLEX_MODE		(1 << 21)
226  #define MVGBE_SET_HALF_DUPLEX_MODE		0
227  #define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	(1 << 22)
228  #define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
229  #define MVGBE_SET_GMII_SPEED_TO_10_100		0
230  #define MVGBE_SET_GMII_SPEED_TO_1000		(1 << 23)
231  #define MVGBE_SET_MII_SPEED_TO_10		0
232  #define MVGBE_SET_MII_SPEED_TO_100		(1 << 24)
233  
234  /* SMI register fields */
235  #define MVGBE_PHY_SMI_TIMEOUT		10000
236  #define MVGBE_PHY_SMI_DATA_OFFS		0	/* Data */
237  #define MVGBE_PHY_SMI_DATA_MASK		(0xffff << MVGBE_PHY_SMI_DATA_OFFS)
238  #define MVGBE_PHY_SMI_DEV_ADDR_OFFS	16	/* PHY device address */
239  #define MVGBE_PHY_SMI_DEV_ADDR_MASK \
240  	(PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
241  #define MVGBE_SMI_REG_ADDR_OFFS		21	/* PHY device reg addr */
242  #define MVGBE_SMI_REG_ADDR_MASK \
243  	(PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS)
244  #define MVGBE_PHY_SMI_OPCODE_OFFS	26	/* Write/Read opcode */
245  #define MVGBE_PHY_SMI_OPCODE_MASK	(3 << MVGBE_PHY_SMI_OPCODE_OFFS)
246  #define MVGBE_PHY_SMI_OPCODE_WRITE	(0 << MVGBE_PHY_SMI_OPCODE_OFFS)
247  #define MVGBE_PHY_SMI_OPCODE_READ	(1 << MVGBE_PHY_SMI_OPCODE_OFFS)
248  #define MVGBE_PHY_SMI_READ_VALID_MASK	(1 << 27)	/* Read Valid */
249  #define MVGBE_PHY_SMI_BUSY_MASK		(1 << 28)	/* Busy */
250  
251  /* SDMA command status fields macros */
252  /* Tx & Rx descriptors status */
253  #define MVGBE_ERROR_SUMMARY		1
254  /* Tx & Rx descriptors command */
255  #define MVGBE_BUFFER_OWNED_BY_DMA	(1 << 31)
256  /* Tx descriptors status */
257  #define MVGBE_LC_ERROR			0
258  #define MVGBE_UR_ERROR			(1 << 1)
259  #define MVGBE_RL_ERROR			(1 << 2)
260  #define MVGBE_LLC_SNAP_FORMAT		(1 << 9)
261  #define MVGBE_TX_LAST_FRAME		(1 << 20)
262  
263  /* Rx descriptors status */
264  #define MVGBE_CRC_ERROR			0
265  #define MVGBE_OVERRUN_ERROR		(1 << 1)
266  #define MVGBE_MAX_FRAME_LENGTH_ERROR	(1 << 2)
267  #define MVGBE_RESOURCE_ERROR		((1 << 2) | (1 << 1))
268  #define MVGBE_VLAN_TAGGED		(1 << 19)
269  #define MVGBE_BPDU_FRAME		(1 << 20)
270  #define MVGBE_TCP_FRAME_OVER_IP_V_4	0
271  #define MVGBE_UDP_FRAME_OVER_IP_V_4	(1 << 21)
272  #define MVGBE_OTHER_FRAME_TYPE		(1 << 22)
273  #define MVGBE_LAYER_2_IS_MVGBE_V_2	(1 << 23)
274  #define MVGBE_FRAME_TYPE_IP_V_4		(1 << 24)
275  #define MVGBE_FRAME_HEADER_OK		(1 << 25)
276  #define MVGBE_RX_LAST_DESC		(1 << 26)
277  #define MVGBE_RX_FIRST_DESC		(1 << 27)
278  #define MVGBE_UNKNOWN_DESTINATION_ADDR	(1 << 28)
279  #define MVGBE_RX_EN_INTERRUPT		(1 << 29)
280  #define MVGBE_LAYER_4_CHECKSUM_OK	(1 << 30)
281  
282  /* Rx descriptors byte count */
283  #define MVGBE_FRAME_FRAGMENTED		(1 << 2)
284  
285  /* Tx descriptors command */
286  #define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC	(1 << 10)
287  #define MVGBE_FRAME_SET_TO_VLAN			(1 << 15)
288  #define MVGBE_TCP_FRAME				0
289  #define MVGBE_UDP_FRAME				(1 << 16)
290  #define MVGBE_GEN_TCP_UDP_CHECKSUM		(1 << 17)
291  #define MVGBE_GEN_IP_V_4_CHECKSUM		(1 << 18)
292  #define MVGBE_ZERO_PADDING			(1 << 19)
293  #define MVGBE_TX_LAST_DESC			(1 << 20)
294  #define MVGBE_TX_FIRST_DESC			(1 << 21)
295  #define MVGBE_GEN_CRC				(1 << 22)
296  #define MVGBE_TX_EN_INTERRUPT			(1 << 23)
297  #define MVGBE_AUTO_MODE				(1 << 30)
298  
299  /* Address decode parameters */
300  /* Ethernet Base Address Register bits */
301  #define EBAR_TARGET_DRAM			0x00000000
302  #define EBAR_TARGET_DEVICE			0x00000001
303  #define EBAR_TARGET_CBS				0x00000002
304  #define EBAR_TARGET_PCI0			0x00000003
305  #define EBAR_TARGET_PCI1			0x00000004
306  #define EBAR_TARGET_CUNIT			0x00000005
307  #define EBAR_TARGET_AUNIT			0x00000006
308  #define EBAR_TARGET_GUNIT			0x00000007
309  
310  /* Window attrib */
311  #define EBAR_DRAM_CS0				0x00000E00
312  #define EBAR_DRAM_CS1				0x00000D00
313  #define EBAR_DRAM_CS2				0x00000B00
314  #define EBAR_DRAM_CS3				0x00000700
315  
316  /* DRAM Target interface */
317  #define EBAR_DRAM_NO_CACHE_COHERENCY		0x00000000
318  #define EBAR_DRAM_CACHE_COHERENCY_WT		0x00001000
319  #define EBAR_DRAM_CACHE_COHERENCY_WB		0x00002000
320  
321  /* Device Bus Target interface */
322  #define EBAR_DEVICE_DEVCS0			0x00001E00
323  #define EBAR_DEVICE_DEVCS1			0x00001D00
324  #define EBAR_DEVICE_DEVCS2			0x00001B00
325  #define EBAR_DEVICE_DEVCS3			0x00001700
326  #define EBAR_DEVICE_BOOTCS3			0x00000F00
327  
328  /* PCI Target interface */
329  #define EBAR_PCI_BYTE_SWAP			0x00000000
330  #define EBAR_PCI_NO_SWAP			0x00000100
331  #define EBAR_PCI_BYTE_WORD_SWAP			0x00000200
332  #define EBAR_PCI_WORD_SWAP			0x00000300
333  #define EBAR_PCI_NO_SNOOP_NOT_ASSERT		0x00000000
334  #define EBAR_PCI_NO_SNOOP_ASSERT		0x00000400
335  #define EBAR_PCI_IO_SPACE			0x00000000
336  #define EBAR_PCI_MEMORY_SPACE			0x00000800
337  #define EBAR_PCI_REQ64_FORCE			0x00000000
338  #define EBAR_PCI_REQ64_SIZE			0x00001000
339  
340  /* Window access control */
341  #define EWIN_ACCESS_NOT_ALLOWED 0
342  #define EWIN_ACCESS_READ_ONLY	1
343  #define EWIN_ACCESS_FULL	((1 << 1) | 1)
344  
345  /* structures represents Controller registers */
346  struct mvgbe_barsz {
347  	u32 bar;
348  	u32 size;
349  };
350  
351  struct mvgbe_rxcdp {
352  	struct mvgbe_rxdesc *rxcdp;
353  	u32 rxcdp_pad[3];
354  };
355  
356  struct mvgbe_tqx {
357  	u32 qxttbc;
358  	u32 tqxtbc;
359  	u32 tqxac;
360  	u32 tqxpad;
361  };
362  
363  struct mvgbe_registers {
364  	u32 phyadr;
365  	u32 smi;
366  	u32 euda;
367  	u32 eudid;
368  	u8 pad1[0x080 - 0x00c - 4];
369  	u32 euic;
370  	u32 euim;
371  	u8 pad2[0x094 - 0x084 - 4];
372  	u32 euea;
373  	u32 euiae;
374  	u8 pad3[0x0b0 - 0x098 - 4];
375  	u32 euc;
376  	u8 pad3a[0x200 - 0x0b0 - 4];
377  	struct mvgbe_barsz barsz[6];
378  	u8 pad4[0x280 - 0x22c - 4];
379  	u32 ha_remap[4];
380  	u32 bare;
381  	u32 epap;
382  	u8 pad5[0x400 - 0x294 - 4];
383  	u32 pxc;
384  	u32 pxcx;
385  	u32 mii_ser_params;
386  	u8 pad6[0x410 - 0x408 - 4];
387  	u32 evlane;
388  	u32 macal;
389  	u32 macah;
390  	u32 sdc;
391  	u32 dscp[7];
392  	u32 psc0;
393  	u32 vpt2p;
394  	u32 ps0;
395  	u32 tqc;
396  	u32 psc1;
397  	u32 ps1;
398  	u32 mrvl_header;
399  	u8 pad7[0x460 - 0x454 - 4];
400  	u32 ic;
401  	u32 ice;
402  	u32 pim;
403  	u32 peim;
404  	u8 pad8[0x474 - 0x46c - 4];
405  	u32 pxtfut;
406  	u32 pad9;
407  	u32 pxmfs;
408  	u32 pad10;
409  	u32 pxdfc;
410  	u32 pxofc;
411  	u8 pad11[0x494 - 0x488 - 4];
412  	u32 peuiae;
413  	u8 pad12[0x4bc - 0x494 - 4];
414  	u32 eth_type_prio;
415  	u8 pad13[0x4dc - 0x4bc - 4];
416  	u32 tqfpc;
417  	u32 pttbrc;
418  	u32 tqc1;
419  	u32 pmtu;
420  	u32 pmtbs;
421  	u8 pad14[0x60c - 0x4ec - 4];
422  	struct mvgbe_rxcdp rxcdp[7];
423  	struct mvgbe_rxdesc *rxcdp7;
424  	u32 rqc;
425  	struct mvgbe_txdesc *tcsdp;
426  	u8 pad15[0x6c0 - 0x684 - 4];
427  	struct mvgbe_txdesc *tcqdp[8];
428  	u8 pad16[0x700 - 0x6dc - 4];
429  	struct mvgbe_tqx tqx[8];
430  	u32 pttbc;
431  	u8 pad17[0x7a8 - 0x780 - 4];
432  	u32 tqxipg0;
433  	u32 pad18[3];
434  	u32 tqxipg1;
435  	u8 pad19[0x7c0 - 0x7b8 - 4];
436  	u32 hitkninlopkt;
437  	u32 hitkninasyncpkt;
438  	u32 lotkninasyncpkt;
439  	u32 pad20;
440  	u32 ts;
441  	u8 pad21[0x3000 - 0x27d0 - 4];
442  	u32 pad20_1[32];	/* mib counter registes */
443  	u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
444  	u32 dfsmt[64];
445  	u32 dfomt[64];
446  	u32 dfut[4];
447  	u8 pad23[0xe20c0 - 0x7360c - 4];
448  	u32 pmbus_top_arbiter;
449  };
450  
451  /* structures/enums needed by driver */
452  enum mvgbe_adrwin {
453  	MVGBE_WIN0,
454  	MVGBE_WIN1,
455  	MVGBE_WIN2,
456  	MVGBE_WIN3,
457  	MVGBE_WIN4,
458  	MVGBE_WIN5
459  };
460  
461  enum mvgbe_target {
462  	MVGBE_TARGET_DRAM,
463  	MVGBE_TARGET_DEV,
464  	MVGBE_TARGET_CBS,
465  	MVGBE_TARGET_PCI0,
466  	MVGBE_TARGET_PCI1
467  };
468  
469  struct mvgbe_winparam {
470  	enum mvgbe_adrwin win;	/* Window number */
471  	enum mvgbe_target target;	/* System targets */
472  	u16 attrib;		/* BAR attrib. See above macros */
473  	u32 base_addr;		/* Window base address in u32 form */
474  	u32 high_addr;		/* Window high address in u32 form */
475  	u32 size;		/* Size in MBytes. Must be % 64Kbyte. */
476  	int enable;		/* Enable/disable access to the window. */
477  	u16 access_ctrl;	/*Access ctrl register. see above macros */
478  };
479  
480  struct mvgbe_rxdesc {
481  	u32 cmd_sts;		/* Descriptor command status */
482  	u16 buf_size;		/* Buffer size */
483  	u16 byte_cnt;		/* Descriptor buffer byte count */
484  	u8 *buf_ptr;		/* Descriptor buffer pointer */
485  	struct mvgbe_rxdesc *nxtdesc_p;	/* Next descriptor pointer */
486  };
487  
488  struct mvgbe_txdesc {
489  	u32 cmd_sts;		/* Descriptor command status */
490  	u16 l4i_chk;		/* CPU provided TCP Checksum */
491  	u16 byte_cnt;		/* Descriptor buffer byte count */
492  	u8 *buf_ptr;		/* Descriptor buffer ptr */
493  	struct mvgbe_txdesc *nxtdesc_p;	/* Next descriptor ptr */
494  };
495  
496  /* port device data struct */
497  struct mvgbe_device {
498  	struct eth_device dev;
499  	struct mvgbe_registers *regs;
500  	struct mvgbe_txdesc *p_txdesc;
501  	struct mvgbe_rxdesc *p_rxdesc;
502  	struct mvgbe_rxdesc *p_rxdesc_curr;
503  	u8 *p_rxbuf;
504  	u8 *p_aligned_txbuf;
505  };
506  
507  #endif /* __MVGBE_H__ */
508