1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 * 7 * based on - Driver for MV64360X ethernet ports 8 * Copyright (C) 2002 rabeeh@galileo.co.il 9 */ 10 11 #ifndef __MVGBE_H__ 12 #define __MVGBE_H__ 13 14 /* PHY_BASE_ADR is board specific and can be configured */ 15 #if defined (CONFIG_PHY_BASE_ADR) 16 #define PHY_BASE_ADR CONFIG_PHY_BASE_ADR 17 #else 18 #define PHY_BASE_ADR 0x08 /* default phy base addr */ 19 #endif 20 21 /* Constants */ 22 #define INT_CAUSE_UNMASK_ALL 0x0007ffff 23 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff 24 #define MRU_MASK 0xfff1ffff 25 #define PHYADR_MASK 0x0000001f 26 #define PHYREG_MASK 0x0000001f 27 #define QTKNBKT_DEF_VAL 0x3fffffff 28 #define QMTBS_DEF_VAL 0x000003ff 29 #define QTKNRT_DEF_VAL 0x0000fcff 30 #define RXUQ 0 /* Used Rx queue */ 31 #define TXUQ 0 /* Used Rx queue */ 32 33 #ifndef CONFIG_DM_ETH 34 #define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev) 35 #endif 36 #define MVGBE_REG_WR(adr, val) writel(val, &adr) 37 #define MVGBE_REG_RD(adr) readl(&adr) 38 #define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr) 39 #define MVGBE_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr) 40 41 /* Default port configuration value */ 42 #define PRT_CFG_VAL ( \ 43 MVGBE_UCAST_MOD_NRML | \ 44 MVGBE_DFLT_RXQ(RXUQ) | \ 45 MVGBE_DFLT_RX_ARPQ(RXUQ) | \ 46 MVGBE_RX_BC_IF_NOT_IP_OR_ARP | \ 47 MVGBE_RX_BC_IF_IP | \ 48 MVGBE_RX_BC_IF_ARP | \ 49 MVGBE_CPTR_TCP_FRMS_DIS | \ 50 MVGBE_CPTR_UDP_FRMS_DIS | \ 51 MVGBE_DFLT_RX_TCPQ(RXUQ) | \ 52 MVGBE_DFLT_RX_UDPQ(RXUQ) | \ 53 MVGBE_DFLT_RX_BPDUQ(RXUQ)) 54 55 /* Default port extend configuration value */ 56 #define PORT_CFG_EXTEND_VALUE \ 57 MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \ 58 MVGBE_PARTITION_DIS | \ 59 MVGBE_TX_CRC_GENERATION_EN 60 61 #define GT_MVGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8) 62 63 /* Default sdma control value */ 64 #define PORT_SDMA_CFG_VALUE ( \ 65 MVGBE_RX_BURST_SIZE_16_64BIT | \ 66 MVGBE_BLM_RX_NO_SWAP | \ 67 MVGBE_BLM_TX_NO_SWAP | \ 68 GT_MVGBE_IPG_INT_RX(RXUQ) | \ 69 MVGBE_TX_BURST_SIZE_16_64BIT) 70 71 /* Default port serial control value */ 72 #ifndef PORT_SERIAL_CONTROL_VALUE 73 #define PORT_SERIAL_CONTROL_VALUE ( \ 74 MVGBE_FORCE_LINK_PASS | \ 75 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ 76 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ 77 MVGBE_ADV_NO_FLOW_CTRL | \ 78 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 79 MVGBE_FORCE_BP_MODE_NO_JAM | \ 80 (1 << 9) /* Reserved bit has to be 1 */ | \ 81 MVGBE_DO_NOT_FORCE_LINK_FAIL | \ 82 MVGBE_EN_AUTO_NEG_SPEED_GMII | \ 83 MVGBE_DTE_ADV_0 | \ 84 MVGBE_MIIPHY_MAC_MODE | \ 85 MVGBE_AUTO_NEG_NO_CHANGE | \ 86 MVGBE_MAX_RX_PACKET_1552BYTE | \ 87 MVGBE_CLR_EXT_LOOPBACK | \ 88 MVGBE_SET_FULL_DUPLEX_MODE | \ 89 MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX) 90 #endif 91 92 /* Tx WRR confoguration macros */ 93 #define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ 94 #define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */ 95 #define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */ 96 /* MAC accepet/reject macros */ 97 #define ACCEPT_MAC_ADDR 0 98 #define REJECT_MAC_ADDR 1 99 /* Size of a Tx/Rx descriptor used in chain list data structure */ 100 #define MV_RXQ_DESC_ALIGNED_SIZE \ 101 (((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN) 102 /* Buffer offset from buffer pointer */ 103 #define RX_BUF_OFFSET 0x2 104 105 /* Port serial status reg (PSR) */ 106 #define MVGBE_INTERFACE_GMII_MII 0 107 #define MVGBE_INTERFACE_PCM 1 108 #define MVGBE_LINK_IS_DOWN 0 109 #define MVGBE_LINK_IS_UP (1 << 1) 110 #define MVGBE_PORT_AT_HALF_DUPLEX 0 111 #define MVGBE_PORT_AT_FULL_DUPLEX (1 << 2) 112 #define MVGBE_RX_FLOW_CTRL_DISD 0 113 #define MVGBE_RX_FLOW_CTRL_ENBALED (1 << 3) 114 #define MVGBE_GMII_SPEED_100_10 0 115 #define MVGBE_GMII_SPEED_1000 (1 << 4) 116 #define MVGBE_MII_SPEED_10 0 117 #define MVGBE_MII_SPEED_100 (1 << 5) 118 #define MVGBE_NO_TX 0 119 #define MVGBE_TX_IN_PROGRESS (1 << 7) 120 #define MVGBE_BYPASS_NO_ACTIVE 0 121 #define MVGBE_BYPASS_ACTIVE (1 << 8) 122 #define MVGBE_PORT_NOT_AT_PARTN_STT 0 123 #define MVGBE_PORT_AT_PARTN_STT (1 << 9) 124 #define MVGBE_PORT_TX_FIFO_NOT_EMPTY 0 125 #define MVGBE_PORT_TX_FIFO_EMPTY (1 << 10) 126 127 /* These macros describes the Port configuration reg (Px_cR) bits */ 128 #define MVGBE_UCAST_MOD_NRML 0 129 #define MVGBE_UNICAST_PROMISCUOUS_MODE 1 130 #define MVGBE_DFLT_RXQ(_x) (_x << 1) 131 #define MVGBE_DFLT_RX_ARPQ(_x) (_x << 4) 132 #define MVGBE_RX_BC_IF_NOT_IP_OR_ARP 0 133 #define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) 134 #define MVGBE_RX_BC_IF_IP 0 135 #define MVGBE_REJECT_BC_IF_IP (1 << 8) 136 #define MVGBE_RX_BC_IF_ARP 0 137 #define MVGBE_REJECT_BC_IF_ARP (1 << 9) 138 #define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12) 139 #define MVGBE_CPTR_TCP_FRMS_DIS 0 140 #define MVGBE_CPTR_TCP_FRMS_EN (1 << 14) 141 #define MVGBE_CPTR_UDP_FRMS_DIS 0 142 #define MVGBE_CPTR_UDP_FRMS_EN (1 << 15) 143 #define MVGBE_DFLT_RX_TCPQ(_x) (_x << 16) 144 #define MVGBE_DFLT_RX_UDPQ(_x) (_x << 19) 145 #define MVGBE_DFLT_RX_BPDUQ(_x) (_x << 22) 146 #define MVGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25) 147 148 /* These macros describes the Port configuration extend reg (Px_cXR) bits*/ 149 #define MVGBE_CLASSIFY_EN 1 150 #define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0 151 #define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1) 152 #define MVGBE_PARTITION_DIS 0 153 #define MVGBE_PARTITION_EN (1 << 2) 154 #define MVGBE_TX_CRC_GENERATION_EN 0 155 #define MVGBE_TX_CRC_GENERATION_DIS (1 << 3) 156 157 /* These macros describes the Port Sdma configuration reg (SDCR) bits */ 158 #define MVGBE_RIFB 1 159 #define MVGBE_RX_BURST_SIZE_1_64BIT 0 160 #define MVGBE_RX_BURST_SIZE_2_64BIT (1 << 1) 161 #define MVGBE_RX_BURST_SIZE_4_64BIT (1 << 2) 162 #define MVGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1)) 163 #define MVGBE_RX_BURST_SIZE_16_64BIT (1 << 3) 164 #define MVGBE_BLM_RX_NO_SWAP (1 << 4) 165 #define MVGBE_BLM_RX_BYTE_SWAP 0 166 #define MVGBE_BLM_TX_NO_SWAP (1 << 5) 167 #define MVGBE_BLM_TX_BYTE_SWAP 0 168 #define MVGBE_DESCRIPTORS_BYTE_SWAP (1 << 6) 169 #define MVGBE_DESCRIPTORS_NO_SWAP 0 170 #define MVGBE_TX_BURST_SIZE_1_64BIT 0 171 #define MVGBE_TX_BURST_SIZE_2_64BIT (1 << 22) 172 #define MVGBE_TX_BURST_SIZE_4_64BIT (1 << 23) 173 #define MVGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22)) 174 #define MVGBE_TX_BURST_SIZE_16_64BIT (1 << 24) 175 176 /* These macros describes the Port serial control reg (PSCR) bits */ 177 #define MVGBE_SERIAL_PORT_DIS 0 178 #define MVGBE_SERIAL_PORT_EN 1 179 #define MVGBE_FORCE_LINK_PASS (1 << 1) 180 #define MVGBE_DO_NOT_FORCE_LINK_PASS 0 181 #define MVGBE_EN_AUTO_NEG_FOR_DUPLX 0 182 #define MVGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2) 183 #define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0 184 #define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) 185 #define MVGBE_ADV_NO_FLOW_CTRL 0 186 #define MVGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4) 187 #define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 188 #define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5) 189 #define MVGBE_FORCE_BP_MODE_NO_JAM 0 190 #define MVGBE_FORCE_BP_MODE_JAM_TX (1 << 7) 191 #define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8) 192 #define MVGBE_FORCE_LINK_FAIL 0 193 #define MVGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10) 194 #define MVGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13) 195 #define MVGBE_EN_AUTO_NEG_SPEED_GMII 0 196 #define MVGBE_DTE_ADV_0 0 197 #define MVGBE_DTE_ADV_1 (1 << 14) 198 #define MVGBE_MIIPHY_MAC_MODE 0 199 #define MVGBE_MIIPHY_PHY_MODE (1 << 15) 200 #define MVGBE_AUTO_NEG_NO_CHANGE 0 201 #define MVGBE_RESTART_AUTO_NEG (1 << 16) 202 #define MVGBE_MAX_RX_PACKET_1518BYTE 0 203 #define MVGBE_MAX_RX_PACKET_1522BYTE (1 << 17) 204 #define MVGBE_MAX_RX_PACKET_1552BYTE (1 << 18) 205 #define MVGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17)) 206 #define MVGBE_MAX_RX_PACKET_9192BYTE (1 << 19) 207 #define MVGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17)) 208 #define MVGBE_SET_EXT_LOOPBACK (1 << 20) 209 #define MVGBE_CLR_EXT_LOOPBACK 0 210 #define MVGBE_SET_FULL_DUPLEX_MODE (1 << 21) 211 #define MVGBE_SET_HALF_DUPLEX_MODE 0 212 #define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) 213 #define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 214 #define MVGBE_SET_GMII_SPEED_TO_10_100 0 215 #define MVGBE_SET_GMII_SPEED_TO_1000 (1 << 23) 216 #define MVGBE_SET_MII_SPEED_TO_10 0 217 #define MVGBE_SET_MII_SPEED_TO_100 (1 << 24) 218 219 /* SMI register fields */ 220 #define MVGBE_PHY_SMI_TIMEOUT 10000 221 #define MVGBE_PHY_SMI_TIMEOUT_MS 1000 222 #define MVGBE_PHY_SMI_DATA_OFFS 0 /* Data */ 223 #define MVGBE_PHY_SMI_DATA_MASK (0xffff << MVGBE_PHY_SMI_DATA_OFFS) 224 #define MVGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ 225 #define MVGBE_PHY_SMI_DEV_ADDR_MASK \ 226 (PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS) 227 #define MVGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */ 228 #define MVGBE_SMI_REG_ADDR_MASK \ 229 (PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS) 230 #define MVGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ 231 #define MVGBE_PHY_SMI_OPCODE_MASK (3 << MVGBE_PHY_SMI_OPCODE_OFFS) 232 #define MVGBE_PHY_SMI_OPCODE_WRITE (0 << MVGBE_PHY_SMI_OPCODE_OFFS) 233 #define MVGBE_PHY_SMI_OPCODE_READ (1 << MVGBE_PHY_SMI_OPCODE_OFFS) 234 #define MVGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */ 235 #define MVGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */ 236 237 /* SDMA command status fields macros */ 238 /* Tx & Rx descriptors status */ 239 #define MVGBE_ERROR_SUMMARY 1 240 /* Tx & Rx descriptors command */ 241 #define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31) 242 /* Tx descriptors status */ 243 #define MVGBE_LC_ERROR 0 244 #define MVGBE_UR_ERROR (1 << 1) 245 #define MVGBE_RL_ERROR (1 << 2) 246 #define MVGBE_LLC_SNAP_FORMAT (1 << 9) 247 #define MVGBE_TX_LAST_FRAME (1 << 20) 248 249 /* Rx descriptors status */ 250 #define MVGBE_CRC_ERROR 0 251 #define MVGBE_OVERRUN_ERROR (1 << 1) 252 #define MVGBE_MAX_FRAME_LENGTH_ERROR (1 << 2) 253 #define MVGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1)) 254 #define MVGBE_VLAN_TAGGED (1 << 19) 255 #define MVGBE_BPDU_FRAME (1 << 20) 256 #define MVGBE_TCP_FRAME_OVER_IP_V_4 0 257 #define MVGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21) 258 #define MVGBE_OTHER_FRAME_TYPE (1 << 22) 259 #define MVGBE_LAYER_2_IS_MVGBE_V_2 (1 << 23) 260 #define MVGBE_FRAME_TYPE_IP_V_4 (1 << 24) 261 #define MVGBE_FRAME_HEADER_OK (1 << 25) 262 #define MVGBE_RX_LAST_DESC (1 << 26) 263 #define MVGBE_RX_FIRST_DESC (1 << 27) 264 #define MVGBE_UNKNOWN_DESTINATION_ADDR (1 << 28) 265 #define MVGBE_RX_EN_INTERRUPT (1 << 29) 266 #define MVGBE_LAYER_4_CHECKSUM_OK (1 << 30) 267 268 /* Rx descriptors byte count */ 269 #define MVGBE_FRAME_FRAGMENTED (1 << 2) 270 271 /* Tx descriptors command */ 272 #define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10) 273 #define MVGBE_FRAME_SET_TO_VLAN (1 << 15) 274 #define MVGBE_TCP_FRAME 0 275 #define MVGBE_UDP_FRAME (1 << 16) 276 #define MVGBE_GEN_TCP_UDP_CHECKSUM (1 << 17) 277 #define MVGBE_GEN_IP_V_4_CHECKSUM (1 << 18) 278 #define MVGBE_ZERO_PADDING (1 << 19) 279 #define MVGBE_TX_LAST_DESC (1 << 20) 280 #define MVGBE_TX_FIRST_DESC (1 << 21) 281 #define MVGBE_GEN_CRC (1 << 22) 282 #define MVGBE_TX_EN_INTERRUPT (1 << 23) 283 #define MVGBE_AUTO_MODE (1 << 30) 284 285 /* Address decode parameters */ 286 /* Ethernet Base Address Register bits */ 287 #define EBAR_TARGET_DRAM 0x00000000 288 #define EBAR_TARGET_DEVICE 0x00000001 289 #define EBAR_TARGET_CBS 0x00000002 290 #define EBAR_TARGET_PCI0 0x00000003 291 #define EBAR_TARGET_PCI1 0x00000004 292 #define EBAR_TARGET_CUNIT 0x00000005 293 #define EBAR_TARGET_AUNIT 0x00000006 294 #define EBAR_TARGET_GUNIT 0x00000007 295 296 /* Window attrib */ 297 #define EBAR_DRAM_CS0 0x00000E00 298 #define EBAR_DRAM_CS1 0x00000D00 299 #define EBAR_DRAM_CS2 0x00000B00 300 #define EBAR_DRAM_CS3 0x00000700 301 302 /* DRAM Target interface */ 303 #define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000 304 #define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000 305 #define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000 306 307 /* Device Bus Target interface */ 308 #define EBAR_DEVICE_DEVCS0 0x00001E00 309 #define EBAR_DEVICE_DEVCS1 0x00001D00 310 #define EBAR_DEVICE_DEVCS2 0x00001B00 311 #define EBAR_DEVICE_DEVCS3 0x00001700 312 #define EBAR_DEVICE_BOOTCS3 0x00000F00 313 314 /* PCI Target interface */ 315 #define EBAR_PCI_BYTE_SWAP 0x00000000 316 #define EBAR_PCI_NO_SWAP 0x00000100 317 #define EBAR_PCI_BYTE_WORD_SWAP 0x00000200 318 #define EBAR_PCI_WORD_SWAP 0x00000300 319 #define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 320 #define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400 321 #define EBAR_PCI_IO_SPACE 0x00000000 322 #define EBAR_PCI_MEMORY_SPACE 0x00000800 323 #define EBAR_PCI_REQ64_FORCE 0x00000000 324 #define EBAR_PCI_REQ64_SIZE 0x00001000 325 326 /* Window access control */ 327 #define EWIN_ACCESS_NOT_ALLOWED 0 328 #define EWIN_ACCESS_READ_ONLY 1 329 #define EWIN_ACCESS_FULL ((1 << 1) | 1) 330 331 /* structures represents Controller registers */ 332 struct mvgbe_barsz { 333 u32 bar; 334 u32 size; 335 }; 336 337 struct mvgbe_rxcdp { 338 struct mvgbe_rxdesc *rxcdp; 339 u32 rxcdp_pad[3]; 340 }; 341 342 struct mvgbe_tqx { 343 u32 qxttbc; 344 u32 tqxtbc; 345 u32 tqxac; 346 u32 tqxpad; 347 }; 348 349 struct mvgbe_registers { 350 u32 phyadr; 351 u32 smi; 352 u32 euda; 353 u32 eudid; 354 u8 pad1[0x080 - 0x00c - 4]; 355 u32 euic; 356 u32 euim; 357 u8 pad2[0x094 - 0x084 - 4]; 358 u32 euea; 359 u32 euiae; 360 u8 pad3[0x0b0 - 0x098 - 4]; 361 u32 euc; 362 u8 pad3a[0x200 - 0x0b0 - 4]; 363 struct mvgbe_barsz barsz[6]; 364 u8 pad4[0x280 - 0x22c - 4]; 365 u32 ha_remap[4]; 366 u32 bare; 367 u32 epap; 368 u8 pad5[0x400 - 0x294 - 4]; 369 u32 pxc; 370 u32 pxcx; 371 u32 mii_ser_params; 372 u8 pad6[0x410 - 0x408 - 4]; 373 u32 evlane; 374 u32 macal; 375 u32 macah; 376 u32 sdc; 377 u32 dscp[7]; 378 u32 psc0; 379 u32 vpt2p; 380 u32 ps0; 381 u32 tqc; 382 u32 psc1; 383 u32 ps1; 384 u32 mrvl_header; 385 u8 pad7[0x460 - 0x454 - 4]; 386 u32 ic; 387 u32 ice; 388 u32 pim; 389 u32 peim; 390 u8 pad8[0x474 - 0x46c - 4]; 391 u32 pxtfut; 392 u32 pad9; 393 u32 pxmfs; 394 u32 pad10; 395 u32 pxdfc; 396 u32 pxofc; 397 u8 pad11[0x494 - 0x488 - 4]; 398 u32 peuiae; 399 u8 pad12[0x4bc - 0x494 - 4]; 400 u32 eth_type_prio; 401 u8 pad13[0x4dc - 0x4bc - 4]; 402 u32 tqfpc; 403 u32 pttbrc; 404 u32 tqc1; 405 u32 pmtu; 406 u32 pmtbs; 407 u8 pad14[0x60c - 0x4ec - 4]; 408 struct mvgbe_rxcdp rxcdp[7]; 409 struct mvgbe_rxdesc *rxcdp7; 410 u32 rqc; 411 struct mvgbe_txdesc *tcsdp; 412 u8 pad15[0x6c0 - 0x684 - 4]; 413 struct mvgbe_txdesc *tcqdp[8]; 414 u8 pad16[0x700 - 0x6dc - 4]; 415 struct mvgbe_tqx tqx[8]; 416 u32 pttbc; 417 u8 pad17[0x7a8 - 0x780 - 4]; 418 u32 tqxipg0; 419 u32 pad18[3]; 420 u32 tqxipg1; 421 u8 pad19[0x7c0 - 0x7b8 - 4]; 422 u32 hitkninlopkt; 423 u32 hitkninasyncpkt; 424 u32 lotkninasyncpkt; 425 u32 pad20; 426 u32 ts; 427 u8 pad21[0x3000 - 0x27d0 - 4]; 428 u32 pad20_1[32]; /* mib counter registes */ 429 u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32]; 430 u32 dfsmt[64]; 431 u32 dfomt[64]; 432 u32 dfut[4]; 433 u8 pad23[0xe20c0 - 0x7360c - 4]; 434 u32 pmbus_top_arbiter; 435 }; 436 437 /* structures/enums needed by driver */ 438 enum mvgbe_adrwin { 439 MVGBE_WIN0, 440 MVGBE_WIN1, 441 MVGBE_WIN2, 442 MVGBE_WIN3, 443 MVGBE_WIN4, 444 MVGBE_WIN5 445 }; 446 447 enum mvgbe_target { 448 MVGBE_TARGET_DRAM, 449 MVGBE_TARGET_DEV, 450 MVGBE_TARGET_CBS, 451 MVGBE_TARGET_PCI0, 452 MVGBE_TARGET_PCI1 453 }; 454 455 struct mvgbe_winparam { 456 enum mvgbe_adrwin win; /* Window number */ 457 enum mvgbe_target target; /* System targets */ 458 u16 attrib; /* BAR attrib. See above macros */ 459 u32 base_addr; /* Window base address in u32 form */ 460 u32 high_addr; /* Window high address in u32 form */ 461 u32 size; /* Size in MBytes. Must be % 64Kbyte. */ 462 int enable; /* Enable/disable access to the window. */ 463 u16 access_ctrl; /*Access ctrl register. see above macros */ 464 }; 465 466 struct mvgbe_rxdesc { 467 u32 cmd_sts; /* Descriptor command status */ 468 u16 buf_size; /* Buffer size */ 469 u16 byte_cnt; /* Descriptor buffer byte count */ 470 u8 *buf_ptr; /* Descriptor buffer pointer */ 471 struct mvgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */ 472 }; 473 474 struct mvgbe_txdesc { 475 u32 cmd_sts; /* Descriptor command status */ 476 u16 l4i_chk; /* CPU provided TCP Checksum */ 477 u16 byte_cnt; /* Descriptor buffer byte count */ 478 u8 *buf_ptr; /* Descriptor buffer ptr */ 479 struct mvgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */ 480 }; 481 482 /* port device data struct */ 483 struct mvgbe_device { 484 #ifndef CONFIG_DM_ETH 485 struct eth_device dev; 486 #endif 487 struct mvgbe_registers *regs; 488 struct mvgbe_txdesc *p_txdesc; 489 struct mvgbe_rxdesc *p_rxdesc; 490 struct mvgbe_rxdesc *p_rxdesc_curr; 491 u8 *p_rxbuf; 492 u8 *p_aligned_txbuf; 493 494 #ifdef CONFIG_DM_ETH 495 phy_interface_t phy_interface; 496 unsigned int link; 497 unsigned int duplex; 498 unsigned int speed; 499 500 int init; 501 int phyaddr; 502 struct phy_device *phydev; 503 struct mii_dev *bus; 504 #endif 505 }; 506 507 #endif /* __MVGBE_H__ */ 508