1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * based on - Driver for MV64360X ethernet ports 7 * Copyright (C) 2002 rabeeh@galileo.co.il 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 25 * MA 02110-1301 USA 26 */ 27 28 #ifndef __MVGBE_H__ 29 #define __MVGBE_H__ 30 31 /* PHY_BASE_ADR is board specific and can be configured */ 32 #if defined (CONFIG_PHY_BASE_ADR) 33 #define PHY_BASE_ADR CONFIG_PHY_BASE_ADR 34 #else 35 #define PHY_BASE_ADR 0x08 /* default phy base addr */ 36 #endif 37 38 /* Constants */ 39 #define INT_CAUSE_UNMASK_ALL 0x0007ffff 40 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff 41 #define MRU_MASK 0xfff1ffff 42 #define PHYADR_MASK 0x0000001f 43 #define PHYREG_MASK 0x0000001f 44 #define QTKNBKT_DEF_VAL 0x3fffffff 45 #define QMTBS_DEF_VAL 0x000003ff 46 #define QTKNRT_DEF_VAL 0x0000fcff 47 #define RXUQ 0 /* Used Rx queue */ 48 #define TXUQ 0 /* Used Rx queue */ 49 50 #define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev) 51 #define MVGBE_REG_WR(adr, val) writel(val, &adr) 52 #define MVGBE_REG_RD(adr) readl(&adr) 53 #define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr) 54 #define MVGBE_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr) 55 56 /* Default port configuration value */ 57 #define PRT_CFG_VAL ( \ 58 MVGBE_UCAST_MOD_NRML | \ 59 MVGBE_DFLT_RXQ(RXUQ) | \ 60 MVGBE_DFLT_RX_ARPQ(RXUQ) | \ 61 MVGBE_RX_BC_IF_NOT_IP_OR_ARP | \ 62 MVGBE_RX_BC_IF_IP | \ 63 MVGBE_RX_BC_IF_ARP | \ 64 MVGBE_CPTR_TCP_FRMS_DIS | \ 65 MVGBE_CPTR_UDP_FRMS_DIS | \ 66 MVGBE_DFLT_RX_TCPQ(RXUQ) | \ 67 MVGBE_DFLT_RX_UDPQ(RXUQ) | \ 68 MVGBE_DFLT_RX_BPDUQ(RXUQ)) 69 70 /* Default port extend configuration value */ 71 #define PORT_CFG_EXTEND_VALUE \ 72 MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \ 73 MVGBE_PARTITION_DIS | \ 74 MVGBE_TX_CRC_GENERATION_EN 75 76 #define GT_MVGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8) 77 78 /* Default sdma control value */ 79 #define PORT_SDMA_CFG_VALUE ( \ 80 MVGBE_RX_BURST_SIZE_16_64BIT | \ 81 MVGBE_BLM_RX_NO_SWAP | \ 82 MVGBE_BLM_TX_NO_SWAP | \ 83 GT_MVGBE_IPG_INT_RX(RXUQ) | \ 84 MVGBE_TX_BURST_SIZE_16_64BIT) 85 86 /* Default port serial control value */ 87 #define PORT_SERIAL_CONTROL_VALUE ( \ 88 MVGBE_FORCE_LINK_PASS | \ 89 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ 90 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ 91 MVGBE_ADV_NO_FLOW_CTRL | \ 92 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ 93 MVGBE_FORCE_BP_MODE_NO_JAM | \ 94 (1 << 9) /* Reserved bit has to be 1 */ | \ 95 MVGBE_DO_NOT_FORCE_LINK_FAIL | \ 96 MVGBE_EN_AUTO_NEG_SPEED_GMII | \ 97 MVGBE_DTE_ADV_0 | \ 98 MVGBE_MIIPHY_MAC_MODE | \ 99 MVGBE_AUTO_NEG_NO_CHANGE | \ 100 MVGBE_MAX_RX_PACKET_1552BYTE | \ 101 MVGBE_CLR_EXT_LOOPBACK | \ 102 MVGBE_SET_FULL_DUPLEX_MODE | \ 103 MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX) 104 105 /* Tx WRR confoguration macros */ 106 #define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */ 107 #define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */ 108 #define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */ 109 /* MAC accepet/reject macros */ 110 #define ACCEPT_MAC_ADDR 0 111 #define REJECT_MAC_ADDR 1 112 /* Size of a Tx/Rx descriptor used in chain list data structure */ 113 #define MV_RXQ_DESC_ALIGNED_SIZE \ 114 (((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN) 115 /* Buffer offset from buffer pointer */ 116 #define RX_BUF_OFFSET 0x2 117 118 /* Port serial status reg (PSR) */ 119 #define MVGBE_INTERFACE_GMII_MII 0 120 #define MVGBE_INTERFACE_PCM 1 121 #define MVGBE_LINK_IS_DOWN 0 122 #define MVGBE_LINK_IS_UP (1 << 1) 123 #define MVGBE_PORT_AT_HALF_DUPLEX 0 124 #define MVGBE_PORT_AT_FULL_DUPLEX (1 << 2) 125 #define MVGBE_RX_FLOW_CTRL_DISD 0 126 #define MVGBE_RX_FLOW_CTRL_ENBALED (1 << 3) 127 #define MVGBE_GMII_SPEED_100_10 0 128 #define MVGBE_GMII_SPEED_1000 (1 << 4) 129 #define MVGBE_MII_SPEED_10 0 130 #define MVGBE_MII_SPEED_100 (1 << 5) 131 #define MVGBE_NO_TX 0 132 #define MVGBE_TX_IN_PROGRESS (1 << 7) 133 #define MVGBE_BYPASS_NO_ACTIVE 0 134 #define MVGBE_BYPASS_ACTIVE (1 << 8) 135 #define MVGBE_PORT_NOT_AT_PARTN_STT 0 136 #define MVGBE_PORT_AT_PARTN_STT (1 << 9) 137 #define MVGBE_PORT_TX_FIFO_NOT_EMPTY 0 138 #define MVGBE_PORT_TX_FIFO_EMPTY (1 << 10) 139 140 /* These macros describes the Port configuration reg (Px_cR) bits */ 141 #define MVGBE_UCAST_MOD_NRML 0 142 #define MVGBE_UNICAST_PROMISCUOUS_MODE 1 143 #define MVGBE_DFLT_RXQ(_x) (_x << 1) 144 #define MVGBE_DFLT_RX_ARPQ(_x) (_x << 4) 145 #define MVGBE_RX_BC_IF_NOT_IP_OR_ARP 0 146 #define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7) 147 #define MVGBE_RX_BC_IF_IP 0 148 #define MVGBE_REJECT_BC_IF_IP (1 << 8) 149 #define MVGBE_RX_BC_IF_ARP 0 150 #define MVGBE_REJECT_BC_IF_ARP (1 << 9) 151 #define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12) 152 #define MVGBE_CPTR_TCP_FRMS_DIS 0 153 #define MVGBE_CPTR_TCP_FRMS_EN (1 << 14) 154 #define MVGBE_CPTR_UDP_FRMS_DIS 0 155 #define MVGBE_CPTR_UDP_FRMS_EN (1 << 15) 156 #define MVGBE_DFLT_RX_TCPQ(_x) (_x << 16) 157 #define MVGBE_DFLT_RX_UDPQ(_x) (_x << 19) 158 #define MVGBE_DFLT_RX_BPDUQ(_x) (_x << 22) 159 #define MVGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25) 160 161 /* These macros describes the Port configuration extend reg (Px_cXR) bits*/ 162 #define MVGBE_CLASSIFY_EN 1 163 #define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0 164 #define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1) 165 #define MVGBE_PARTITION_DIS 0 166 #define MVGBE_PARTITION_EN (1 << 2) 167 #define MVGBE_TX_CRC_GENERATION_EN 0 168 #define MVGBE_TX_CRC_GENERATION_DIS (1 << 3) 169 170 /* These macros describes the Port Sdma configuration reg (SDCR) bits */ 171 #define MVGBE_RIFB 1 172 #define MVGBE_RX_BURST_SIZE_1_64BIT 0 173 #define MVGBE_RX_BURST_SIZE_2_64BIT (1 << 1) 174 #define MVGBE_RX_BURST_SIZE_4_64BIT (1 << 2) 175 #define MVGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1)) 176 #define MVGBE_RX_BURST_SIZE_16_64BIT (1 << 3) 177 #define MVGBE_BLM_RX_NO_SWAP (1 << 4) 178 #define MVGBE_BLM_RX_BYTE_SWAP 0 179 #define MVGBE_BLM_TX_NO_SWAP (1 << 5) 180 #define MVGBE_BLM_TX_BYTE_SWAP 0 181 #define MVGBE_DESCRIPTORS_BYTE_SWAP (1 << 6) 182 #define MVGBE_DESCRIPTORS_NO_SWAP 0 183 #define MVGBE_TX_BURST_SIZE_1_64BIT 0 184 #define MVGBE_TX_BURST_SIZE_2_64BIT (1 << 22) 185 #define MVGBE_TX_BURST_SIZE_4_64BIT (1 << 23) 186 #define MVGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22)) 187 #define MVGBE_TX_BURST_SIZE_16_64BIT (1 << 24) 188 189 /* These macros describes the Port serial control reg (PSCR) bits */ 190 #define MVGBE_SERIAL_PORT_DIS 0 191 #define MVGBE_SERIAL_PORT_EN 1 192 #define MVGBE_FORCE_LINK_PASS (1 << 1) 193 #define MVGBE_DO_NOT_FORCE_LINK_PASS 0 194 #define MVGBE_EN_AUTO_NEG_FOR_DUPLX 0 195 #define MVGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2) 196 #define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0 197 #define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3) 198 #define MVGBE_ADV_NO_FLOW_CTRL 0 199 #define MVGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4) 200 #define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 201 #define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5) 202 #define MVGBE_FORCE_BP_MODE_NO_JAM 0 203 #define MVGBE_FORCE_BP_MODE_JAM_TX (1 << 7) 204 #define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8) 205 #define MVGBE_FORCE_LINK_FAIL 0 206 #define MVGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10) 207 #define MVGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13) 208 #define MVGBE_EN_AUTO_NEG_SPEED_GMII 0 209 #define MVGBE_DTE_ADV_0 0 210 #define MVGBE_DTE_ADV_1 (1 << 14) 211 #define MVGBE_MIIPHY_MAC_MODE 0 212 #define MVGBE_MIIPHY_PHY_MODE (1 << 15) 213 #define MVGBE_AUTO_NEG_NO_CHANGE 0 214 #define MVGBE_RESTART_AUTO_NEG (1 << 16) 215 #define MVGBE_MAX_RX_PACKET_1518BYTE 0 216 #define MVGBE_MAX_RX_PACKET_1522BYTE (1 << 17) 217 #define MVGBE_MAX_RX_PACKET_1552BYTE (1 << 18) 218 #define MVGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17)) 219 #define MVGBE_MAX_RX_PACKET_9192BYTE (1 << 19) 220 #define MVGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17)) 221 #define MVGBE_SET_EXT_LOOPBACK (1 << 20) 222 #define MVGBE_CLR_EXT_LOOPBACK 0 223 #define MVGBE_SET_FULL_DUPLEX_MODE (1 << 21) 224 #define MVGBE_SET_HALF_DUPLEX_MODE 0 225 #define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22) 226 #define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 227 #define MVGBE_SET_GMII_SPEED_TO_10_100 0 228 #define MVGBE_SET_GMII_SPEED_TO_1000 (1 << 23) 229 #define MVGBE_SET_MII_SPEED_TO_10 0 230 #define MVGBE_SET_MII_SPEED_TO_100 (1 << 24) 231 232 /* SMI register fields */ 233 #define MVGBE_PHY_SMI_TIMEOUT 10000 234 #define MVGBE_PHY_SMI_DATA_OFFS 0 /* Data */ 235 #define MVGBE_PHY_SMI_DATA_MASK (0xffff << MVGBE_PHY_SMI_DATA_OFFS) 236 #define MVGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */ 237 #define MVGBE_PHY_SMI_DEV_ADDR_MASK \ 238 (PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS) 239 #define MVGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */ 240 #define MVGBE_SMI_REG_ADDR_MASK \ 241 (PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS) 242 #define MVGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */ 243 #define MVGBE_PHY_SMI_OPCODE_MASK (3 << MVGBE_PHY_SMI_OPCODE_OFFS) 244 #define MVGBE_PHY_SMI_OPCODE_WRITE (0 << MVGBE_PHY_SMI_OPCODE_OFFS) 245 #define MVGBE_PHY_SMI_OPCODE_READ (1 << MVGBE_PHY_SMI_OPCODE_OFFS) 246 #define MVGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */ 247 #define MVGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */ 248 249 /* SDMA command status fields macros */ 250 /* Tx & Rx descriptors status */ 251 #define MVGBE_ERROR_SUMMARY 1 252 /* Tx & Rx descriptors command */ 253 #define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31) 254 /* Tx descriptors status */ 255 #define MVGBE_LC_ERROR 0 256 #define MVGBE_UR_ERROR (1 << 1) 257 #define MVGBE_RL_ERROR (1 << 2) 258 #define MVGBE_LLC_SNAP_FORMAT (1 << 9) 259 #define MVGBE_TX_LAST_FRAME (1 << 20) 260 261 /* Rx descriptors status */ 262 #define MVGBE_CRC_ERROR 0 263 #define MVGBE_OVERRUN_ERROR (1 << 1) 264 #define MVGBE_MAX_FRAME_LENGTH_ERROR (1 << 2) 265 #define MVGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1)) 266 #define MVGBE_VLAN_TAGGED (1 << 19) 267 #define MVGBE_BPDU_FRAME (1 << 20) 268 #define MVGBE_TCP_FRAME_OVER_IP_V_4 0 269 #define MVGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21) 270 #define MVGBE_OTHER_FRAME_TYPE (1 << 22) 271 #define MVGBE_LAYER_2_IS_MVGBE_V_2 (1 << 23) 272 #define MVGBE_FRAME_TYPE_IP_V_4 (1 << 24) 273 #define MVGBE_FRAME_HEADER_OK (1 << 25) 274 #define MVGBE_RX_LAST_DESC (1 << 26) 275 #define MVGBE_RX_FIRST_DESC (1 << 27) 276 #define MVGBE_UNKNOWN_DESTINATION_ADDR (1 << 28) 277 #define MVGBE_RX_EN_INTERRUPT (1 << 29) 278 #define MVGBE_LAYER_4_CHECKSUM_OK (1 << 30) 279 280 /* Rx descriptors byte count */ 281 #define MVGBE_FRAME_FRAGMENTED (1 << 2) 282 283 /* Tx descriptors command */ 284 #define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10) 285 #define MVGBE_FRAME_SET_TO_VLAN (1 << 15) 286 #define MVGBE_TCP_FRAME 0 287 #define MVGBE_UDP_FRAME (1 << 16) 288 #define MVGBE_GEN_TCP_UDP_CHECKSUM (1 << 17) 289 #define MVGBE_GEN_IP_V_4_CHECKSUM (1 << 18) 290 #define MVGBE_ZERO_PADDING (1 << 19) 291 #define MVGBE_TX_LAST_DESC (1 << 20) 292 #define MVGBE_TX_FIRST_DESC (1 << 21) 293 #define MVGBE_GEN_CRC (1 << 22) 294 #define MVGBE_TX_EN_INTERRUPT (1 << 23) 295 #define MVGBE_AUTO_MODE (1 << 30) 296 297 /* Address decode parameters */ 298 /* Ethernet Base Address Register bits */ 299 #define EBAR_TARGET_DRAM 0x00000000 300 #define EBAR_TARGET_DEVICE 0x00000001 301 #define EBAR_TARGET_CBS 0x00000002 302 #define EBAR_TARGET_PCI0 0x00000003 303 #define EBAR_TARGET_PCI1 0x00000004 304 #define EBAR_TARGET_CUNIT 0x00000005 305 #define EBAR_TARGET_AUNIT 0x00000006 306 #define EBAR_TARGET_GUNIT 0x00000007 307 308 /* Window attrib */ 309 #define EBAR_DRAM_CS0 0x00000E00 310 #define EBAR_DRAM_CS1 0x00000D00 311 #define EBAR_DRAM_CS2 0x00000B00 312 #define EBAR_DRAM_CS3 0x00000700 313 314 /* DRAM Target interface */ 315 #define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000 316 #define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000 317 #define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000 318 319 /* Device Bus Target interface */ 320 #define EBAR_DEVICE_DEVCS0 0x00001E00 321 #define EBAR_DEVICE_DEVCS1 0x00001D00 322 #define EBAR_DEVICE_DEVCS2 0x00001B00 323 #define EBAR_DEVICE_DEVCS3 0x00001700 324 #define EBAR_DEVICE_BOOTCS3 0x00000F00 325 326 /* PCI Target interface */ 327 #define EBAR_PCI_BYTE_SWAP 0x00000000 328 #define EBAR_PCI_NO_SWAP 0x00000100 329 #define EBAR_PCI_BYTE_WORD_SWAP 0x00000200 330 #define EBAR_PCI_WORD_SWAP 0x00000300 331 #define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000 332 #define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400 333 #define EBAR_PCI_IO_SPACE 0x00000000 334 #define EBAR_PCI_MEMORY_SPACE 0x00000800 335 #define EBAR_PCI_REQ64_FORCE 0x00000000 336 #define EBAR_PCI_REQ64_SIZE 0x00001000 337 338 /* Window access control */ 339 #define EWIN_ACCESS_NOT_ALLOWED 0 340 #define EWIN_ACCESS_READ_ONLY 1 341 #define EWIN_ACCESS_FULL ((1 << 1) | 1) 342 343 /* structures represents Controller registers */ 344 struct mvgbe_barsz { 345 u32 bar; 346 u32 size; 347 }; 348 349 struct mvgbe_rxcdp { 350 struct mvgbe_rxdesc *rxcdp; 351 u32 rxcdp_pad[3]; 352 }; 353 354 struct mvgbe_tqx { 355 u32 qxttbc; 356 u32 tqxtbc; 357 u32 tqxac; 358 u32 tqxpad; 359 }; 360 361 struct mvgbe_registers { 362 u32 phyadr; 363 u32 smi; 364 u32 euda; 365 u32 eudid; 366 u8 pad1[0x080 - 0x00c - 4]; 367 u32 euic; 368 u32 euim; 369 u8 pad2[0x094 - 0x084 - 4]; 370 u32 euea; 371 u32 euiae; 372 u8 pad3[0x0b0 - 0x098 - 4]; 373 u32 euc; 374 u8 pad3a[0x200 - 0x0b0 - 4]; 375 struct mvgbe_barsz barsz[6]; 376 u8 pad4[0x280 - 0x22c - 4]; 377 u32 ha_remap[4]; 378 u32 bare; 379 u32 epap; 380 u8 pad5[0x400 - 0x294 - 4]; 381 u32 pxc; 382 u32 pxcx; 383 u32 mii_ser_params; 384 u8 pad6[0x410 - 0x408 - 4]; 385 u32 evlane; 386 u32 macal; 387 u32 macah; 388 u32 sdc; 389 u32 dscp[7]; 390 u32 psc0; 391 u32 vpt2p; 392 u32 ps0; 393 u32 tqc; 394 u32 psc1; 395 u32 ps1; 396 u32 mrvl_header; 397 u8 pad7[0x460 - 0x454 - 4]; 398 u32 ic; 399 u32 ice; 400 u32 pim; 401 u32 peim; 402 u8 pad8[0x474 - 0x46c - 4]; 403 u32 pxtfut; 404 u32 pad9; 405 u32 pxmfs; 406 u32 pad10; 407 u32 pxdfc; 408 u32 pxofc; 409 u8 pad11[0x494 - 0x488 - 4]; 410 u32 peuiae; 411 u8 pad12[0x4bc - 0x494 - 4]; 412 u32 eth_type_prio; 413 u8 pad13[0x4dc - 0x4bc - 4]; 414 u32 tqfpc; 415 u32 pttbrc; 416 u32 tqc1; 417 u32 pmtu; 418 u32 pmtbs; 419 u8 pad14[0x60c - 0x4ec - 4]; 420 struct mvgbe_rxcdp rxcdp[7]; 421 struct mvgbe_rxdesc *rxcdp7; 422 u32 rqc; 423 struct mvgbe_txdesc *tcsdp; 424 u8 pad15[0x6c0 - 0x684 - 4]; 425 struct mvgbe_txdesc *tcqdp[8]; 426 u8 pad16[0x700 - 0x6dc - 4]; 427 struct mvgbe_tqx tqx[8]; 428 u32 pttbc; 429 u8 pad17[0x7a8 - 0x780 - 4]; 430 u32 tqxipg0; 431 u32 pad18[3]; 432 u32 tqxipg1; 433 u8 pad19[0x7c0 - 0x7b8 - 4]; 434 u32 hitkninlopkt; 435 u32 hitkninasyncpkt; 436 u32 lotkninasyncpkt; 437 u32 pad20; 438 u32 ts; 439 u8 pad21[0x3000 - 0x27d0 - 4]; 440 u32 pad20_1[32]; /* mib counter registes */ 441 u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32]; 442 u32 dfsmt[64]; 443 u32 dfomt[64]; 444 u32 dfut[4]; 445 u8 pad23[0xe20c0 - 0x7360c - 4]; 446 u32 pmbus_top_arbiter; 447 }; 448 449 /* structures/enums needed by driver */ 450 enum mvgbe_adrwin { 451 MVGBE_WIN0, 452 MVGBE_WIN1, 453 MVGBE_WIN2, 454 MVGBE_WIN3, 455 MVGBE_WIN4, 456 MVGBE_WIN5 457 }; 458 459 enum mvgbe_target { 460 MVGBE_TARGET_DRAM, 461 MVGBE_TARGET_DEV, 462 MVGBE_TARGET_CBS, 463 MVGBE_TARGET_PCI0, 464 MVGBE_TARGET_PCI1 465 }; 466 467 struct mvgbe_winparam { 468 enum mvgbe_adrwin win; /* Window number */ 469 enum mvgbe_target target; /* System targets */ 470 u16 attrib; /* BAR attrib. See above macros */ 471 u32 base_addr; /* Window base address in u32 form */ 472 u32 high_addr; /* Window high address in u32 form */ 473 u32 size; /* Size in MBytes. Must be % 64Kbyte. */ 474 int enable; /* Enable/disable access to the window. */ 475 u16 access_ctrl; /*Access ctrl register. see above macros */ 476 }; 477 478 struct mvgbe_rxdesc { 479 u32 cmd_sts; /* Descriptor command status */ 480 u16 buf_size; /* Buffer size */ 481 u16 byte_cnt; /* Descriptor buffer byte count */ 482 u8 *buf_ptr; /* Descriptor buffer pointer */ 483 struct mvgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */ 484 }; 485 486 struct mvgbe_txdesc { 487 u32 cmd_sts; /* Descriptor command status */ 488 u16 l4i_chk; /* CPU provided TCP Checksum */ 489 u16 byte_cnt; /* Descriptor buffer byte count */ 490 u8 *buf_ptr; /* Descriptor buffer ptr */ 491 struct mvgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */ 492 }; 493 494 /* port device data struct */ 495 struct mvgbe_device { 496 struct eth_device dev; 497 struct mvgbe_registers *regs; 498 struct mvgbe_txdesc *p_txdesc; 499 struct mvgbe_rxdesc *p_rxdesc; 500 struct mvgbe_rxdesc *p_rxdesc_curr; 501 u8 *p_rxbuf; 502 u8 *p_aligned_txbuf; 503 }; 504 505 #endif /* __MVGBE_H__ */ 506