1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2009 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 * 7 * (C) Copyright 2003 8 * Ingo Assmus <ingo.assmus@keymile.com> 9 * 10 * based on - Driver for MV64360X ethernet ports 11 * Copyright (C) 2002 rabeeh@galileo.co.il 12 */ 13 14 #include <common.h> 15 #include <net.h> 16 #include <malloc.h> 17 #include <miiphy.h> 18 #include <asm/io.h> 19 #include <linux/errno.h> 20 #include <asm/types.h> 21 #include <asm/system.h> 22 #include <asm/byteorder.h> 23 #include <asm/arch/cpu.h> 24 25 #if defined(CONFIG_KIRKWOOD) 26 #include <asm/arch/soc.h> 27 #elif defined(CONFIG_ORION5X) 28 #include <asm/arch/orion5x.h> 29 #endif 30 31 #include "mvgbe.h" 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #ifndef CONFIG_MVGBE_PORTS 36 # define CONFIG_MVGBE_PORTS {0, 0} 37 #endif 38 39 #define MV_PHY_ADR_REQUEST 0xee 40 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) 41 42 #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 43 /* 44 * smi_reg_read - miiphy_read callback function. 45 * 46 * Returns 16bit phy register value, or 0xffff on error 47 */ 48 static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad, 49 int reg_ofs) 50 { 51 u16 data = 0; 52 struct eth_device *dev = eth_get_dev_by_name(bus->name); 53 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 54 struct mvgbe_registers *regs = dmvgbe->regs; 55 u32 smi_reg; 56 u32 timeout; 57 58 /* Phyadr read request */ 59 if (phy_adr == MV_PHY_ADR_REQUEST && 60 reg_ofs == MV_PHY_ADR_REQUEST) { 61 /* */ 62 data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK); 63 return data; 64 } 65 /* check parameters */ 66 if (phy_adr > PHYADR_MASK) { 67 printf("Err..(%s) Invalid PHY address %d\n", 68 __func__, phy_adr); 69 return -EFAULT; 70 } 71 if (reg_ofs > PHYREG_MASK) { 72 printf("Err..(%s) Invalid register offset %d\n", 73 __func__, reg_ofs); 74 return -EFAULT; 75 } 76 77 timeout = MVGBE_PHY_SMI_TIMEOUT; 78 /* wait till the SMI is not busy */ 79 do { 80 /* read smi register */ 81 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); 82 if (timeout-- == 0) { 83 printf("Err..(%s) SMI busy timeout\n", __func__); 84 return -EFAULT; 85 } 86 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); 87 88 /* fill the phy address and regiser offset and read opcode */ 89 smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) 90 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS) 91 | MVGBE_PHY_SMI_OPCODE_READ; 92 93 /* write the smi register */ 94 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); 95 96 /*wait till read value is ready */ 97 timeout = MVGBE_PHY_SMI_TIMEOUT; 98 99 do { 100 /* read smi register */ 101 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); 102 if (timeout-- == 0) { 103 printf("Err..(%s) SMI read ready timeout\n", 104 __func__); 105 return -EFAULT; 106 } 107 } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK)); 108 109 /* Wait for the data to update in the SMI register */ 110 for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++) 111 ; 112 113 data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK); 114 115 debug("%s:(adr %d, off %d) value= %04x\n", __func__, phy_adr, reg_ofs, 116 data); 117 118 return data; 119 } 120 121 /* 122 * smi_reg_write - imiiphy_write callback function. 123 * 124 * Returns 0 if write succeed, -EINVAL on bad parameters 125 * -ETIME on timeout 126 */ 127 static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad, 128 int reg_ofs, u16 data) 129 { 130 struct eth_device *dev = eth_get_dev_by_name(bus->name); 131 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 132 struct mvgbe_registers *regs = dmvgbe->regs; 133 u32 smi_reg; 134 u32 timeout; 135 136 /* Phyadr write request*/ 137 if (phy_adr == MV_PHY_ADR_REQUEST && 138 reg_ofs == MV_PHY_ADR_REQUEST) { 139 MVGBE_REG_WR(regs->phyadr, data); 140 return 0; 141 } 142 143 /* check parameters */ 144 if (phy_adr > PHYADR_MASK) { 145 printf("Err..(%s) Invalid phy address\n", __func__); 146 return -EINVAL; 147 } 148 if (reg_ofs > PHYREG_MASK) { 149 printf("Err..(%s) Invalid register offset\n", __func__); 150 return -EINVAL; 151 } 152 153 /* wait till the SMI is not busy */ 154 timeout = MVGBE_PHY_SMI_TIMEOUT; 155 do { 156 /* read smi register */ 157 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); 158 if (timeout-- == 0) { 159 printf("Err..(%s) SMI busy timeout\n", __func__); 160 return -ETIME; 161 } 162 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); 163 164 /* fill the phy addr and reg offset and write opcode and data */ 165 smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS); 166 smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) 167 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS); 168 smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ; 169 170 /* write the smi register */ 171 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); 172 173 return 0; 174 } 175 #endif 176 177 /* Stop and checks all queues */ 178 static void stop_queue(u32 * qreg) 179 { 180 u32 reg_data; 181 182 reg_data = readl(qreg); 183 184 if (reg_data & 0xFF) { 185 /* Issue stop command for active channels only */ 186 writel((reg_data << 8), qreg); 187 188 /* Wait for all queue activity to terminate. */ 189 do { 190 /* 191 * Check port cause register that all queues 192 * are stopped 193 */ 194 reg_data = readl(qreg); 195 } 196 while (reg_data & 0xFF); 197 } 198 } 199 200 /* 201 * set_access_control - Config address decode parameters for Ethernet unit 202 * 203 * This function configures the address decode parameters for the Gigabit 204 * Ethernet Controller according the given parameters struct. 205 * 206 * @regs Register struct pointer. 207 * @param Address decode parameter struct. 208 */ 209 static void set_access_control(struct mvgbe_registers *regs, 210 struct mvgbe_winparam *param) 211 { 212 u32 access_prot_reg; 213 214 /* Set access control register */ 215 access_prot_reg = MVGBE_REG_RD(regs->epap); 216 /* clear window permission */ 217 access_prot_reg &= (~(3 << (param->win * 2))); 218 access_prot_reg |= (param->access_ctrl << (param->win * 2)); 219 MVGBE_REG_WR(regs->epap, access_prot_reg); 220 221 /* Set window Size reg (SR) */ 222 MVGBE_REG_WR(regs->barsz[param->win].size, 223 (((param->size / 0x10000) - 1) << 16)); 224 225 /* Set window Base address reg (BA) */ 226 MVGBE_REG_WR(regs->barsz[param->win].bar, 227 (param->target | param->attrib | param->base_addr)); 228 /* High address remap reg (HARR) */ 229 if (param->win < 4) 230 MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr); 231 232 /* Base address enable reg (BARER) */ 233 if (param->enable == 1) 234 MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win)); 235 else 236 MVGBE_REG_BITS_SET(regs->bare, (1 << param->win)); 237 } 238 239 static void set_dram_access(struct mvgbe_registers *regs) 240 { 241 struct mvgbe_winparam win_param; 242 int i; 243 244 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 245 /* Set access parameters for DRAM bank i */ 246 win_param.win = i; /* Use Ethernet window i */ 247 /* Window target - DDR */ 248 win_param.target = MVGBE_TARGET_DRAM; 249 /* Enable full access */ 250 win_param.access_ctrl = EWIN_ACCESS_FULL; 251 win_param.high_addr = 0; 252 /* Get bank base and size */ 253 win_param.base_addr = gd->bd->bi_dram[i].start; 254 win_param.size = gd->bd->bi_dram[i].size; 255 if (win_param.size == 0) 256 win_param.enable = 0; 257 else 258 win_param.enable = 1; /* Enable the access */ 259 260 /* Enable DRAM bank */ 261 switch (i) { 262 case 0: 263 win_param.attrib = EBAR_DRAM_CS0; 264 break; 265 case 1: 266 win_param.attrib = EBAR_DRAM_CS1; 267 break; 268 case 2: 269 win_param.attrib = EBAR_DRAM_CS2; 270 break; 271 case 3: 272 win_param.attrib = EBAR_DRAM_CS3; 273 break; 274 default: 275 /* invalid bank, disable access */ 276 win_param.enable = 0; 277 win_param.attrib = 0; 278 break; 279 } 280 /* Set the access control for address window(EPAPR) RD/WR */ 281 set_access_control(regs, &win_param); 282 } 283 } 284 285 /* 286 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables 287 * 288 * Go through all the DA filter tables (Unicast, Special Multicast & Other 289 * Multicast) and set each entry to 0. 290 */ 291 static void port_init_mac_tables(struct mvgbe_registers *regs) 292 { 293 int table_index; 294 295 /* Clear DA filter unicast table (Ex_dFUT) */ 296 for (table_index = 0; table_index < 4; ++table_index) 297 MVGBE_REG_WR(regs->dfut[table_index], 0); 298 299 for (table_index = 0; table_index < 64; ++table_index) { 300 /* Clear DA filter special multicast table (Ex_dFSMT) */ 301 MVGBE_REG_WR(regs->dfsmt[table_index], 0); 302 /* Clear DA filter other multicast table (Ex_dFOMT) */ 303 MVGBE_REG_WR(regs->dfomt[table_index], 0); 304 } 305 } 306 307 /* 308 * port_uc_addr - This function Set the port unicast address table 309 * 310 * This function locates the proper entry in the Unicast table for the 311 * specified MAC nibble and sets its properties according to function 312 * parameters. 313 * This function add/removes MAC addresses from the port unicast address 314 * table. 315 * 316 * @uc_nibble Unicast MAC Address last nibble. 317 * @option 0 = Add, 1 = remove address. 318 * 319 * RETURN: 1 if output succeeded. 0 if option parameter is invalid. 320 */ 321 static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble, 322 int option) 323 { 324 u32 unicast_reg; 325 u32 tbl_offset; 326 u32 reg_offset; 327 328 /* Locate the Unicast table entry */ 329 uc_nibble = (0xf & uc_nibble); 330 /* Register offset from unicast table base */ 331 tbl_offset = (uc_nibble / 4); 332 /* Entry offset within the above register */ 333 reg_offset = uc_nibble % 4; 334 335 switch (option) { 336 case REJECT_MAC_ADDR: 337 /* 338 * Clear accepts frame bit at specified unicast 339 * DA table entry 340 */ 341 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); 342 unicast_reg &= (0xFF << (8 * reg_offset)); 343 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); 344 break; 345 case ACCEPT_MAC_ADDR: 346 /* Set accepts frame bit at unicast DA filter table entry */ 347 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); 348 unicast_reg &= (0xFF << (8 * reg_offset)); 349 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); 350 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); 351 break; 352 default: 353 return 0; 354 } 355 return 1; 356 } 357 358 /* 359 * port_uc_addr_set - This function Set the port Unicast address. 360 */ 361 static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr) 362 { 363 u32 mac_h; 364 u32 mac_l; 365 366 mac_l = (p_addr[4] << 8) | (p_addr[5]); 367 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | 368 (p_addr[3] << 0); 369 370 MVGBE_REG_WR(regs->macal, mac_l); 371 MVGBE_REG_WR(regs->macah, mac_h); 372 373 /* Accept frames of this address */ 374 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR); 375 } 376 377 /* 378 * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. 379 */ 380 static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe) 381 { 382 struct mvgbe_rxdesc *p_rx_desc; 383 int i; 384 385 /* initialize the Rx descriptors ring */ 386 p_rx_desc = dmvgbe->p_rxdesc; 387 for (i = 0; i < RINGSZ; i++) { 388 p_rx_desc->cmd_sts = 389 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; 390 p_rx_desc->buf_size = PKTSIZE_ALIGN; 391 p_rx_desc->byte_cnt = 0; 392 p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN; 393 if (i == (RINGSZ - 1)) 394 p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc; 395 else { 396 p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *) 397 ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE); 398 p_rx_desc = p_rx_desc->nxtdesc_p; 399 } 400 } 401 dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc; 402 } 403 404 static int mvgbe_init(struct eth_device *dev) 405 { 406 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 407 struct mvgbe_registers *regs = dmvgbe->regs; 408 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ 409 !defined(CONFIG_PHYLIB) && \ 410 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) 411 int i; 412 #endif 413 /* setup RX rings */ 414 mvgbe_init_rx_desc_ring(dmvgbe); 415 416 /* Clear the ethernet port interrupts */ 417 MVGBE_REG_WR(regs->ic, 0); 418 MVGBE_REG_WR(regs->ice, 0); 419 /* Unmask RX buffer and TX end interrupt */ 420 MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL); 421 /* Unmask phy and link status changes interrupts */ 422 MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT); 423 424 set_dram_access(regs); 425 port_init_mac_tables(regs); 426 port_uc_addr_set(regs, dmvgbe->dev.enetaddr); 427 428 /* Assign port configuration and command. */ 429 MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL); 430 MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); 431 MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); 432 433 /* Assign port SDMA configuration */ 434 MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); 435 MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL); 436 MVGBE_REG_WR(regs->tqx[0].tqxtbc, 437 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL); 438 /* Turn off the port/RXUQ bandwidth limitation */ 439 MVGBE_REG_WR(regs->pmtu, 0); 440 441 /* Set maximum receive buffer to 9700 bytes */ 442 MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE 443 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK)); 444 445 /* Enable port initially */ 446 MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN); 447 448 /* 449 * Set ethernet MTU for leaky bucket mechanism to 0 - this will 450 * disable the leaky bucket mechanism . 451 */ 452 MVGBE_REG_WR(regs->pmtu, 0); 453 454 /* Assignment of Rx CRDB of given RXUQ */ 455 MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr); 456 /* ensure previous write is done before enabling Rx DMA */ 457 isb(); 458 /* Enable port Rx. */ 459 MVGBE_REG_WR(regs->rqc, (1 << RXUQ)); 460 461 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ 462 !defined(CONFIG_PHYLIB) && \ 463 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) 464 /* Wait up to 5s for the link status */ 465 for (i = 0; i < 5; i++) { 466 u16 phyadr; 467 468 miiphy_read(dev->name, MV_PHY_ADR_REQUEST, 469 MV_PHY_ADR_REQUEST, &phyadr); 470 /* Return if we get link up */ 471 if (miiphy_link(dev->name, phyadr)) 472 return 0; 473 udelay(1000000); 474 } 475 476 printf("No link on %s\n", dev->name); 477 return -1; 478 #endif 479 return 0; 480 } 481 482 static int mvgbe_halt(struct eth_device *dev) 483 { 484 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 485 struct mvgbe_registers *regs = dmvgbe->regs; 486 487 /* Disable all gigE address decoder */ 488 MVGBE_REG_WR(regs->bare, 0x3f); 489 490 stop_queue(®s->tqc); 491 stop_queue(®s->rqc); 492 493 /* Disable port */ 494 MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN); 495 /* Set port is not reset */ 496 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4); 497 #ifdef CONFIG_SYS_MII_MODE 498 /* Set MMI interface up */ 499 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3); 500 #endif 501 /* Disable & mask ethernet port interrupts */ 502 MVGBE_REG_WR(regs->ic, 0); 503 MVGBE_REG_WR(regs->ice, 0); 504 MVGBE_REG_WR(regs->pim, 0); 505 MVGBE_REG_WR(regs->peim, 0); 506 507 return 0; 508 } 509 510 static int mvgbe_write_hwaddr(struct eth_device *dev) 511 { 512 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 513 struct mvgbe_registers *regs = dmvgbe->regs; 514 515 /* Programs net device MAC address after initialization */ 516 port_uc_addr_set(regs, dmvgbe->dev.enetaddr); 517 return 0; 518 } 519 520 static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize) 521 { 522 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 523 struct mvgbe_registers *regs = dmvgbe->regs; 524 struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc; 525 void *p = (void *)dataptr; 526 u32 cmd_sts; 527 u32 txuq0_reg_addr; 528 529 /* Copy buffer if it's misaligned */ 530 if ((u32) dataptr & 0x07) { 531 if (datasize > PKTSIZE_ALIGN) { 532 printf("Non-aligned data too large (%d)\n", 533 datasize); 534 return -1; 535 } 536 537 memcpy(dmvgbe->p_aligned_txbuf, p, datasize); 538 p = dmvgbe->p_aligned_txbuf; 539 } 540 541 p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC; 542 p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC; 543 p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA; 544 p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT; 545 p_txdesc->buf_ptr = (u8 *) p; 546 p_txdesc->byte_cnt = datasize; 547 548 /* Set this tc desc as zeroth TXUQ */ 549 txuq0_reg_addr = (u32)®s->tcqdp[TXUQ]; 550 writel((u32) p_txdesc, txuq0_reg_addr); 551 552 /* ensure tx desc writes above are performed before we start Tx DMA */ 553 isb(); 554 555 /* Apply send command using zeroth TXUQ */ 556 MVGBE_REG_WR(regs->tqc, (1 << TXUQ)); 557 558 /* 559 * wait for packet xmit completion 560 */ 561 cmd_sts = readl(&p_txdesc->cmd_sts); 562 while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) { 563 /* return fail if error is detected */ 564 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) == 565 (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) && 566 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) { 567 printf("Err..(%s) in xmit packet\n", __func__); 568 return -1; 569 } 570 cmd_sts = readl(&p_txdesc->cmd_sts); 571 }; 572 return 0; 573 } 574 575 static int mvgbe_recv(struct eth_device *dev) 576 { 577 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 578 struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr; 579 u32 cmd_sts; 580 u32 timeout = 0; 581 u32 rxdesc_curr_addr; 582 583 /* wait untill rx packet available or timeout */ 584 do { 585 if (timeout < MVGBE_PHY_SMI_TIMEOUT) 586 timeout++; 587 else { 588 debug("%s time out...\n", __func__); 589 return -1; 590 } 591 } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA); 592 593 if (p_rxdesc_curr->byte_cnt != 0) { 594 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n", 595 __func__, (u32) p_rxdesc_curr->byte_cnt, 596 (u32) p_rxdesc_curr->buf_ptr, 597 (u32) p_rxdesc_curr->cmd_sts); 598 } 599 600 /* 601 * In case received a packet without first/last bits on 602 * OR the error summary bit is on, 603 * the packets needs to be dropeed. 604 */ 605 cmd_sts = readl(&p_rxdesc_curr->cmd_sts); 606 607 if ((cmd_sts & 608 (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) 609 != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) { 610 611 printf("Err..(%s) Dropping packet spread on" 612 " multiple descriptors\n", __func__); 613 614 } else if (cmd_sts & MVGBE_ERROR_SUMMARY) { 615 616 printf("Err..(%s) Dropping packet with errors\n", 617 __func__); 618 619 } else { 620 /* !!! call higher layer processing */ 621 debug("%s: Sending Received packet to" 622 " upper layer (net_process_received_packet)\n", 623 __func__); 624 625 /* let the upper layer handle the packet */ 626 net_process_received_packet((p_rxdesc_curr->buf_ptr + 627 RX_BUF_OFFSET), 628 (int)(p_rxdesc_curr->byte_cnt - 629 RX_BUF_OFFSET)); 630 } 631 /* 632 * free these descriptors and point next in the ring 633 */ 634 p_rxdesc_curr->cmd_sts = 635 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; 636 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; 637 p_rxdesc_curr->byte_cnt = 0; 638 639 rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr; 640 writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr); 641 642 return 0; 643 } 644 645 #if defined(CONFIG_PHYLIB) 646 int mvgbe_phylib_init(struct eth_device *dev, int phyid) 647 { 648 struct mii_dev *bus; 649 struct phy_device *phydev; 650 int ret; 651 652 bus = mdio_alloc(); 653 if (!bus) { 654 printf("mdio_alloc failed\n"); 655 return -ENOMEM; 656 } 657 bus->read = smi_reg_read; 658 bus->write = smi_reg_write; 659 strcpy(bus->name, dev->name); 660 661 ret = mdio_register(bus); 662 if (ret) { 663 printf("mdio_register failed\n"); 664 free(bus); 665 return -ENOMEM; 666 } 667 668 /* Set phy address of the port */ 669 smi_reg_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid); 670 671 phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII); 672 if (!phydev) { 673 printf("phy_connect failed\n"); 674 return -ENODEV; 675 } 676 677 phy_config(phydev); 678 phy_startup(phydev); 679 680 return 0; 681 } 682 #endif 683 684 int mvgbe_initialize(bd_t *bis) 685 { 686 struct mvgbe_device *dmvgbe; 687 struct eth_device *dev; 688 int devnum; 689 u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS; 690 691 for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) { 692 /*skip if port is configured not to use */ 693 if (used_ports[devnum] == 0) 694 continue; 695 696 dmvgbe = malloc(sizeof(struct mvgbe_device)); 697 698 if (!dmvgbe) 699 goto error1; 700 701 memset(dmvgbe, 0, sizeof(struct mvgbe_device)); 702 703 dmvgbe->p_rxdesc = 704 (struct mvgbe_rxdesc *)memalign(PKTALIGN, 705 MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1); 706 707 if (!dmvgbe->p_rxdesc) 708 goto error2; 709 710 dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, 711 RINGSZ*PKTSIZE_ALIGN + 1); 712 713 if (!dmvgbe->p_rxbuf) 714 goto error3; 715 716 dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); 717 718 if (!dmvgbe->p_aligned_txbuf) 719 goto error4; 720 721 dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign( 722 PKTALIGN, sizeof(struct mvgbe_txdesc) + 1); 723 724 if (!dmvgbe->p_txdesc) { 725 free(dmvgbe->p_aligned_txbuf); 726 error4: 727 free(dmvgbe->p_rxbuf); 728 error3: 729 free(dmvgbe->p_rxdesc); 730 error2: 731 free(dmvgbe); 732 error1: 733 printf("Err.. %s Failed to allocate memory\n", 734 __func__); 735 return -1; 736 } 737 738 dev = &dmvgbe->dev; 739 740 /* must be less than sizeof(dev->name) */ 741 sprintf(dev->name, "egiga%d", devnum); 742 743 switch (devnum) { 744 case 0: 745 dmvgbe->regs = (void *)MVGBE0_BASE; 746 break; 747 #if defined(MVGBE1_BASE) 748 case 1: 749 dmvgbe->regs = (void *)MVGBE1_BASE; 750 break; 751 #endif 752 default: /* this should never happen */ 753 printf("Err..(%s) Invalid device number %d\n", 754 __func__, devnum); 755 return -1; 756 } 757 758 dev->init = (void *)mvgbe_init; 759 dev->halt = (void *)mvgbe_halt; 760 dev->send = (void *)mvgbe_send; 761 dev->recv = (void *)mvgbe_recv; 762 dev->write_hwaddr = (void *)mvgbe_write_hwaddr; 763 764 eth_register(dev); 765 766 #if defined(CONFIG_PHYLIB) 767 mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum); 768 #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 769 int retval; 770 struct mii_dev *mdiodev = mdio_alloc(); 771 if (!mdiodev) 772 return -ENOMEM; 773 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); 774 mdiodev->read = smi_reg_read; 775 mdiodev->write = smi_reg_write; 776 777 retval = mdio_register(mdiodev); 778 if (retval < 0) 779 return retval; 780 /* Set phy address of the port */ 781 miiphy_write(dev->name, MV_PHY_ADR_REQUEST, 782 MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); 783 #endif 784 } 785 return 0; 786 } 787