1 /* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * (C) Copyright 2003 7 * Ingo Assmus <ingo.assmus@keymile.com> 8 * 9 * based on - Driver for MV64360X ethernet ports 10 * Copyright (C) 2002 rabeeh@galileo.co.il 11 * 12 * SPDX-License-Identifier: GPL-2.0+ 13 */ 14 15 #include <common.h> 16 #include <net.h> 17 #include <malloc.h> 18 #include <miiphy.h> 19 #include <asm/io.h> 20 #include <asm/errno.h> 21 #include <asm/types.h> 22 #include <asm/system.h> 23 #include <asm/byteorder.h> 24 #include <asm/arch/cpu.h> 25 26 #if defined(CONFIG_KIRKWOOD) 27 #include <asm/arch/soc.h> 28 #elif defined(CONFIG_ORION5X) 29 #include <asm/arch/orion5x.h> 30 #elif defined(CONFIG_DOVE) 31 #include <asm/arch/dove.h> 32 #endif 33 34 #include "mvgbe.h" 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 #ifndef CONFIG_MVGBE_PORTS 39 # define CONFIG_MVGBE_PORTS {0, 0} 40 #endif 41 42 #define MV_PHY_ADR_REQUEST 0xee 43 #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi) 44 45 #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 46 /* 47 * smi_reg_read - miiphy_read callback function. 48 * 49 * Returns 16bit phy register value, or 0xffff on error 50 */ 51 static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad, 52 int reg_ofs) 53 { 54 u16 data = 0; 55 struct eth_device *dev = eth_get_dev_by_name(bus->name); 56 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 57 struct mvgbe_registers *regs = dmvgbe->regs; 58 u32 smi_reg; 59 u32 timeout; 60 61 /* Phyadr read request */ 62 if (phy_adr == MV_PHY_ADR_REQUEST && 63 reg_ofs == MV_PHY_ADR_REQUEST) { 64 /* */ 65 data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK); 66 return data; 67 } 68 /* check parameters */ 69 if (phy_adr > PHYADR_MASK) { 70 printf("Err..(%s) Invalid PHY address %d\n", 71 __func__, phy_adr); 72 return -EFAULT; 73 } 74 if (reg_ofs > PHYREG_MASK) { 75 printf("Err..(%s) Invalid register offset %d\n", 76 __func__, reg_ofs); 77 return -EFAULT; 78 } 79 80 timeout = MVGBE_PHY_SMI_TIMEOUT; 81 /* wait till the SMI is not busy */ 82 do { 83 /* read smi register */ 84 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); 85 if (timeout-- == 0) { 86 printf("Err..(%s) SMI busy timeout\n", __func__); 87 return -EFAULT; 88 } 89 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); 90 91 /* fill the phy address and regiser offset and read opcode */ 92 smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) 93 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS) 94 | MVGBE_PHY_SMI_OPCODE_READ; 95 96 /* write the smi register */ 97 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); 98 99 /*wait till read value is ready */ 100 timeout = MVGBE_PHY_SMI_TIMEOUT; 101 102 do { 103 /* read smi register */ 104 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); 105 if (timeout-- == 0) { 106 printf("Err..(%s) SMI read ready timeout\n", 107 __func__); 108 return -EFAULT; 109 } 110 } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK)); 111 112 /* Wait for the data to update in the SMI register */ 113 for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++) 114 ; 115 116 data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK); 117 118 debug("%s:(adr %d, off %d) value= %04x\n", __func__, phy_adr, reg_ofs, 119 data); 120 121 return data; 122 } 123 124 /* 125 * smi_reg_write - imiiphy_write callback function. 126 * 127 * Returns 0 if write succeed, -EINVAL on bad parameters 128 * -ETIME on timeout 129 */ 130 static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad, 131 int reg_ofs, u16 data) 132 { 133 struct eth_device *dev = eth_get_dev_by_name(bus->name); 134 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 135 struct mvgbe_registers *regs = dmvgbe->regs; 136 u32 smi_reg; 137 u32 timeout; 138 139 /* Phyadr write request*/ 140 if (phy_adr == MV_PHY_ADR_REQUEST && 141 reg_ofs == MV_PHY_ADR_REQUEST) { 142 MVGBE_REG_WR(regs->phyadr, data); 143 return 0; 144 } 145 146 /* check parameters */ 147 if (phy_adr > PHYADR_MASK) { 148 printf("Err..(%s) Invalid phy address\n", __func__); 149 return -EINVAL; 150 } 151 if (reg_ofs > PHYREG_MASK) { 152 printf("Err..(%s) Invalid register offset\n", __func__); 153 return -EINVAL; 154 } 155 156 /* wait till the SMI is not busy */ 157 timeout = MVGBE_PHY_SMI_TIMEOUT; 158 do { 159 /* read smi register */ 160 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG); 161 if (timeout-- == 0) { 162 printf("Err..(%s) SMI busy timeout\n", __func__); 163 return -ETIME; 164 } 165 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK); 166 167 /* fill the phy addr and reg offset and write opcode and data */ 168 smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS); 169 smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS) 170 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS); 171 smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ; 172 173 /* write the smi register */ 174 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg); 175 176 return 0; 177 } 178 #endif 179 180 #if defined(CONFIG_PHYLIB) 181 int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, 182 int reg_addr) 183 { 184 u16 data; 185 int ret; 186 ret = smi_reg_read(bus->name, phy_addr, reg_addr, &data); 187 if (ret) 188 return ret; 189 return data; 190 } 191 192 int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, 193 int reg_addr, u16 data) 194 { 195 return smi_reg_write(bus->name, phy_addr, reg_addr, data); 196 } 197 #endif 198 199 /* Stop and checks all queues */ 200 static void stop_queue(u32 * qreg) 201 { 202 u32 reg_data; 203 204 reg_data = readl(qreg); 205 206 if (reg_data & 0xFF) { 207 /* Issue stop command for active channels only */ 208 writel((reg_data << 8), qreg); 209 210 /* Wait for all queue activity to terminate. */ 211 do { 212 /* 213 * Check port cause register that all queues 214 * are stopped 215 */ 216 reg_data = readl(qreg); 217 } 218 while (reg_data & 0xFF); 219 } 220 } 221 222 /* 223 * set_access_control - Config address decode parameters for Ethernet unit 224 * 225 * This function configures the address decode parameters for the Gigabit 226 * Ethernet Controller according the given parameters struct. 227 * 228 * @regs Register struct pointer. 229 * @param Address decode parameter struct. 230 */ 231 static void set_access_control(struct mvgbe_registers *regs, 232 struct mvgbe_winparam *param) 233 { 234 u32 access_prot_reg; 235 236 /* Set access control register */ 237 access_prot_reg = MVGBE_REG_RD(regs->epap); 238 /* clear window permission */ 239 access_prot_reg &= (~(3 << (param->win * 2))); 240 access_prot_reg |= (param->access_ctrl << (param->win * 2)); 241 MVGBE_REG_WR(regs->epap, access_prot_reg); 242 243 /* Set window Size reg (SR) */ 244 MVGBE_REG_WR(regs->barsz[param->win].size, 245 (((param->size / 0x10000) - 1) << 16)); 246 247 /* Set window Base address reg (BA) */ 248 MVGBE_REG_WR(regs->barsz[param->win].bar, 249 (param->target | param->attrib | param->base_addr)); 250 /* High address remap reg (HARR) */ 251 if (param->win < 4) 252 MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr); 253 254 /* Base address enable reg (BARER) */ 255 if (param->enable == 1) 256 MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win)); 257 else 258 MVGBE_REG_BITS_SET(regs->bare, (1 << param->win)); 259 } 260 261 static void set_dram_access(struct mvgbe_registers *regs) 262 { 263 struct mvgbe_winparam win_param; 264 int i; 265 266 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { 267 /* Set access parameters for DRAM bank i */ 268 win_param.win = i; /* Use Ethernet window i */ 269 /* Window target - DDR */ 270 win_param.target = MVGBE_TARGET_DRAM; 271 /* Enable full access */ 272 win_param.access_ctrl = EWIN_ACCESS_FULL; 273 win_param.high_addr = 0; 274 /* Get bank base and size */ 275 win_param.base_addr = gd->bd->bi_dram[i].start; 276 win_param.size = gd->bd->bi_dram[i].size; 277 if (win_param.size == 0) 278 win_param.enable = 0; 279 else 280 win_param.enable = 1; /* Enable the access */ 281 282 /* Enable DRAM bank */ 283 switch (i) { 284 case 0: 285 win_param.attrib = EBAR_DRAM_CS0; 286 break; 287 case 1: 288 win_param.attrib = EBAR_DRAM_CS1; 289 break; 290 case 2: 291 win_param.attrib = EBAR_DRAM_CS2; 292 break; 293 case 3: 294 win_param.attrib = EBAR_DRAM_CS3; 295 break; 296 default: 297 /* invalid bank, disable access */ 298 win_param.enable = 0; 299 win_param.attrib = 0; 300 break; 301 } 302 /* Set the access control for address window(EPAPR) RD/WR */ 303 set_access_control(regs, &win_param); 304 } 305 } 306 307 /* 308 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables 309 * 310 * Go through all the DA filter tables (Unicast, Special Multicast & Other 311 * Multicast) and set each entry to 0. 312 */ 313 static void port_init_mac_tables(struct mvgbe_registers *regs) 314 { 315 int table_index; 316 317 /* Clear DA filter unicast table (Ex_dFUT) */ 318 for (table_index = 0; table_index < 4; ++table_index) 319 MVGBE_REG_WR(regs->dfut[table_index], 0); 320 321 for (table_index = 0; table_index < 64; ++table_index) { 322 /* Clear DA filter special multicast table (Ex_dFSMT) */ 323 MVGBE_REG_WR(regs->dfsmt[table_index], 0); 324 /* Clear DA filter other multicast table (Ex_dFOMT) */ 325 MVGBE_REG_WR(regs->dfomt[table_index], 0); 326 } 327 } 328 329 /* 330 * port_uc_addr - This function Set the port unicast address table 331 * 332 * This function locates the proper entry in the Unicast table for the 333 * specified MAC nibble and sets its properties according to function 334 * parameters. 335 * This function add/removes MAC addresses from the port unicast address 336 * table. 337 * 338 * @uc_nibble Unicast MAC Address last nibble. 339 * @option 0 = Add, 1 = remove address. 340 * 341 * RETURN: 1 if output succeeded. 0 if option parameter is invalid. 342 */ 343 static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble, 344 int option) 345 { 346 u32 unicast_reg; 347 u32 tbl_offset; 348 u32 reg_offset; 349 350 /* Locate the Unicast table entry */ 351 uc_nibble = (0xf & uc_nibble); 352 /* Register offset from unicast table base */ 353 tbl_offset = (uc_nibble / 4); 354 /* Entry offset within the above register */ 355 reg_offset = uc_nibble % 4; 356 357 switch (option) { 358 case REJECT_MAC_ADDR: 359 /* 360 * Clear accepts frame bit at specified unicast 361 * DA table entry 362 */ 363 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); 364 unicast_reg &= (0xFF << (8 * reg_offset)); 365 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); 366 break; 367 case ACCEPT_MAC_ADDR: 368 /* Set accepts frame bit at unicast DA filter table entry */ 369 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]); 370 unicast_reg &= (0xFF << (8 * reg_offset)); 371 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset)); 372 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg); 373 break; 374 default: 375 return 0; 376 } 377 return 1; 378 } 379 380 /* 381 * port_uc_addr_set - This function Set the port Unicast address. 382 */ 383 static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr) 384 { 385 u32 mac_h; 386 u32 mac_l; 387 388 mac_l = (p_addr[4] << 8) | (p_addr[5]); 389 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) | 390 (p_addr[3] << 0); 391 392 MVGBE_REG_WR(regs->macal, mac_l); 393 MVGBE_REG_WR(regs->macah, mac_h); 394 395 /* Accept frames of this address */ 396 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR); 397 } 398 399 /* 400 * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. 401 */ 402 static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe) 403 { 404 struct mvgbe_rxdesc *p_rx_desc; 405 int i; 406 407 /* initialize the Rx descriptors ring */ 408 p_rx_desc = dmvgbe->p_rxdesc; 409 for (i = 0; i < RINGSZ; i++) { 410 p_rx_desc->cmd_sts = 411 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; 412 p_rx_desc->buf_size = PKTSIZE_ALIGN; 413 p_rx_desc->byte_cnt = 0; 414 p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN; 415 if (i == (RINGSZ - 1)) 416 p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc; 417 else { 418 p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *) 419 ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE); 420 p_rx_desc = p_rx_desc->nxtdesc_p; 421 } 422 } 423 dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc; 424 } 425 426 static int mvgbe_init(struct eth_device *dev) 427 { 428 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 429 struct mvgbe_registers *regs = dmvgbe->regs; 430 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ 431 !defined(CONFIG_PHYLIB) && \ 432 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) 433 int i; 434 #endif 435 /* setup RX rings */ 436 mvgbe_init_rx_desc_ring(dmvgbe); 437 438 /* Clear the ethernet port interrupts */ 439 MVGBE_REG_WR(regs->ic, 0); 440 MVGBE_REG_WR(regs->ice, 0); 441 /* Unmask RX buffer and TX end interrupt */ 442 MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL); 443 /* Unmask phy and link status changes interrupts */ 444 MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT); 445 446 set_dram_access(regs); 447 port_init_mac_tables(regs); 448 port_uc_addr_set(regs, dmvgbe->dev.enetaddr); 449 450 /* Assign port configuration and command. */ 451 MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL); 452 MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE); 453 MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE); 454 455 /* Assign port SDMA configuration */ 456 MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE); 457 MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL); 458 MVGBE_REG_WR(regs->tqx[0].tqxtbc, 459 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL); 460 /* Turn off the port/RXUQ bandwidth limitation */ 461 MVGBE_REG_WR(regs->pmtu, 0); 462 463 /* Set maximum receive buffer to 9700 bytes */ 464 MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE 465 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK)); 466 467 /* Enable port initially */ 468 MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN); 469 470 /* 471 * Set ethernet MTU for leaky bucket mechanism to 0 - this will 472 * disable the leaky bucket mechanism . 473 */ 474 MVGBE_REG_WR(regs->pmtu, 0); 475 476 /* Assignment of Rx CRDB of given RXUQ */ 477 MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr); 478 /* ensure previous write is done before enabling Rx DMA */ 479 isb(); 480 /* Enable port Rx. */ 481 MVGBE_REG_WR(regs->rqc, (1 << RXUQ)); 482 483 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \ 484 !defined(CONFIG_PHYLIB) && \ 485 defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN) 486 /* Wait up to 5s for the link status */ 487 for (i = 0; i < 5; i++) { 488 u16 phyadr; 489 490 miiphy_read(dev->name, MV_PHY_ADR_REQUEST, 491 MV_PHY_ADR_REQUEST, &phyadr); 492 /* Return if we get link up */ 493 if (miiphy_link(dev->name, phyadr)) 494 return 0; 495 udelay(1000000); 496 } 497 498 printf("No link on %s\n", dev->name); 499 return -1; 500 #endif 501 return 0; 502 } 503 504 static int mvgbe_halt(struct eth_device *dev) 505 { 506 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 507 struct mvgbe_registers *regs = dmvgbe->regs; 508 509 /* Disable all gigE address decoder */ 510 MVGBE_REG_WR(regs->bare, 0x3f); 511 512 stop_queue(®s->tqc); 513 stop_queue(®s->rqc); 514 515 /* Disable port */ 516 MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN); 517 /* Set port is not reset */ 518 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4); 519 #ifdef CONFIG_SYS_MII_MODE 520 /* Set MMI interface up */ 521 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3); 522 #endif 523 /* Disable & mask ethernet port interrupts */ 524 MVGBE_REG_WR(regs->ic, 0); 525 MVGBE_REG_WR(regs->ice, 0); 526 MVGBE_REG_WR(regs->pim, 0); 527 MVGBE_REG_WR(regs->peim, 0); 528 529 return 0; 530 } 531 532 static int mvgbe_write_hwaddr(struct eth_device *dev) 533 { 534 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 535 struct mvgbe_registers *regs = dmvgbe->regs; 536 537 /* Programs net device MAC address after initialization */ 538 port_uc_addr_set(regs, dmvgbe->dev.enetaddr); 539 return 0; 540 } 541 542 static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize) 543 { 544 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 545 struct mvgbe_registers *regs = dmvgbe->regs; 546 struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc; 547 void *p = (void *)dataptr; 548 u32 cmd_sts; 549 u32 txuq0_reg_addr; 550 551 /* Copy buffer if it's misaligned */ 552 if ((u32) dataptr & 0x07) { 553 if (datasize > PKTSIZE_ALIGN) { 554 printf("Non-aligned data too large (%d)\n", 555 datasize); 556 return -1; 557 } 558 559 memcpy(dmvgbe->p_aligned_txbuf, p, datasize); 560 p = dmvgbe->p_aligned_txbuf; 561 } 562 563 p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC; 564 p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC; 565 p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA; 566 p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT; 567 p_txdesc->buf_ptr = (u8 *) p; 568 p_txdesc->byte_cnt = datasize; 569 570 /* Set this tc desc as zeroth TXUQ */ 571 txuq0_reg_addr = (u32)®s->tcqdp[TXUQ]; 572 writel((u32) p_txdesc, txuq0_reg_addr); 573 574 /* ensure tx desc writes above are performed before we start Tx DMA */ 575 isb(); 576 577 /* Apply send command using zeroth TXUQ */ 578 MVGBE_REG_WR(regs->tqc, (1 << TXUQ)); 579 580 /* 581 * wait for packet xmit completion 582 */ 583 cmd_sts = readl(&p_txdesc->cmd_sts); 584 while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) { 585 /* return fail if error is detected */ 586 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) == 587 (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) && 588 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) { 589 printf("Err..(%s) in xmit packet\n", __func__); 590 return -1; 591 } 592 cmd_sts = readl(&p_txdesc->cmd_sts); 593 }; 594 return 0; 595 } 596 597 static int mvgbe_recv(struct eth_device *dev) 598 { 599 struct mvgbe_device *dmvgbe = to_mvgbe(dev); 600 struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr; 601 u32 cmd_sts; 602 u32 timeout = 0; 603 u32 rxdesc_curr_addr; 604 605 /* wait untill rx packet available or timeout */ 606 do { 607 if (timeout < MVGBE_PHY_SMI_TIMEOUT) 608 timeout++; 609 else { 610 debug("%s time out...\n", __func__); 611 return -1; 612 } 613 } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA); 614 615 if (p_rxdesc_curr->byte_cnt != 0) { 616 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n", 617 __func__, (u32) p_rxdesc_curr->byte_cnt, 618 (u32) p_rxdesc_curr->buf_ptr, 619 (u32) p_rxdesc_curr->cmd_sts); 620 } 621 622 /* 623 * In case received a packet without first/last bits on 624 * OR the error summary bit is on, 625 * the packets needs to be dropeed. 626 */ 627 cmd_sts = readl(&p_rxdesc_curr->cmd_sts); 628 629 if ((cmd_sts & 630 (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) 631 != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) { 632 633 printf("Err..(%s) Dropping packet spread on" 634 " multiple descriptors\n", __func__); 635 636 } else if (cmd_sts & MVGBE_ERROR_SUMMARY) { 637 638 printf("Err..(%s) Dropping packet with errors\n", 639 __func__); 640 641 } else { 642 /* !!! call higher layer processing */ 643 debug("%s: Sending Received packet to" 644 " upper layer (net_process_received_packet)\n", 645 __func__); 646 647 /* let the upper layer handle the packet */ 648 net_process_received_packet((p_rxdesc_curr->buf_ptr + 649 RX_BUF_OFFSET), 650 (int)(p_rxdesc_curr->byte_cnt - 651 RX_BUF_OFFSET)); 652 } 653 /* 654 * free these descriptors and point next in the ring 655 */ 656 p_rxdesc_curr->cmd_sts = 657 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT; 658 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN; 659 p_rxdesc_curr->byte_cnt = 0; 660 661 rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr; 662 writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr); 663 664 return 0; 665 } 666 667 #if defined(CONFIG_PHYLIB) 668 int mvgbe_phylib_init(struct eth_device *dev, int phyid) 669 { 670 struct mii_dev *bus; 671 struct phy_device *phydev; 672 int ret; 673 674 bus = mdio_alloc(); 675 if (!bus) { 676 printf("mdio_alloc failed\n"); 677 return -ENOMEM; 678 } 679 bus->read = mvgbe_phy_read; 680 bus->write = mvgbe_phy_write; 681 strcpy(bus->name, dev->name); 682 683 ret = mdio_register(bus); 684 if (ret) { 685 printf("mdio_register failed\n"); 686 free(bus); 687 return -ENOMEM; 688 } 689 690 /* Set phy address of the port */ 691 mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid); 692 693 phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII); 694 if (!phydev) { 695 printf("phy_connect failed\n"); 696 return -ENODEV; 697 } 698 699 phy_config(phydev); 700 phy_startup(phydev); 701 702 return 0; 703 } 704 #endif 705 706 int mvgbe_initialize(bd_t *bis) 707 { 708 struct mvgbe_device *dmvgbe; 709 struct eth_device *dev; 710 int devnum; 711 u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS; 712 713 for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) { 714 /*skip if port is configured not to use */ 715 if (used_ports[devnum] == 0) 716 continue; 717 718 dmvgbe = malloc(sizeof(struct mvgbe_device)); 719 720 if (!dmvgbe) 721 goto error1; 722 723 memset(dmvgbe, 0, sizeof(struct mvgbe_device)); 724 725 dmvgbe->p_rxdesc = 726 (struct mvgbe_rxdesc *)memalign(PKTALIGN, 727 MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1); 728 729 if (!dmvgbe->p_rxdesc) 730 goto error2; 731 732 dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, 733 RINGSZ*PKTSIZE_ALIGN + 1); 734 735 if (!dmvgbe->p_rxbuf) 736 goto error3; 737 738 dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN); 739 740 if (!dmvgbe->p_aligned_txbuf) 741 goto error4; 742 743 dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign( 744 PKTALIGN, sizeof(struct mvgbe_txdesc) + 1); 745 746 if (!dmvgbe->p_txdesc) { 747 free(dmvgbe->p_aligned_txbuf); 748 error4: 749 free(dmvgbe->p_rxbuf); 750 error3: 751 free(dmvgbe->p_rxdesc); 752 error2: 753 free(dmvgbe); 754 error1: 755 printf("Err.. %s Failed to allocate memory\n", 756 __func__); 757 return -1; 758 } 759 760 dev = &dmvgbe->dev; 761 762 /* must be less than sizeof(dev->name) */ 763 sprintf(dev->name, "egiga%d", devnum); 764 765 switch (devnum) { 766 case 0: 767 dmvgbe->regs = (void *)MVGBE0_BASE; 768 break; 769 #if defined(MVGBE1_BASE) 770 case 1: 771 dmvgbe->regs = (void *)MVGBE1_BASE; 772 break; 773 #endif 774 default: /* this should never happen */ 775 printf("Err..(%s) Invalid device number %d\n", 776 __func__, devnum); 777 return -1; 778 } 779 780 dev->init = (void *)mvgbe_init; 781 dev->halt = (void *)mvgbe_halt; 782 dev->send = (void *)mvgbe_send; 783 dev->recv = (void *)mvgbe_recv; 784 dev->write_hwaddr = (void *)mvgbe_write_hwaddr; 785 786 eth_register(dev); 787 788 #if defined(CONFIG_PHYLIB) 789 mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum); 790 #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 791 int retval; 792 struct mii_dev *mdiodev = mdio_alloc(); 793 if (!mdiodev) 794 return -ENOMEM; 795 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); 796 mdiodev->read = smi_reg_read; 797 mdiodev->write = smi_reg_write; 798 799 retval = mdio_register(mdiodev); 800 if (retval < 0) 801 return retval; 802 /* Set phy address of the port */ 803 miiphy_write(dev->name, MV_PHY_ADR_REQUEST, 804 MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); 805 #endif 806 } 807 return 0; 808 } 809