1 /* 2 * (C) Copyright 2000 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <command.h> 10 #include <malloc.h> 11 #include <net.h> 12 #include <netdev.h> 13 #include <asm/cpm_8xx.h> 14 #include <asm/io.h> 15 16 #include <phy.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 /* define WANT_MII when MII support is required */ 21 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_FEC1_PHY) || defined(CONFIG_FEC2_PHY) 22 #define WANT_MII 23 #else 24 #undef WANT_MII 25 #endif 26 27 #if defined(WANT_MII) 28 #include <miiphy.h> 29 30 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) 31 #error "CONFIG_MII has to be defined!" 32 #endif 33 34 #endif 35 36 #if defined(CONFIG_RMII) && !defined(WANT_MII) 37 #error RMII support is unusable without a working PHY. 38 #endif 39 40 #ifdef CONFIG_SYS_DISCOVER_PHY 41 static int mii_discover_phy(struct eth_device *dev); 42 #endif 43 44 int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg); 45 int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, 46 u16 value); 47 48 static struct ether_fcc_info_s 49 { 50 int ether_index; 51 int fecp_offset; 52 int phy_addr; 53 int actual_phy_addr; 54 int initialized; 55 } 56 ether_fcc_info[] = { 57 #if defined(CONFIG_ETHER_ON_FEC1) 58 { 59 0, 60 offsetof(immap_t, im_cpm.cp_fec1), 61 CONFIG_FEC1_PHY, 62 -1, 63 0, 64 65 }, 66 #endif 67 #if defined(CONFIG_ETHER_ON_FEC2) 68 { 69 1, 70 offsetof(immap_t, im_cpm.cp_fec2), 71 CONFIG_FEC2_PHY, 72 -1, 73 0, 74 }, 75 #endif 76 }; 77 78 /* Ethernet Transmit and Receive Buffers */ 79 #define DBUF_LENGTH 1520 80 81 #define TX_BUF_CNT 2 82 83 #define TOUT_LOOP 100 84 85 #define PKT_MAXBUF_SIZE 1518 86 #define PKT_MINBUF_SIZE 64 87 #define PKT_MAXBLR_SIZE 1520 88 89 #ifdef __GNUC__ 90 static char txbuf[DBUF_LENGTH] __aligned(8); 91 #else 92 #error txbuf must be aligned. 93 #endif 94 95 static uint rxIdx; /* index of the current RX buffer */ 96 static uint txIdx; /* index of the current TX buffer */ 97 98 /* 99 * FEC Ethernet Tx and Rx buffer descriptors allocated at the 100 * immr->udata_bd address on Dual-Port RAM 101 * Provide for Double Buffering 102 */ 103 104 struct common_buf_desc { 105 cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ 106 cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ 107 }; 108 109 static struct common_buf_desc __iomem *rtx; 110 111 static int fec_send(struct eth_device *dev, void *packet, int length); 112 static int fec_recv(struct eth_device *dev); 113 static int fec_init(struct eth_device *dev, bd_t *bd); 114 static void fec_halt(struct eth_device *dev); 115 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 116 static void __mii_init(void); 117 #endif 118 119 int fec_initialize(bd_t *bis) 120 { 121 struct eth_device *dev; 122 struct ether_fcc_info_s *efis; 123 int i; 124 125 for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) { 126 dev = malloc(sizeof(*dev)); 127 if (dev == NULL) 128 hang(); 129 130 memset(dev, 0, sizeof(*dev)); 131 132 /* for FEC1 make sure that the name of the interface is the same 133 as the old one for compatibility reasons */ 134 if (i == 0) 135 strcpy(dev->name, "FEC"); 136 else 137 sprintf(dev->name, "FEC%d", 138 ether_fcc_info[i].ether_index + 1); 139 140 efis = ðer_fcc_info[i]; 141 142 /* 143 * reset actual phy addr 144 */ 145 efis->actual_phy_addr = -1; 146 147 dev->priv = efis; 148 dev->init = fec_init; 149 dev->halt = fec_halt; 150 dev->send = fec_send; 151 dev->recv = fec_recv; 152 153 eth_register(dev); 154 155 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 156 int retval; 157 struct mii_dev *mdiodev = mdio_alloc(); 158 if (!mdiodev) 159 return -ENOMEM; 160 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); 161 mdiodev->read = fec8xx_miiphy_read; 162 mdiodev->write = fec8xx_miiphy_write; 163 164 retval = mdio_register(mdiodev); 165 if (retval < 0) 166 return retval; 167 #endif 168 } 169 return 1; 170 } 171 172 static int fec_send(struct eth_device *dev, void *packet, int length) 173 { 174 int j, rc; 175 struct ether_fcc_info_s *efis = dev->priv; 176 fec_t __iomem *fecp = 177 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset); 178 179 /* section 16.9.23.3 180 * Wait for ready 181 */ 182 j = 0; 183 while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) && 184 (j < TOUT_LOOP)) { 185 udelay(1); 186 j++; 187 } 188 if (j >= TOUT_LOOP) 189 printf("TX not ready\n"); 190 191 out_be32(&rtx->txbd[txIdx].cbd_bufaddr, (uint)packet); 192 out_be16(&rtx->txbd[txIdx].cbd_datlen, length); 193 setbits_be16(&rtx->txbd[txIdx].cbd_sc, 194 BD_ENET_TX_READY | BD_ENET_TX_LAST); 195 196 /* Activate transmit Buffer Descriptor polling */ 197 /* Descriptor polling active */ 198 out_be32(&fecp->fec_x_des_active, 0x01000000); 199 200 j = 0; 201 while ((in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_READY) && 202 (j < TOUT_LOOP)) { 203 udelay(1); 204 j++; 205 } 206 if (j >= TOUT_LOOP) 207 printf("TX timeout\n"); 208 209 /* return only status bits */; 210 rc = in_be16(&rtx->txbd[txIdx].cbd_sc) & BD_ENET_TX_STATS; 211 212 txIdx = (txIdx + 1) % TX_BUF_CNT; 213 214 return rc; 215 } 216 217 static int fec_recv(struct eth_device *dev) 218 { 219 struct ether_fcc_info_s *efis = dev->priv; 220 fec_t __iomem *fecp = 221 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset); 222 int length; 223 224 for (;;) { 225 /* section 16.9.23.2 */ 226 if (in_be16(&rtx->rxbd[rxIdx].cbd_sc) & BD_ENET_RX_EMPTY) { 227 length = -1; 228 break; /* nothing received - leave for() loop */ 229 } 230 231 length = in_be16(&rtx->rxbd[rxIdx].cbd_datlen); 232 233 if (!(in_be16(&rtx->rxbd[rxIdx].cbd_sc) & 0x003f)) { 234 uchar *rx = net_rx_packets[rxIdx]; 235 236 length -= 4; 237 238 #if defined(CONFIG_CMD_CDP) 239 if ((rx[0] & 1) != 0 && 240 memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 && 241 !is_cdp_packet((uchar *)rx)) 242 rx = NULL; 243 #endif 244 /* 245 * Pass the packet up to the protocol layers. 246 */ 247 if (rx != NULL) 248 net_process_received_packet(rx, length); 249 } 250 251 /* Give the buffer back to the FEC. */ 252 out_be16(&rtx->rxbd[rxIdx].cbd_datlen, 0); 253 254 /* wrap around buffer index when necessary */ 255 if ((rxIdx + 1) >= PKTBUFSRX) { 256 out_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, 257 BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); 258 rxIdx = 0; 259 } else { 260 out_be16(&rtx->rxbd[rxIdx].cbd_sc, BD_ENET_RX_EMPTY); 261 rxIdx++; 262 } 263 264 /* Try to fill Buffer Descriptors */ 265 /* Descriptor polling active */ 266 out_be32(&fecp->fec_r_des_active, 0x01000000); 267 } 268 269 return length; 270 } 271 272 /************************************************************** 273 * 274 * FEC Ethernet Initialization Routine 275 * 276 *************************************************************/ 277 278 #define FEC_ECNTRL_PINMUX 0x00000004 279 #define FEC_ECNTRL_ETHER_EN 0x00000002 280 #define FEC_ECNTRL_RESET 0x00000001 281 282 #define FEC_RCNTRL_BC_REJ 0x00000010 283 #define FEC_RCNTRL_PROM 0x00000008 284 #define FEC_RCNTRL_MII_MODE 0x00000004 285 #define FEC_RCNTRL_DRT 0x00000002 286 #define FEC_RCNTRL_LOOP 0x00000001 287 288 #define FEC_TCNTRL_FDEN 0x00000004 289 #define FEC_TCNTRL_HBC 0x00000002 290 #define FEC_TCNTRL_GTS 0x00000001 291 292 #define FEC_RESET_DELAY 50 293 294 #if defined(CONFIG_RMII) 295 296 static inline void fec_10Mbps(struct eth_device *dev) 297 { 298 struct ether_fcc_info_s *efis = dev->priv; 299 int fecidx = efis->ether_index; 300 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; 301 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; 302 303 if ((unsigned int)fecidx >= 2) 304 hang(); 305 306 setbits_be32(&immr->im_cpm.cp_cptr, mask); 307 } 308 309 static inline void fec_100Mbps(struct eth_device *dev) 310 { 311 struct ether_fcc_info_s *efis = dev->priv; 312 int fecidx = efis->ether_index; 313 uint mask = (fecidx == 0) ? 0x0000010 : 0x0000008; 314 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; 315 316 if ((unsigned int)fecidx >= 2) 317 hang(); 318 319 clrbits_be32(&immr->im_cpm.cp_cptr, mask); 320 } 321 322 #endif 323 324 static inline void fec_full_duplex(struct eth_device *dev) 325 { 326 struct ether_fcc_info_s *efis = dev->priv; 327 fec_t __iomem *fecp = 328 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset); 329 330 clrbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT); 331 setbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD enable */ 332 } 333 334 static inline void fec_half_duplex(struct eth_device *dev) 335 { 336 struct ether_fcc_info_s *efis = dev->priv; 337 fec_t __iomem *fecp = 338 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset); 339 340 setbits_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_DRT); 341 clrbits_be32(&fecp->fec_x_cntrl, FEC_TCNTRL_FDEN); /* FD disable */ 342 } 343 344 static void fec_pin_init(int fecidx) 345 { 346 bd_t *bd = gd->bd; 347 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; 348 349 /* 350 * Set MII speed to 2.5 MHz or slightly below. 351 * 352 * According to the MPC860T (Rev. D) Fast ethernet controller user 353 * manual (6.2.14), 354 * the MII management interface clock must be less than or equal 355 * to 2.5 MHz. 356 * This MDC frequency is equal to system clock / (2 * MII_SPEED). 357 * Then MII_SPEED = system_clock / 2 * 2,5 MHz. 358 * 359 * All MII configuration is done via FEC1 registers: 360 */ 361 out_be32(&immr->im_cpm.cp_fec1.fec_mii_speed, 362 ((bd->bi_intfreq + 4999999) / 5000000) << 1); 363 364 #if defined(CONFIG_MPC885) && defined(WANT_MII) 365 /* use MDC for MII */ 366 setbits_be16(&immr->im_ioport.iop_pdpar, 0x0080); 367 clrbits_be16(&immr->im_ioport.iop_pddir, 0x0080); 368 #endif 369 370 if (fecidx == 0) { 371 #if defined(CONFIG_ETHER_ON_FEC1) 372 373 #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */ 374 375 #if !defined(CONFIG_RMII) 376 377 setbits_be16(&immr->im_ioport.iop_papar, 0xf830); 378 setbits_be16(&immr->im_ioport.iop_padir, 0x0830); 379 clrbits_be16(&immr->im_ioport.iop_padir, 0xf000); 380 381 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00001001); 382 clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00001001); 383 384 setbits_be16(&immr->im_ioport.iop_pcpar, 0x000c); 385 clrbits_be16(&immr->im_ioport.iop_pcdir, 0x000c); 386 387 setbits_be32(&immr->im_cpm.cp_pepar, 0x00000003); 388 setbits_be32(&immr->im_cpm.cp_pedir, 0x00000003); 389 clrbits_be32(&immr->im_cpm.cp_peso, 0x00000003); 390 391 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000100); 392 393 #else 394 395 #if !defined(CONFIG_FEC1_PHY_NORXERR) 396 setbits_be16(&immr->im_ioport.iop_papar, 0x1000); 397 clrbits_be16(&immr->im_ioport.iop_padir, 0x1000); 398 #endif 399 setbits_be16(&immr->im_ioport.iop_papar, 0xe810); 400 setbits_be16(&immr->im_ioport.iop_padir, 0x0810); 401 clrbits_be16(&immr->im_ioport.iop_padir, 0xe000); 402 403 setbits_be32(&immr->im_cpm.cp_pbpar, 0x00000001); 404 clrbits_be32(&immr->im_cpm.cp_pbdir, 0x00000001); 405 406 setbits_be32(&immr->im_cpm.cp_cptr, 0x00000100); 407 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000050); 408 409 #endif /* !CONFIG_RMII */ 410 411 #else 412 /* 413 * Configure all of port D for MII. 414 */ 415 out_be16(&immr->im_ioport.iop_pdpar, 0x1fff); 416 out_be16(&immr->im_ioport.iop_pddir, 0x1fff); 417 418 #if defined(CONFIG_TARGET_MCR3000) 419 out_be16(&immr->im_ioport.iop_papar, 0xBBFF); 420 out_be16(&immr->im_ioport.iop_padir, 0x04F0); 421 out_be16(&immr->im_ioport.iop_paodr, 0x0000); 422 423 out_be32(&immr->im_cpm.cp_pbpar, 0x000133FF); 424 out_be32(&immr->im_cpm.cp_pbdir, 0x0003BF0F); 425 out_be16(&immr->im_cpm.cp_pbodr, 0x0000); 426 427 out_be16(&immr->im_ioport.iop_pcpar, 0x0400); 428 out_be16(&immr->im_ioport.iop_pcdir, 0x0080); 429 out_be16(&immr->im_ioport.iop_pcso , 0x0D53); 430 out_be16(&immr->im_ioport.iop_pcint, 0x0000); 431 432 out_be16(&immr->im_ioport.iop_pdpar, 0x03FE); 433 out_be16(&immr->im_ioport.iop_pddir, 0x1C09); 434 435 setbits_be32(&immr->im_ioport.utmode, 0x80); 436 #endif 437 #endif 438 439 #endif /* CONFIG_ETHER_ON_FEC1 */ 440 } else if (fecidx == 1) { 441 #if defined(CONFIG_ETHER_ON_FEC2) 442 443 #if defined(CONFIG_MPC885) /* MPC87x/88x have got 2 FECs and different pinout */ 444 445 #if !defined(CONFIG_RMII) 446 setbits_be32(&immr->im_cpm.cp_pepar, 0x0003fffc); 447 setbits_be32(&immr->im_cpm.cp_pedir, 0x0003fffc); 448 clrbits_be32(&immr->im_cpm.cp_peso, 0x000087fc); 449 setbits_be32(&immr->im_cpm.cp_peso, 0x00037800); 450 451 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000080); 452 #else 453 454 #if !defined(CONFIG_FEC2_PHY_NORXERR) 455 setbits_be32(&immr->im_cpm.cp_pepar, 0x00000010); 456 setbits_be32(&immr->im_cpm.cp_pedir, 0x00000010); 457 clrbits_be32(&immr->im_cpm.cp_peso, 0x00000010); 458 #endif 459 setbits_be32(&immr->im_cpm.cp_pepar, 0x00039620); 460 setbits_be32(&immr->im_cpm.cp_pedir, 0x00039620); 461 setbits_be32(&immr->im_cpm.cp_peso, 0x00031000); 462 clrbits_be32(&immr->im_cpm.cp_peso, 0x00008620); 463 464 setbits_be32(&immr->im_cpm.cp_cptr, 0x00000080); 465 clrbits_be32(&immr->im_cpm.cp_cptr, 0x00000028); 466 #endif /* CONFIG_RMII */ 467 468 #endif /* CONFIG_MPC885 */ 469 470 #endif /* CONFIG_ETHER_ON_FEC2 */ 471 } 472 } 473 474 static int fec_reset(fec_t __iomem *fecp) 475 { 476 int i; 477 478 /* Whack a reset. 479 * A delay is required between a reset of the FEC block and 480 * initialization of other FEC registers because the reset takes 481 * some time to complete. If you don't delay, subsequent writes 482 * to FEC registers might get killed by the reset routine which is 483 * still in progress. 484 */ 485 486 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET); 487 for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) && 488 (i < FEC_RESET_DELAY); ++i) 489 udelay(1); 490 491 if (i == FEC_RESET_DELAY) 492 return -1; 493 494 return 0; 495 } 496 497 static int fec_init(struct eth_device *dev, bd_t *bd) 498 { 499 struct ether_fcc_info_s *efis = dev->priv; 500 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; 501 fec_t __iomem *fecp = 502 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset); 503 int i; 504 505 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 506 /* the MII interface is connected to FEC1 507 * so for the miiphy_xxx function to work we must 508 * call mii_init since fec_halt messes the thing up 509 */ 510 if (efis->ether_index != 0) 511 __mii_init(); 512 #endif 513 514 if (fec_reset(fecp) < 0) 515 printf("FEC_RESET_DELAY timeout\n"); 516 517 /* We use strictly polling mode only 518 */ 519 out_be32(&fecp->fec_imask, 0); 520 521 /* Clear any pending interrupt 522 */ 523 out_be32(&fecp->fec_ievent, 0xffc0); 524 525 /* No need to set the IVEC register */ 526 527 /* Set station address 528 */ 529 #define ea dev->enetaddr 530 out_be32(&fecp->fec_addr_low, (ea[0] << 24) | (ea[1] << 16) | 531 (ea[2] << 8) | ea[3]); 532 out_be16(&fecp->fec_addr_high, (ea[4] << 8) | ea[5]); 533 #undef ea 534 535 #if defined(CONFIG_CMD_CDP) 536 /* 537 * Turn on multicast address hash table 538 */ 539 out_be32(&fecp->fec_hash_table_high, 0xffffffff); 540 out_be32(&fecp->fec_hash_table_low, 0xffffffff); 541 #else 542 /* Clear multicast address hash table 543 */ 544 out_be32(&fecp->fec_hash_table_high, 0); 545 out_be32(&fecp->fec_hash_table_low, 0); 546 #endif 547 548 /* Set maximum receive buffer size. 549 */ 550 out_be32(&fecp->fec_r_buff_size, PKT_MAXBLR_SIZE); 551 552 /* Set maximum frame length 553 */ 554 out_be32(&fecp->fec_r_hash, PKT_MAXBUF_SIZE); 555 556 /* 557 * Setup Buffers and Buffer Descriptors 558 */ 559 rxIdx = 0; 560 txIdx = 0; 561 562 if (!rtx) 563 rtx = (struct common_buf_desc __iomem *) 564 (immr->im_cpm.cp_dpmem + CPM_FEC_BASE); 565 /* 566 * Setup Receiver Buffer Descriptors (13.14.24.18) 567 * Settings: 568 * Empty, Wrap 569 */ 570 for (i = 0; i < PKTBUFSRX; i++) { 571 out_be16(&rtx->rxbd[i].cbd_sc, BD_ENET_RX_EMPTY); 572 out_be16(&rtx->rxbd[i].cbd_datlen, 0); /* Reset */ 573 out_be32(&rtx->rxbd[i].cbd_bufaddr, (uint)net_rx_packets[i]); 574 } 575 setbits_be16(&rtx->rxbd[PKTBUFSRX - 1].cbd_sc, BD_ENET_RX_WRAP); 576 577 /* 578 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) 579 * Settings: 580 * Last, Tx CRC 581 */ 582 for (i = 0; i < TX_BUF_CNT; i++) { 583 out_be16(&rtx->txbd[i].cbd_sc, BD_ENET_TX_LAST | BD_ENET_TX_TC); 584 out_be16(&rtx->txbd[i].cbd_datlen, 0); /* Reset */ 585 out_be32(&rtx->txbd[i].cbd_bufaddr, (uint)txbuf); 586 } 587 setbits_be16(&rtx->txbd[TX_BUF_CNT - 1].cbd_sc, BD_ENET_TX_WRAP); 588 589 /* Set receive and transmit descriptor base 590 */ 591 out_be32(&fecp->fec_r_des_start, (__force unsigned int)rtx->rxbd); 592 out_be32(&fecp->fec_x_des_start, (__force unsigned int)rtx->txbd); 593 594 /* Enable MII mode 595 */ 596 /* Half duplex mode */ 597 out_be32(&fecp->fec_r_cntrl, FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT); 598 out_be32(&fecp->fec_x_cntrl, 0); 599 600 /* Enable big endian and don't care about SDMA FC. 601 */ 602 out_be32(&fecp->fec_fun_code, 0x78000000); 603 604 /* 605 * Setup the pin configuration of the FEC 606 */ 607 fec_pin_init(efis->ether_index); 608 609 rxIdx = 0; 610 txIdx = 0; 611 612 /* 613 * Now enable the transmit and receive processing 614 */ 615 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN); 616 617 if (efis->phy_addr == -1) { 618 #ifdef CONFIG_SYS_DISCOVER_PHY 619 /* 620 * wait for the PHY to wake up after reset 621 */ 622 efis->actual_phy_addr = mii_discover_phy(dev); 623 624 if (efis->actual_phy_addr == -1) { 625 printf("Unable to discover phy!\n"); 626 return -1; 627 } 628 #else 629 efis->actual_phy_addr = -1; 630 #endif 631 } else { 632 efis->actual_phy_addr = efis->phy_addr; 633 } 634 635 #if defined(CONFIG_MII) && defined(CONFIG_RMII) 636 /* 637 * adapt the RMII speed to the speed of the phy 638 */ 639 if (miiphy_speed(dev->name, efis->actual_phy_addr) == _100BASET) 640 fec_100Mbps(dev); 641 else 642 fec_10Mbps(dev); 643 #endif 644 645 #if defined(CONFIG_MII) 646 /* 647 * adapt to the half/full speed settings 648 */ 649 if (miiphy_duplex(dev->name, efis->actual_phy_addr) == FULL) 650 fec_full_duplex(dev); 651 else 652 fec_half_duplex(dev); 653 #endif 654 655 /* And last, try to fill Rx Buffer Descriptors */ 656 /* Descriptor polling active */ 657 out_be32(&fecp->fec_r_des_active, 0x01000000); 658 659 efis->initialized = 1; 660 661 return 0; 662 } 663 664 665 static void fec_halt(struct eth_device *dev) 666 { 667 struct ether_fcc_info_s *efis = dev->priv; 668 fec_t __iomem *fecp = 669 (fec_t __iomem *)(CONFIG_SYS_IMMR + efis->fecp_offset); 670 int i; 671 672 /* avoid halt if initialized; mii gets stuck otherwise */ 673 if (!efis->initialized) 674 return; 675 676 /* Whack a reset. 677 * A delay is required between a reset of the FEC block and 678 * initialization of other FEC registers because the reset takes 679 * some time to complete. If you don't delay, subsequent writes 680 * to FEC registers might get killed by the reset routine which is 681 * still in progress. 682 */ 683 684 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_RESET); 685 for (i = 0; (in_be32(&fecp->fec_ecntrl) & FEC_ECNTRL_RESET) && 686 (i < FEC_RESET_DELAY); ++i) 687 udelay(1); 688 689 if (i == FEC_RESET_DELAY) { 690 printf("FEC_RESET_DELAY timeout\n"); 691 return; 692 } 693 694 efis->initialized = 0; 695 } 696 697 #if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 698 699 /* Make MII read/write commands for the FEC. 700 */ 701 702 #define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ 703 (REG & 0x1f) << 18)) 704 705 #define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ 706 (REG & 0x1f) << 18) | \ 707 (VAL & 0xffff)) 708 709 /* Interrupt events/masks. 710 */ 711 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 712 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 713 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 714 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 715 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ 716 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 717 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ 718 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 719 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 720 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 721 722 /* send command to phy using mii, wait for result */ 723 static uint 724 mii_send(uint mii_cmd) 725 { 726 uint mii_reply; 727 fec_t __iomem *ep; 728 int cnt; 729 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; 730 731 ep = &immr->im_cpm.cp_fec; 732 733 out_be32(&ep->fec_mii_data, mii_cmd); /* command to phy */ 734 735 /* wait for mii complete */ 736 cnt = 0; 737 while (!(in_be32(&ep->fec_ievent) & FEC_ENET_MII)) { 738 if (++cnt > 1000) { 739 printf("mii_send STUCK!\n"); 740 break; 741 } 742 } 743 mii_reply = in_be32(&ep->fec_mii_data); /* result from phy */ 744 out_be32(&ep->fec_ievent, FEC_ENET_MII); /* clear MII complete */ 745 return mii_reply & 0xffff; /* data read from phy */ 746 } 747 #endif 748 749 #if defined(CONFIG_SYS_DISCOVER_PHY) 750 static int mii_discover_phy(struct eth_device *dev) 751 { 752 #define MAX_PHY_PASSES 11 753 uint phyno; 754 int pass; 755 uint phytype; 756 int phyaddr; 757 758 phyaddr = -1; /* didn't find a PHY yet */ 759 for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { 760 if (pass > 1) { 761 /* PHY may need more time to recover from reset. 762 * The LXT970 needs 50ms typical, no maximum is 763 * specified, so wait 10ms before try again. 764 * With 11 passes this gives it 100ms to wake up. 765 */ 766 udelay(10000); /* wait 10ms */ 767 } 768 for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { 769 phytype = mii_send(mk_mii_read(phyno, MII_PHYSID2)); 770 if (phytype != 0xffff) { 771 phyaddr = phyno; 772 phytype |= mii_send(mk_mii_read(phyno, 773 MII_PHYSID1)) << 16; 774 } 775 } 776 } 777 if (phyaddr < 0) 778 printf("No PHY device found.\n"); 779 780 return phyaddr; 781 } 782 #endif /* CONFIG_SYS_DISCOVER_PHY */ 783 784 #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && !defined(CONFIG_BITBANGMII) 785 786 /**************************************************************************** 787 * mii_init -- Initialize the MII via FEC 1 for MII command without ethernet 788 * This function is a subset of eth_init 789 **************************************************************************** 790 */ 791 static void __mii_init(void) 792 { 793 immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; 794 fec_t __iomem *fecp = &immr->im_cpm.cp_fec; 795 796 if (fec_reset(fecp) < 0) 797 printf("FEC_RESET_DELAY timeout\n"); 798 799 /* We use strictly polling mode only 800 */ 801 out_be32(&fecp->fec_imask, 0); 802 803 /* Clear any pending interrupt 804 */ 805 out_be32(&fecp->fec_ievent, 0xffc0); 806 807 /* Now enable the transmit and receive processing 808 */ 809 out_be32(&fecp->fec_ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN); 810 } 811 812 void mii_init(void) 813 { 814 int i; 815 816 __mii_init(); 817 818 /* Setup the pin configuration of the FEC(s) 819 */ 820 for (i = 0; i < ARRAY_SIZE(ether_fcc_info); i++) 821 fec_pin_init(ether_fcc_info[i].ether_index); 822 } 823 824 /***************************************************************************** 825 * Read and write a MII PHY register, routines used by MII Utilities 826 * 827 * FIXME: These routines are expected to return 0 on success, but mii_send 828 * does _not_ return an error code. Maybe 0xFFFF means error, i.e. 829 * no PHY connected... 830 * For now always return 0. 831 * FIXME: These routines only work after calling eth_init() at least once! 832 * Otherwise they hang in mii_send() !!! Sorry! 833 *****************************************************************************/ 834 835 int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) 836 { 837 unsigned short value = 0; 838 short rdreg; /* register working value */ 839 840 rdreg = mii_send(mk_mii_read(addr, reg)); 841 842 value = rdreg; 843 return value; 844 } 845 846 int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, 847 u16 value) 848 { 849 (void)mii_send(mk_mii_write(addr, reg, value)); 850 851 return 0; 852 } 853 #endif 854