1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <malloc.h> 29 30 #include <asm/fec.h> 31 #include <asm/immap.h> 32 33 #include <command.h> 34 #include <net.h> 35 #include <miiphy.h> 36 37 #undef ET_DEBUG 38 #undef MII_DEBUG 39 40 /* Ethernet Transmit and Receive Buffers */ 41 #define DBUF_LENGTH 1520 42 #define TX_BUF_CNT 2 43 #define PKT_MAXBUF_SIZE 1518 44 #define PKT_MINBUF_SIZE 64 45 #define PKT_MAXBLR_SIZE 1520 46 #define LAST_PKTBUFSRX PKTBUFSRX - 1 47 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) 48 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) 49 50 DECLARE_GLOBAL_DATA_PTR; 51 52 struct fec_info_s fec_info[] = { 53 #ifdef CFG_FEC0_IOBASE 54 { 55 0, /* index */ 56 CFG_FEC0_IOBASE, /* io base */ 57 CFG_FEC0_PINMUX, /* gpio pin muxing */ 58 CFG_FEC0_MIIBASE, /* mii base */ 59 -1, /* phy_addr */ 60 0, /* duplex and speed */ 61 0, /* phy name */ 62 0, /* phyname init */ 63 0, /* RX BD */ 64 0, /* TX BD */ 65 0, /* rx Index */ 66 0, /* tx Index */ 67 0, /* tx buffer */ 68 0, /* initialized flag */ 69 (struct fec_info_s *)-1, 70 }, 71 #endif 72 #ifdef CFG_FEC1_IOBASE 73 { 74 1, /* index */ 75 CFG_FEC1_IOBASE, /* io base */ 76 CFG_FEC1_PINMUX, /* gpio pin muxing */ 77 CFG_FEC1_MIIBASE, /* mii base */ 78 -1, /* phy_addr */ 79 0, /* duplex and speed */ 80 0, /* phy name */ 81 0, /* phy name init */ 82 #ifdef CFG_FEC_BUF_USE_SRAM 83 (cbd_t *)DBUF_LENGTH, /* RX BD */ 84 #else 85 0, /* RX BD */ 86 #endif 87 0, /* TX BD */ 88 0, /* rx Index */ 89 0, /* tx Index */ 90 0, /* tx buffer */ 91 0, /* initialized flag */ 92 (struct fec_info_s *)-1, 93 } 94 #endif 95 }; 96 97 int fec_send(struct eth_device *dev, volatile void *packet, int length); 98 int fec_recv(struct eth_device *dev); 99 int fec_init(struct eth_device *dev, bd_t * bd); 100 void fec_halt(struct eth_device *dev); 101 void fec_reset(struct eth_device *dev); 102 103 extern int fecpin_setclear(struct eth_device *dev, int setclear); 104 105 #ifdef CFG_DISCOVER_PHY 106 extern void __mii_init(void); 107 extern uint mii_send(uint mii_cmd); 108 extern int mii_discover_phy(struct eth_device *dev); 109 extern int mcffec_miiphy_read(char *devname, unsigned char addr, 110 unsigned char reg, unsigned short *value); 111 extern int mcffec_miiphy_write(char *devname, unsigned char addr, 112 unsigned char reg, unsigned short value); 113 #endif 114 115 void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) 116 { 117 if ((dup_spd >> 16) == FULL) { 118 /* Set maximum frame length */ 119 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | 120 FEC_RCR_PROM | 0x100; 121 fecp->tcr = FEC_TCR_FDEN; 122 } else { 123 /* Half duplex mode */ 124 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | 125 FEC_RCR_MII_MODE | FEC_RCR_DRT; 126 fecp->tcr &= ~FEC_TCR_FDEN; 127 } 128 129 if ((dup_spd & 0xFFFF) == _100BASET) { 130 #ifdef CONFIG_MCF5445x 131 fecp->rcr &= ~0x200; /* disabled 10T base */ 132 #endif 133 #ifdef MII_DEBUG 134 printf("100Mbps\n"); 135 #endif 136 bd->bi_ethspeed = 100; 137 } else { 138 #ifdef CONFIG_MCF5445x 139 fecp->rcr |= 0x200; /* enabled 10T base */ 140 #endif 141 #ifdef MII_DEBUG 142 printf("10Mbps\n"); 143 #endif 144 bd->bi_ethspeed = 10; 145 } 146 } 147 148 int fec_send(struct eth_device *dev, volatile void *packet, int length) 149 { 150 struct fec_info_s *info = dev->priv; 151 volatile fec_t *fecp = (fec_t *) (info->iobase); 152 int j, rc; 153 u16 phyStatus; 154 155 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); 156 157 /* section 16.9.23.3 158 * Wait for ready 159 */ 160 j = 0; 161 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 162 (j < MCFFEC_TOUT_LOOP)) { 163 udelay(1); 164 j++; 165 } 166 if (j >= MCFFEC_TOUT_LOOP) { 167 printf("TX not ready\n"); 168 } 169 170 info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; 171 info->txbd[info->txIdx].cbd_datlen = length; 172 info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; 173 174 /* Activate transmit Buffer Descriptor polling */ 175 fecp->tdar = 0x01000000; /* Descriptor polling active */ 176 177 #ifndef CFG_FEC_BUF_USE_SRAM 178 /* 179 * FEC unable to initial transmit data packet. 180 * A nop will ensure the descriptor polling active completed. 181 * CF Internal RAM has shorter cycle access than DRAM. If use 182 * DRAM as Buffer descriptor and data, a nop is a must. 183 * Affect only V2 and V3. 184 */ 185 __asm__ ("nop"); 186 187 #endif 188 189 #ifdef CFG_UNIFY_CACHE 190 icache_invalid(); 191 #endif 192 193 j = 0; 194 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 195 (j < MCFFEC_TOUT_LOOP)) { 196 udelay(1); 197 j++; 198 } 199 if (j >= MCFFEC_TOUT_LOOP) { 200 printf("TX timeout\n"); 201 } 202 203 #ifdef ET_DEBUG 204 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", 205 __FILE__, __LINE__, __FUNCTION__, j, 206 info->txbd[info->txIdx].cbd_sc, 207 (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); 208 #endif 209 210 /* return only status bits */ 211 rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); 212 info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; 213 214 return rc; 215 } 216 217 int fec_recv(struct eth_device *dev) 218 { 219 struct fec_info_s *info = dev->priv; 220 volatile fec_t *fecp = (fec_t *) (info->iobase); 221 int length; 222 223 for (;;) { 224 #ifndef CFG_FEC_BUF_USE_SRAM 225 #endif 226 #ifdef CFG_UNIFY_CACHE 227 icache_invalid(); 228 #endif 229 /* section 16.9.23.2 */ 230 if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { 231 length = -1; 232 break; /* nothing received - leave for() loop */ 233 } 234 235 length = info->rxbd[info->rxIdx].cbd_datlen; 236 237 if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) { 238 printf("%s[%d] err: %x\n", 239 __FUNCTION__, __LINE__, 240 info->rxbd[info->rxIdx].cbd_sc); 241 #ifdef ET_DEBUG 242 printf("%s[%d] err: %x\n", 243 __FUNCTION__, __LINE__, 244 info->rxbd[info->rxIdx].cbd_sc); 245 #endif 246 } else { 247 248 length -= 4; 249 /* Pass the packet up to the protocol layers. */ 250 NetReceive(NetRxPackets[info->rxIdx], length); 251 252 fecp->eir |= FEC_EIR_RXF; 253 } 254 255 /* Give the buffer back to the FEC. */ 256 info->rxbd[info->rxIdx].cbd_datlen = 0; 257 258 /* wrap around buffer index when necessary */ 259 if (info->rxIdx == LAST_PKTBUFSRX) { 260 info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E; 261 info->rxIdx = 0; 262 } else { 263 info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY; 264 info->rxIdx++; 265 } 266 267 /* Try to fill Buffer Descriptors */ 268 fecp->rdar = 0x01000000; /* Descriptor polling active */ 269 } 270 271 return length; 272 } 273 274 #ifdef ET_DEBUG 275 void dbgFecRegs(struct eth_device *dev) 276 { 277 struct fec_info_s *info = dev->priv; 278 volatile fec_t *fecp = (fec_t *) (info->iobase); 279 280 printf("=====\n"); 281 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); 282 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); 283 printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar); 284 printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar); 285 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); 286 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); 287 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); 288 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); 289 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); 290 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); 291 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); 292 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); 293 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); 294 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); 295 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); 296 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); 297 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); 298 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); 299 printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr); 300 printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr); 301 printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr); 302 printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr); 303 printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr); 304 305 printf("\n"); 306 printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop, 307 fecp->rmon_t_drop); 308 printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets, 309 fecp->rmon_t_packets); 310 printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt, 311 fecp->rmon_t_bc_pkt); 312 printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt, 313 fecp->rmon_t_mc_pkt); 314 printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align, 315 fecp->rmon_t_crc_align); 316 printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize, 317 fecp->rmon_t_undersize); 318 printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize, 319 fecp->rmon_t_oversize); 320 printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag, 321 fecp->rmon_t_frag); 322 printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab, 323 fecp->rmon_t_jab); 324 printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col, 325 fecp->rmon_t_col); 326 printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64, 327 fecp->rmon_t_p64); 328 printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127, 329 fecp->rmon_t_p65to127); 330 printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255, 331 fecp->rmon_t_p128to255); 332 printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511, 333 fecp->rmon_t_p256to511); 334 printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023, 335 fecp->rmon_t_p512to1023); 336 printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047, 337 fecp->rmon_t_p1024to2047); 338 printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048, 339 fecp->rmon_t_p_gte2048); 340 printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets, 341 fecp->rmon_t_octets); 342 343 printf("\n"); 344 printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop, 345 fecp->ieee_t_drop); 346 printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok, 347 fecp->ieee_t_frame_ok); 348 printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col, 349 fecp->ieee_t_1col); 350 printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol, 351 fecp->ieee_t_mcol); 352 printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def, 353 fecp->ieee_t_def); 354 printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol, 355 fecp->ieee_t_lcol); 356 printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol, 357 fecp->ieee_t_excol); 358 printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr, 359 fecp->ieee_t_macerr); 360 printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr, 361 fecp->ieee_t_cserr); 362 printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe, 363 fecp->ieee_t_sqe); 364 printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc, 365 fecp->ieee_t_fdxfc); 366 printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok, 367 fecp->ieee_t_octets_ok); 368 369 printf("\n"); 370 printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop, 371 fecp->rmon_r_drop); 372 printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets, 373 fecp->rmon_r_packets); 374 printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt, 375 fecp->rmon_r_bc_pkt); 376 printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt, 377 fecp->rmon_r_mc_pkt); 378 printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align, 379 fecp->rmon_r_crc_align); 380 printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize, 381 fecp->rmon_r_undersize); 382 printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize, 383 fecp->rmon_r_oversize); 384 printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag, 385 fecp->rmon_r_frag); 386 printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab, 387 fecp->rmon_r_jab); 388 printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64, 389 fecp->rmon_r_p64); 390 printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127, 391 fecp->rmon_r_p65to127); 392 printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255, 393 fecp->rmon_r_p128to255); 394 printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511, 395 fecp->rmon_r_p256to511); 396 printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023, 397 fecp->rmon_r_p512to1023); 398 printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047, 399 fecp->rmon_r_p1024to2047); 400 printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048, 401 fecp->rmon_r_p_gte2048); 402 printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets, 403 fecp->rmon_r_octets); 404 405 printf("\n"); 406 printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop, 407 fecp->ieee_r_drop); 408 printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok, 409 fecp->ieee_r_frame_ok); 410 printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc, 411 fecp->ieee_r_crc); 412 printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align, 413 fecp->ieee_r_align); 414 printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr, 415 fecp->ieee_r_macerr); 416 printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc, 417 fecp->ieee_r_fdxfc); 418 printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok, 419 fecp->ieee_r_octets_ok); 420 421 printf("\n\n\n"); 422 } 423 #endif 424 425 int fec_init(struct eth_device *dev, bd_t * bd) 426 { 427 struct fec_info_s *info = dev->priv; 428 volatile fec_t *fecp = (fec_t *) (info->iobase); 429 int i; 430 u8 *ea = NULL; 431 432 fecpin_setclear(dev, 1); 433 434 fec_reset(dev); 435 436 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ 437 defined (CFG_DISCOVER_PHY) 438 439 mii_init(); 440 441 setFecDuplexSpeed(fecp, bd, info->dup_spd); 442 #else 443 #ifndef CFG_DISCOVER_PHY 444 setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); 445 #endif /* ifndef CFG_DISCOVER_PHY */ 446 #endif /* CONFIG_CMD_MII || CONFIG_MII */ 447 448 /* We use strictly polling mode only */ 449 fecp->eimr = 0; 450 451 /* Clear any pending interrupt */ 452 fecp->eir = 0xffffffff; 453 454 /* Set station address */ 455 if ((u32) fecp == CFG_FEC0_IOBASE) { 456 #ifdef CFG_FEC1_IOBASE 457 volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE); 458 ea = &bd->bi_enet1addr[0]; 459 fecp1->palr = 460 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 461 fecp1->paur = (ea[4] << 24) | (ea[5] << 16); 462 #endif 463 ea = &bd->bi_enetaddr[0]; 464 fecp->palr = 465 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 466 fecp->paur = (ea[4] << 24) | (ea[5] << 16); 467 } else { 468 #ifdef CFG_FEC0_IOBASE 469 volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE); 470 ea = &bd->bi_enetaddr[0]; 471 fecp0->palr = 472 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 473 fecp0->paur = (ea[4] << 24) | (ea[5] << 16); 474 #endif 475 #ifdef CFG_FEC1_IOBASE 476 ea = &bd->bi_enet1addr[0]; 477 fecp->palr = 478 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 479 fecp->paur = (ea[4] << 24) | (ea[5] << 16); 480 #endif 481 } 482 483 /* Clear unicast address hash table */ 484 fecp->iaur = 0; 485 fecp->ialr = 0; 486 487 /* Clear multicast address hash table */ 488 fecp->gaur = 0; 489 fecp->galr = 0; 490 491 /* Set maximum receive buffer size. */ 492 fecp->emrbr = PKT_MAXBLR_SIZE; 493 494 /* 495 * Setup Buffers and Buffer Desriptors 496 */ 497 info->rxIdx = 0; 498 info->txIdx = 0; 499 500 /* 501 * Setup Receiver Buffer Descriptors (13.14.24.18) 502 * Settings: 503 * Empty, Wrap 504 */ 505 for (i = 0; i < PKTBUFSRX; i++) { 506 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; 507 info->rxbd[i].cbd_datlen = 0; /* Reset */ 508 info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; 509 } 510 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; 511 512 /* 513 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) 514 * Settings: 515 * Last, Tx CRC 516 */ 517 for (i = 0; i < TX_BUF_CNT; i++) { 518 info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; 519 info->txbd[i].cbd_datlen = 0; /* Reset */ 520 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); 521 } 522 info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; 523 524 /* Set receive and transmit descriptor base */ 525 fecp->erdsr = (unsigned int)(&info->rxbd[0]); 526 fecp->etdsr = (unsigned int)(&info->txbd[0]); 527 528 /* Now enable the transmit and receive processing */ 529 fecp->ecr |= FEC_ECR_ETHER_EN; 530 531 /* And last, try to fill Rx Buffer Descriptors */ 532 fecp->rdar = 0x01000000; /* Descriptor polling active */ 533 534 return 1; 535 } 536 537 void fec_reset(struct eth_device *dev) 538 { 539 struct fec_info_s *info = dev->priv; 540 volatile fec_t *fecp = (fec_t *) (info->iobase); 541 int i; 542 543 fecp->ecr = FEC_ECR_RESET; 544 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { 545 udelay(1); 546 } 547 if (i == FEC_RESET_DELAY) { 548 printf("FEC_RESET_DELAY timeout\n"); 549 } 550 } 551 552 void fec_halt(struct eth_device *dev) 553 { 554 struct fec_info_s *info = dev->priv; 555 556 fec_reset(dev); 557 558 fecpin_setclear(dev, 0); 559 560 info->rxIdx = info->txIdx = 0; 561 memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t)); 562 memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t)); 563 memset(info->txbuf, 0, DBUF_LENGTH); 564 } 565 566 int mcffec_initialize(bd_t * bis) 567 { 568 struct eth_device *dev; 569 int i; 570 #ifdef CFG_FEC_BUF_USE_SRAM 571 u32 tmp = CFG_INIT_RAM_ADDR + 0x1000; 572 #endif 573 574 for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { 575 576 dev = 577 (struct eth_device *)memalign(CFG_CACHELINE_SIZE, 578 sizeof *dev); 579 if (dev == NULL) 580 hang(); 581 582 memset(dev, 0, sizeof(*dev)); 583 584 sprintf(dev->name, "FEC%d", fec_info[i].index); 585 586 dev->priv = &fec_info[i]; 587 dev->init = fec_init; 588 dev->halt = fec_halt; 589 dev->send = fec_send; 590 dev->recv = fec_recv; 591 592 /* setup Receive and Transmit buffer descriptor */ 593 #ifdef CFG_FEC_BUF_USE_SRAM 594 fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp); 595 tmp = (u32)fec_info[i].rxbd; 596 fec_info[i].txbd = 597 (cbd_t *)((u32)fec_info[i].txbd + tmp + 598 (PKTBUFSRX * sizeof(cbd_t))); 599 tmp = (u32)fec_info[i].txbd; 600 fec_info[i].txbuf = 601 (char *)((u32)fec_info[i].txbuf + tmp + 602 (CFG_TX_ETH_BUFFER * sizeof(cbd_t))); 603 tmp = (u32)fec_info[i].txbuf; 604 #else 605 fec_info[i].rxbd = 606 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 607 (PKTBUFSRX * sizeof(cbd_t))); 608 fec_info[i].txbd = 609 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 610 (TX_BUF_CNT * sizeof(cbd_t))); 611 fec_info[i].txbuf = 612 (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); 613 #endif 614 615 #ifdef ET_DEBUG 616 printf("rxbd %x txbd %x\n", 617 (int)fec_info[i].rxbd, (int)fec_info[i].txbd); 618 #endif 619 620 fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); 621 622 eth_register(dev); 623 624 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 625 miiphy_register(dev->name, 626 mcffec_miiphy_read, mcffec_miiphy_write); 627 #endif 628 if (i > 0) 629 fec_info[i - 1].next = &fec_info[i]; 630 } 631 fec_info[i - 1].next = &fec_info[0]; 632 633 /* default speed */ 634 bis->bi_ethspeed = 10; 635 636 return 0; 637 } 638