1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <malloc.h> 29 30 #include <asm/fec.h> 31 #include <asm/immap.h> 32 33 #include <command.h> 34 #include <net.h> 35 #include <miiphy.h> 36 37 #undef ET_DEBUG 38 #undef MII_DEBUG 39 40 /* Ethernet Transmit and Receive Buffers */ 41 #define DBUF_LENGTH 1520 42 #define TX_BUF_CNT 2 43 #define PKT_MAXBUF_SIZE 1518 44 #define PKT_MINBUF_SIZE 64 45 #define PKT_MAXBLR_SIZE 1520 46 #define LAST_PKTBUFSRX PKTBUFSRX - 1 47 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) 48 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) 49 50 DECLARE_GLOBAL_DATA_PTR; 51 52 struct fec_info_s fec_info[] = { 53 #ifdef CFG_FEC0_IOBASE 54 { 55 0, /* index */ 56 CFG_FEC0_IOBASE, /* io base */ 57 CFG_FEC0_PINMUX, /* gpio pin muxing */ 58 CFG_FEC0_MIIBASE, /* mii base */ 59 -1, /* phy_addr */ 60 0, /* duplex and speed */ 61 0, /* phy name */ 62 0, /* phyname init */ 63 0, /* RX BD */ 64 0, /* TX BD */ 65 0, /* rx Index */ 66 0, /* tx Index */ 67 0, /* tx buffer */ 68 0, /* initialized flag */ 69 }, 70 #endif 71 #ifdef CFG_FEC1_IOBASE 72 { 73 1, /* index */ 74 CFG_FEC1_IOBASE, /* io base */ 75 CFG_FEC1_PINMUX, /* gpio pin muxing */ 76 CFG_FEC1_MIIBASE, /* mii base */ 77 -1, /* phy_addr */ 78 0, /* duplex and speed */ 79 0, /* phy name */ 80 0, /* phy name init */ 81 0, /* RX BD */ 82 0, /* TX BD */ 83 0, /* rx Index */ 84 0, /* tx Index */ 85 0, /* tx buffer */ 86 0, /* initialized flag */ 87 } 88 #endif 89 }; 90 91 int fec_send(struct eth_device *dev, volatile void *packet, int length); 92 int fec_recv(struct eth_device *dev); 93 int fec_init(struct eth_device *dev, bd_t * bd); 94 void fec_halt(struct eth_device *dev); 95 void fec_reset(struct eth_device *dev); 96 97 extern int fecpin_setclear(struct eth_device *dev, int setclear); 98 99 #ifdef CFG_DISCOVER_PHY 100 extern void __mii_init(void); 101 extern uint mii_send(uint mii_cmd); 102 extern int mii_discover_phy(struct eth_device *dev); 103 extern int mcffec_miiphy_read(char *devname, unsigned char addr, 104 unsigned char reg, unsigned short *value); 105 extern int mcffec_miiphy_write(char *devname, unsigned char addr, 106 unsigned char reg, unsigned short value); 107 #endif 108 109 void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) 110 { 111 if ((dup_spd >> 16) == FULL) { 112 /* Set maximum frame length */ 113 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | 114 FEC_RCR_PROM | 0x100; 115 fecp->tcr = FEC_TCR_FDEN; 116 } else { 117 /* Half duplex mode */ 118 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | 119 FEC_RCR_MII_MODE | FEC_RCR_DRT; 120 fecp->tcr &= ~FEC_TCR_FDEN; 121 } 122 123 if ((dup_spd & 0xFFFF) == _100BASET) { 124 #ifdef CONFIG_MCF5445x 125 fecp->rcr &= ~0x200; /* disabled 10T base */ 126 #endif 127 #ifdef MII_DEBUG 128 printf("100Mbps\n"); 129 #endif 130 bd->bi_ethspeed = 100; 131 } else { 132 #ifdef CONFIG_MCF5445x 133 fecp->rcr |= 0x200; /* enabled 10T base */ 134 #endif 135 #ifdef MII_DEBUG 136 printf("10Mbps\n"); 137 #endif 138 bd->bi_ethspeed = 10; 139 } 140 } 141 142 int fec_send(struct eth_device *dev, volatile void *packet, int length) 143 { 144 struct fec_info_s *info = dev->priv; 145 volatile fec_t *fecp = (fec_t *) (info->iobase); 146 int j, rc; 147 u16 phyStatus; 148 149 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); 150 151 /* section 16.9.23.3 152 * Wait for ready 153 */ 154 j = 0; 155 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 156 (j < MCFFEC_TOUT_LOOP)) { 157 udelay(1); 158 j++; 159 } 160 if (j >= MCFFEC_TOUT_LOOP) { 161 printf("TX not ready\n"); 162 } 163 164 info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; 165 info->txbd[info->txIdx].cbd_datlen = length; 166 info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; 167 168 /* Activate transmit Buffer Descriptor polling */ 169 fecp->tdar = 0x01000000; /* Descriptor polling active */ 170 171 /* FEC fix for MCF5275, FEC unable to initial transmit data packet. 172 * A nop will ensure the descriptor polling active completed. 173 */ 174 #ifdef CONFIG_M5275 175 __asm__ ("nop"); 176 #endif 177 178 #ifdef CFG_UNIFY_CACHE 179 icache_invalid(); 180 #endif 181 j = 0; 182 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 183 (j < MCFFEC_TOUT_LOOP)) { 184 udelay(1); 185 j++; 186 } 187 if (j >= MCFFEC_TOUT_LOOP) { 188 printf("TX timeout\n"); 189 } 190 191 #ifdef ET_DEBUG 192 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", 193 __FILE__, __LINE__, __FUNCTION__, j, 194 info->txbd[info->txIdx].cbd_sc, 195 (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); 196 #endif 197 198 /* return only status bits */ 199 rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); 200 info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; 201 202 return rc; 203 } 204 205 int fec_recv(struct eth_device *dev) 206 { 207 struct fec_info_s *info = dev->priv; 208 volatile fec_t *fecp = (fec_t *) (info->iobase); 209 int length; 210 211 for (;;) { 212 #ifdef CFG_UNIFY_CACHE 213 icache_invalid(); 214 #endif 215 /* section 16.9.23.2 */ 216 if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { 217 length = -1; 218 break; /* nothing received - leave for() loop */ 219 } 220 221 length = info->rxbd[info->rxIdx].cbd_datlen; 222 223 if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) { 224 printf("%s[%d] err: %x\n", 225 __FUNCTION__, __LINE__, 226 info->rxbd[info->rxIdx].cbd_sc); 227 #ifdef ET_DEBUG 228 printf("%s[%d] err: %x\n", 229 __FUNCTION__, __LINE__, 230 info->rxbd[info->rxIdx].cbd_sc); 231 #endif 232 } else { 233 234 length -= 4; 235 /* Pass the packet up to the protocol layers. */ 236 NetReceive(NetRxPackets[info->rxIdx], length); 237 238 fecp->eir |= FEC_EIR_RXF; 239 } 240 241 /* Give the buffer back to the FEC. */ 242 info->rxbd[info->rxIdx].cbd_datlen = 0; 243 244 /* wrap around buffer index when necessary */ 245 if (info->rxIdx == LAST_PKTBUFSRX) { 246 info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E; 247 info->rxIdx = 0; 248 } else { 249 info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY; 250 info->rxIdx++; 251 } 252 253 /* Try to fill Buffer Descriptors */ 254 fecp->rdar = 0x01000000; /* Descriptor polling active */ 255 } 256 257 return length; 258 } 259 260 #ifdef ET_DEBUG 261 void dbgFecRegs(struct eth_device *dev) 262 { 263 struct fec_info_s *info = dev->priv; 264 volatile fec_t *fecp = (fec_t *) (info->iobase); 265 266 printf("=====\n"); 267 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); 268 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); 269 printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar); 270 printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar); 271 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); 272 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); 273 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); 274 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); 275 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); 276 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); 277 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); 278 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); 279 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); 280 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); 281 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); 282 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); 283 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); 284 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); 285 printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr); 286 printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr); 287 printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr); 288 printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr); 289 printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr); 290 291 printf("\n"); 292 printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop, 293 fecp->rmon_t_drop); 294 printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets, 295 fecp->rmon_t_packets); 296 printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt, 297 fecp->rmon_t_bc_pkt); 298 printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt, 299 fecp->rmon_t_mc_pkt); 300 printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align, 301 fecp->rmon_t_crc_align); 302 printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize, 303 fecp->rmon_t_undersize); 304 printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize, 305 fecp->rmon_t_oversize); 306 printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag, 307 fecp->rmon_t_frag); 308 printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab, 309 fecp->rmon_t_jab); 310 printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col, 311 fecp->rmon_t_col); 312 printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64, 313 fecp->rmon_t_p64); 314 printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127, 315 fecp->rmon_t_p65to127); 316 printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255, 317 fecp->rmon_t_p128to255); 318 printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511, 319 fecp->rmon_t_p256to511); 320 printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023, 321 fecp->rmon_t_p512to1023); 322 printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047, 323 fecp->rmon_t_p1024to2047); 324 printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048, 325 fecp->rmon_t_p_gte2048); 326 printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets, 327 fecp->rmon_t_octets); 328 329 printf("\n"); 330 printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop, 331 fecp->ieee_t_drop); 332 printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok, 333 fecp->ieee_t_frame_ok); 334 printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col, 335 fecp->ieee_t_1col); 336 printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol, 337 fecp->ieee_t_mcol); 338 printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def, 339 fecp->ieee_t_def); 340 printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol, 341 fecp->ieee_t_lcol); 342 printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol, 343 fecp->ieee_t_excol); 344 printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr, 345 fecp->ieee_t_macerr); 346 printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr, 347 fecp->ieee_t_cserr); 348 printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe, 349 fecp->ieee_t_sqe); 350 printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc, 351 fecp->ieee_t_fdxfc); 352 printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok, 353 fecp->ieee_t_octets_ok); 354 355 printf("\n"); 356 printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop, 357 fecp->rmon_r_drop); 358 printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets, 359 fecp->rmon_r_packets); 360 printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt, 361 fecp->rmon_r_bc_pkt); 362 printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt, 363 fecp->rmon_r_mc_pkt); 364 printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align, 365 fecp->rmon_r_crc_align); 366 printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize, 367 fecp->rmon_r_undersize); 368 printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize, 369 fecp->rmon_r_oversize); 370 printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag, 371 fecp->rmon_r_frag); 372 printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab, 373 fecp->rmon_r_jab); 374 printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64, 375 fecp->rmon_r_p64); 376 printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127, 377 fecp->rmon_r_p65to127); 378 printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255, 379 fecp->rmon_r_p128to255); 380 printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511, 381 fecp->rmon_r_p256to511); 382 printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023, 383 fecp->rmon_r_p512to1023); 384 printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047, 385 fecp->rmon_r_p1024to2047); 386 printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048, 387 fecp->rmon_r_p_gte2048); 388 printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets, 389 fecp->rmon_r_octets); 390 391 printf("\n"); 392 printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop, 393 fecp->ieee_r_drop); 394 printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok, 395 fecp->ieee_r_frame_ok); 396 printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc, 397 fecp->ieee_r_crc); 398 printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align, 399 fecp->ieee_r_align); 400 printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr, 401 fecp->ieee_r_macerr); 402 printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc, 403 fecp->ieee_r_fdxfc); 404 printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok, 405 fecp->ieee_r_octets_ok); 406 407 printf("\n\n\n"); 408 } 409 #endif 410 411 int fec_init(struct eth_device *dev, bd_t * bd) 412 { 413 struct fec_info_s *info = dev->priv; 414 volatile fec_t *fecp = (fec_t *) (info->iobase); 415 int i; 416 u8 *ea = NULL; 417 418 fecpin_setclear(dev, 1); 419 420 fec_reset(dev); 421 422 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ 423 defined (CFG_DISCOVER_PHY) 424 425 mii_init(); 426 427 setFecDuplexSpeed(fecp, bd, info->dup_spd); 428 #else 429 #ifndef CFG_DISCOVER_PHY 430 setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); 431 #endif /* ifndef CFG_DISCOVER_PHY */ 432 #endif /* CONFIG_CMD_MII || CONFIG_MII */ 433 434 /* We use strictly polling mode only */ 435 fecp->eimr = 0; 436 437 /* Clear any pending interrupt */ 438 fecp->eir = 0xffffffff; 439 440 /* Set station address */ 441 if ((u32) fecp == CFG_FEC0_IOBASE) { 442 #ifdef CFG_FEC1_IOBASE 443 volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE); 444 ea = &bd->bi_enet1addr[0]; 445 fecp1->palr = 446 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 447 fecp1->paur = (ea[4] << 24) | (ea[5] << 16); 448 #endif 449 ea = &bd->bi_enetaddr[0]; 450 fecp->palr = 451 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 452 fecp->paur = (ea[4] << 24) | (ea[5] << 16); 453 } else { 454 #ifdef CFG_FEC0_IOBASE 455 volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE); 456 ea = &bd->bi_enetaddr[0]; 457 fecp0->palr = 458 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 459 fecp0->paur = (ea[4] << 24) | (ea[5] << 16); 460 #endif 461 #ifdef CFG_FEC1_IOBASE 462 ea = &bd->bi_enet1addr[0]; 463 fecp->palr = 464 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 465 fecp->paur = (ea[4] << 24) | (ea[5] << 16); 466 #endif 467 } 468 469 /* Clear unicast address hash table */ 470 fecp->iaur = 0; 471 fecp->ialr = 0; 472 473 /* Clear multicast address hash table */ 474 fecp->gaur = 0; 475 fecp->galr = 0; 476 477 /* Set maximum receive buffer size. */ 478 fecp->emrbr = PKT_MAXBLR_SIZE; 479 480 /* 481 * Setup Buffers and Buffer Desriptors 482 */ 483 info->rxIdx = 0; 484 info->txIdx = 0; 485 486 /* 487 * Setup Receiver Buffer Descriptors (13.14.24.18) 488 * Settings: 489 * Empty, Wrap 490 */ 491 for (i = 0; i < PKTBUFSRX; i++) { 492 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; 493 info->rxbd[i].cbd_datlen = 0; /* Reset */ 494 info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; 495 } 496 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; 497 498 /* 499 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) 500 * Settings: 501 * Last, Tx CRC 502 */ 503 for (i = 0; i < TX_BUF_CNT; i++) { 504 info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; 505 info->txbd[i].cbd_datlen = 0; /* Reset */ 506 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); 507 } 508 info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; 509 510 /* Set receive and transmit descriptor base */ 511 fecp->erdsr = (unsigned int)(&info->rxbd[0]); 512 fecp->etdsr = (unsigned int)(&info->txbd[0]); 513 514 /* Now enable the transmit and receive processing */ 515 fecp->ecr |= FEC_ECR_ETHER_EN; 516 517 /* And last, try to fill Rx Buffer Descriptors */ 518 fecp->rdar = 0x01000000; /* Descriptor polling active */ 519 520 return 1; 521 } 522 523 void fec_reset(struct eth_device *dev) 524 { 525 struct fec_info_s *info = dev->priv; 526 volatile fec_t *fecp = (fec_t *) (info->iobase); 527 int i; 528 529 fecp->ecr = FEC_ECR_RESET; 530 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { 531 udelay(1); 532 } 533 if (i == FEC_RESET_DELAY) { 534 printf("FEC_RESET_DELAY timeout\n"); 535 } 536 } 537 538 void fec_halt(struct eth_device *dev) 539 { 540 struct fec_info_s *info = dev->priv; 541 542 fec_reset(dev); 543 544 fecpin_setclear(dev, 0); 545 546 info->rxIdx = info->txIdx = 0; 547 memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t)); 548 memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t)); 549 memset(info->txbuf, 0, DBUF_LENGTH); 550 } 551 552 int mcffec_initialize(bd_t * bis) 553 { 554 struct eth_device *dev; 555 int i; 556 557 for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { 558 559 dev = 560 (struct eth_device *)memalign(CFG_CACHELINE_SIZE, 561 sizeof *dev); 562 if (dev == NULL) 563 hang(); 564 565 memset(dev, 0, sizeof(*dev)); 566 567 sprintf(dev->name, "FEC%d", fec_info[i].index); 568 569 dev->priv = &fec_info[i]; 570 dev->init = fec_init; 571 dev->halt = fec_halt; 572 dev->send = fec_send; 573 dev->recv = fec_recv; 574 575 /* setup Receive and Transmit buffer descriptor */ 576 fec_info[i].rxbd = 577 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 578 (PKTBUFSRX * sizeof(cbd_t))); 579 fec_info[i].txbd = 580 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 581 (TX_BUF_CNT * sizeof(cbd_t))); 582 fec_info[i].txbuf = 583 (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); 584 #ifdef ET_DEBUG 585 printf("rxbd %x txbd %x\n", 586 (int)fec_info[i].rxbd, (int)fec_info[i].txbd); 587 #endif 588 589 fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); 590 591 eth_register(dev); 592 593 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 594 miiphy_register(dev->name, 595 mcffec_miiphy_read, mcffec_miiphy_write); 596 #endif 597 } 598 599 /* default speed */ 600 bis->bi_ethspeed = 10; 601 602 return 1; 603 } 604