1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <malloc.h> 29 30 #ifdef CONFIG_MCFFEC 31 32 #include <asm/fec.h> 33 #include <asm/immap.h> 34 35 #include <command.h> 36 #include <net.h> 37 #include <miiphy.h> 38 39 #undef ET_DEBUG 40 #undef MII_DEBUG 41 42 /* Ethernet Transmit and Receive Buffers */ 43 #define DBUF_LENGTH 1520 44 #define TX_BUF_CNT 2 45 #define PKT_MAXBUF_SIZE 1518 46 #define PKT_MINBUF_SIZE 64 47 #define PKT_MAXBLR_SIZE 1520 48 #define LAST_PKTBUFSRX PKTBUFSRX - 1 49 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) 50 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) 51 52 DECLARE_GLOBAL_DATA_PTR; 53 54 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) 55 56 struct fec_info_s fec_info[] = { 57 #ifdef CFG_FEC0_IOBASE 58 { 59 0, /* index */ 60 CFG_FEC0_IOBASE, /* io base */ 61 CFG_FEC0_PINMUX, /* gpio pin muxing */ 62 CFG_FEC0_MIIBASE, /* mii base */ 63 -1, /* phy_addr */ 64 0, /* duplex and speed */ 65 0, /* phy name */ 66 0, /* phyname init */ 67 0, /* RX BD */ 68 0, /* TX BD */ 69 0, /* rx Index */ 70 0, /* tx Index */ 71 0, /* tx buffer */ 72 0, /* initialized flag */ 73 }, 74 #endif 75 #ifdef CFG_FEC1_IOBASE 76 { 77 1, /* index */ 78 CFG_FEC1_IOBASE, /* io base */ 79 CFG_FEC1_PINMUX, /* gpio pin muxing */ 80 CFG_FEC1_MIIBASE, /* mii base */ 81 -1, /* phy_addr */ 82 0, /* duplex and speed */ 83 0, /* phy name */ 84 0, /* phy name init */ 85 0, /* RX BD */ 86 0, /* TX BD */ 87 0, /* rx Index */ 88 0, /* tx Index */ 89 0, /* tx buffer */ 90 0, /* initialized flag */ 91 } 92 #endif 93 }; 94 95 int fec_send(struct eth_device *dev, volatile void *packet, int length); 96 int fec_recv(struct eth_device *dev); 97 int fec_init(struct eth_device *dev, bd_t * bd); 98 void fec_halt(struct eth_device *dev); 99 void fec_reset(struct eth_device *dev); 100 101 extern int fecpin_setclear(struct eth_device *dev, int setclear); 102 103 #ifdef CFG_DISCOVER_PHY 104 extern void __mii_init(void); 105 extern uint mii_send(uint mii_cmd); 106 extern int mii_discover_phy(struct eth_device *dev); 107 extern int mcffec_miiphy_read(char *devname, unsigned char addr, 108 unsigned char reg, unsigned short *value); 109 extern int mcffec_miiphy_write(char *devname, unsigned char addr, 110 unsigned char reg, unsigned short value); 111 #endif 112 113 void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) 114 { 115 if ((dup_spd >> 16) == FULL) { 116 /* Set maximum frame length */ 117 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | 118 FEC_RCR_PROM | 0x100; 119 fecp->tcr = FEC_TCR_FDEN; 120 } else { 121 /* Half duplex mode */ 122 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | 123 FEC_RCR_MII_MODE | FEC_RCR_DRT; 124 fecp->tcr &= ~FEC_TCR_FDEN; 125 } 126 127 if ((dup_spd & 0xFFFF) == _100BASET) { 128 #ifdef MII_DEBUG 129 printf("100Mbps\n"); 130 #endif 131 bd->bi_ethspeed = 100; 132 } else { 133 #ifdef MII_DEBUG 134 printf("10Mbps\n"); 135 #endif 136 bd->bi_ethspeed = 10; 137 } 138 } 139 140 int fec_send(struct eth_device *dev, volatile void *packet, int length) 141 { 142 struct fec_info_s *info = dev->priv; 143 volatile fec_t *fecp = (fec_t *) (info->iobase); 144 int j, rc; 145 u16 phyStatus; 146 147 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); 148 149 /* section 16.9.23.3 150 * Wait for ready 151 */ 152 j = 0; 153 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 154 (j < MCFFEC_TOUT_LOOP)) { 155 udelay(1); 156 j++; 157 } 158 if (j >= MCFFEC_TOUT_LOOP) { 159 printf("TX not ready\n"); 160 } 161 162 info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; 163 info->txbd[info->txIdx].cbd_datlen = length; 164 info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; 165 166 /* Activate transmit Buffer Descriptor polling */ 167 fecp->tdar = 0x01000000; /* Descriptor polling active */ 168 169 #ifdef CFG_UNIFY_CACHE 170 icache_invalid(); 171 #endif 172 j = 0; 173 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 174 (j < MCFFEC_TOUT_LOOP)) { 175 udelay(1); 176 j++; 177 } 178 if (j >= MCFFEC_TOUT_LOOP) { 179 printf("TX timeout\n"); 180 } 181 182 #ifdef ET_DEBUG 183 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", 184 __FILE__, __LINE__, __FUNCTION__, j, 185 info->txbd[info->txIdx].cbd_sc, 186 (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); 187 #endif 188 189 /* return only status bits */ 190 rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); 191 info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; 192 193 return rc; 194 } 195 196 int fec_recv(struct eth_device *dev) 197 { 198 struct fec_info_s *info = dev->priv; 199 volatile fec_t *fecp = (fec_t *) (info->iobase); 200 int length; 201 202 for (;;) { 203 #ifdef CFG_UNIFY_CACHE 204 icache_invalid(); 205 #endif 206 /* section 16.9.23.2 */ 207 if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { 208 length = -1; 209 break; /* nothing received - leave for() loop */ 210 } 211 212 length = info->rxbd[info->rxIdx].cbd_datlen; 213 214 if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) { 215 printf("%s[%d] err: %x\n", 216 __FUNCTION__, __LINE__, 217 info->rxbd[info->rxIdx].cbd_sc); 218 #ifdef ET_DEBUG 219 printf("%s[%d] err: %x\n", 220 __FUNCTION__, __LINE__, 221 info->rxbd[info->rxIdx].cbd_sc); 222 #endif 223 } else { 224 225 length -= 4; 226 /* Pass the packet up to the protocol layers. */ 227 NetReceive(NetRxPackets[info->rxIdx], length); 228 229 fecp->eir |= FEC_EIR_RXF; 230 } 231 232 /* Give the buffer back to the FEC. */ 233 info->rxbd[info->rxIdx].cbd_datlen = 0; 234 235 /* wrap around buffer index when necessary */ 236 if (info->rxIdx == LAST_PKTBUFSRX) { 237 info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E; 238 info->rxIdx = 0; 239 } else { 240 info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY; 241 info->rxIdx++; 242 } 243 244 /* Try to fill Buffer Descriptors */ 245 fecp->rdar = 0x01000000; /* Descriptor polling active */ 246 } 247 248 return length; 249 } 250 251 #ifdef ET_DEBUG 252 void dbgFecRegs(struct eth_device *dev) 253 { 254 struct fec_info_s *info = dev->priv; 255 volatile fec_t *fecp = (fec_t *) (info->iobase); 256 257 printf("=====\n"); 258 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); 259 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); 260 printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar); 261 printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar); 262 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); 263 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); 264 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); 265 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); 266 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); 267 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); 268 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); 269 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); 270 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); 271 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); 272 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); 273 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); 274 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); 275 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); 276 printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr); 277 printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr); 278 printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr); 279 printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr); 280 printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr); 281 282 printf("\n"); 283 printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop, 284 fecp->rmon_t_drop); 285 printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets, 286 fecp->rmon_t_packets); 287 printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt, 288 fecp->rmon_t_bc_pkt); 289 printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt, 290 fecp->rmon_t_mc_pkt); 291 printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align, 292 fecp->rmon_t_crc_align); 293 printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize, 294 fecp->rmon_t_undersize); 295 printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize, 296 fecp->rmon_t_oversize); 297 printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag, 298 fecp->rmon_t_frag); 299 printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab, 300 fecp->rmon_t_jab); 301 printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col, 302 fecp->rmon_t_col); 303 printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64, 304 fecp->rmon_t_p64); 305 printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127, 306 fecp->rmon_t_p65to127); 307 printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255, 308 fecp->rmon_t_p128to255); 309 printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511, 310 fecp->rmon_t_p256to511); 311 printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023, 312 fecp->rmon_t_p512to1023); 313 printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047, 314 fecp->rmon_t_p1024to2047); 315 printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048, 316 fecp->rmon_t_p_gte2048); 317 printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets, 318 fecp->rmon_t_octets); 319 320 printf("\n"); 321 printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop, 322 fecp->ieee_t_drop); 323 printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok, 324 fecp->ieee_t_frame_ok); 325 printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col, 326 fecp->ieee_t_1col); 327 printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol, 328 fecp->ieee_t_mcol); 329 printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def, 330 fecp->ieee_t_def); 331 printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol, 332 fecp->ieee_t_lcol); 333 printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol, 334 fecp->ieee_t_excol); 335 printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr, 336 fecp->ieee_t_macerr); 337 printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr, 338 fecp->ieee_t_cserr); 339 printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe, 340 fecp->ieee_t_sqe); 341 printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc, 342 fecp->ieee_t_fdxfc); 343 printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok, 344 fecp->ieee_t_octets_ok); 345 346 printf("\n"); 347 printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop, 348 fecp->rmon_r_drop); 349 printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets, 350 fecp->rmon_r_packets); 351 printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt, 352 fecp->rmon_r_bc_pkt); 353 printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt, 354 fecp->rmon_r_mc_pkt); 355 printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align, 356 fecp->rmon_r_crc_align); 357 printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize, 358 fecp->rmon_r_undersize); 359 printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize, 360 fecp->rmon_r_oversize); 361 printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag, 362 fecp->rmon_r_frag); 363 printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab, 364 fecp->rmon_r_jab); 365 printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64, 366 fecp->rmon_r_p64); 367 printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127, 368 fecp->rmon_r_p65to127); 369 printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255, 370 fecp->rmon_r_p128to255); 371 printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511, 372 fecp->rmon_r_p256to511); 373 printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023, 374 fecp->rmon_r_p512to1023); 375 printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047, 376 fecp->rmon_r_p1024to2047); 377 printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048, 378 fecp->rmon_r_p_gte2048); 379 printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets, 380 fecp->rmon_r_octets); 381 382 printf("\n"); 383 printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop, 384 fecp->ieee_r_drop); 385 printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok, 386 fecp->ieee_r_frame_ok); 387 printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc, 388 fecp->ieee_r_crc); 389 printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align, 390 fecp->ieee_r_align); 391 printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr, 392 fecp->ieee_r_macerr); 393 printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc, 394 fecp->ieee_r_fdxfc); 395 printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok, 396 fecp->ieee_r_octets_ok); 397 398 printf("\n\n\n"); 399 } 400 #endif 401 402 int fec_init(struct eth_device *dev, bd_t * bd) 403 { 404 struct fec_info_s *info = dev->priv; 405 volatile fec_t *fecp = (fec_t *) (info->iobase); 406 int i; 407 u8 *ea = NULL; 408 409 fecpin_setclear(dev, 1); 410 411 fec_reset(dev); 412 413 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ 414 defined (CFG_DISCOVER_PHY) 415 416 mii_init(); 417 418 setFecDuplexSpeed(fecp, bd, info->dup_spd); 419 #else 420 #ifndef CFG_DISCOVER_PHY 421 setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); 422 #endif /* ifndef CFG_DISCOVER_PHY */ 423 #endif /* CONFIG_CMD_MII || CONFIG_MII */ 424 425 /* We use strictly polling mode only */ 426 fecp->eimr = 0; 427 428 /* Clear any pending interrupt */ 429 fecp->eir = 0xffffffff; 430 431 /* Set station address */ 432 if ((u32) fecp == CFG_FEC0_IOBASE) { 433 #ifdef CFG_FEC1_IOBASE 434 volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE); 435 ea = &bd->bi_enet1addr[0]; 436 fecp1->palr = 437 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 438 fecp1->paur = (ea[4] << 24) | (ea[5] << 16); 439 #endif 440 ea = &bd->bi_enetaddr[0]; 441 fecp->palr = 442 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 443 fecp->paur = (ea[4] << 24) | (ea[5] << 16); 444 } else { 445 #ifdef CFG_FEC0_IOBASE 446 volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE); 447 ea = &bd->bi_enetaddr[0]; 448 fecp0->palr = 449 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 450 fecp0->paur = (ea[4] << 24) | (ea[5] << 16); 451 #endif 452 #ifdef CFG_FEC1_IOBASE 453 ea = &bd->bi_enet1addr[0]; 454 fecp->palr = 455 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 456 fecp->paur = (ea[4] << 24) | (ea[5] << 16); 457 #endif 458 } 459 460 /* Clear unicast address hash table */ 461 fecp->iaur = 0; 462 fecp->ialr = 0; 463 464 /* Clear multicast address hash table */ 465 fecp->gaur = 0; 466 fecp->galr = 0; 467 468 /* Set maximum receive buffer size. */ 469 fecp->emrbr = PKT_MAXBLR_SIZE; 470 471 /* 472 * Setup Buffers and Buffer Desriptors 473 */ 474 info->rxIdx = 0; 475 info->txIdx = 0; 476 477 /* 478 * Setup Receiver Buffer Descriptors (13.14.24.18) 479 * Settings: 480 * Empty, Wrap 481 */ 482 for (i = 0; i < PKTBUFSRX; i++) { 483 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; 484 info->rxbd[i].cbd_datlen = 0; /* Reset */ 485 info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; 486 } 487 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; 488 489 /* 490 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) 491 * Settings: 492 * Last, Tx CRC 493 */ 494 for (i = 0; i < TX_BUF_CNT; i++) { 495 info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; 496 info->txbd[i].cbd_datlen = 0; /* Reset */ 497 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); 498 } 499 info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; 500 501 /* Set receive and transmit descriptor base */ 502 fecp->erdsr = (unsigned int)(&info->rxbd[0]); 503 fecp->etdsr = (unsigned int)(&info->txbd[0]); 504 505 /* Now enable the transmit and receive processing */ 506 fecp->ecr |= FEC_ECR_ETHER_EN; 507 508 /* And last, try to fill Rx Buffer Descriptors */ 509 fecp->rdar = 0x01000000; /* Descriptor polling active */ 510 511 return 1; 512 } 513 514 void fec_reset(struct eth_device *dev) 515 { 516 struct fec_info_s *info = dev->priv; 517 volatile fec_t *fecp = (fec_t *) (info->iobase); 518 int i; 519 520 fecp->ecr = FEC_ECR_RESET; 521 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { 522 udelay(1); 523 } 524 if (i == FEC_RESET_DELAY) { 525 printf("FEC_RESET_DELAY timeout\n"); 526 } 527 } 528 529 void fec_halt(struct eth_device *dev) 530 { 531 struct fec_info_s *info = dev->priv; 532 533 fec_reset(dev); 534 535 fecpin_setclear(dev, 0); 536 537 info->rxIdx = info->txIdx = 0; 538 memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t)); 539 memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t)); 540 memset(info->txbuf, 0, DBUF_LENGTH); 541 } 542 543 int mcffec_initialize(bd_t * bis) 544 { 545 struct eth_device *dev; 546 int i; 547 548 for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { 549 550 dev = 551 (struct eth_device *)memalign(CFG_CACHELINE_SIZE, 552 sizeof *dev); 553 if (dev == NULL) 554 hang(); 555 556 memset(dev, 0, sizeof(*dev)); 557 558 sprintf(dev->name, "FEC%d", fec_info[i].index); 559 560 dev->priv = &fec_info[i]; 561 dev->init = fec_init; 562 dev->halt = fec_halt; 563 dev->send = fec_send; 564 dev->recv = fec_recv; 565 566 /* setup Receive and Transmit buffer descriptor */ 567 fec_info[i].rxbd = 568 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 569 (PKTBUFSRX * sizeof(cbd_t))); 570 fec_info[i].txbd = 571 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 572 (TX_BUF_CNT * sizeof(cbd_t))); 573 fec_info[i].txbuf = 574 (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); 575 #ifdef ET_DEBUG 576 printf("rxbd %x txbd %x\n", 577 (int)fec_info[i].rxbd, (int)fec_info[i].txbd); 578 #endif 579 580 fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); 581 582 eth_register(dev); 583 584 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 585 miiphy_register(dev->name, 586 mcffec_miiphy_read, mcffec_miiphy_write); 587 #endif 588 } 589 590 /* default speed */ 591 bis->bi_ethspeed = 10; 592 593 return 1; 594 } 595 596 #endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ 597 #endif /* CONFIG_MCFFEC */ 598