1 /* 2 * (C) Copyright 2000-2004 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27 #include <common.h> 28 #include <malloc.h> 29 30 #include <asm/fec.h> 31 #include <asm/immap.h> 32 33 #include <command.h> 34 #include <net.h> 35 #include <netdev.h> 36 #include <miiphy.h> 37 38 #undef ET_DEBUG 39 #undef MII_DEBUG 40 41 /* Ethernet Transmit and Receive Buffers */ 42 #define DBUF_LENGTH 1520 43 #define TX_BUF_CNT 2 44 #define PKT_MAXBUF_SIZE 1518 45 #define PKT_MINBUF_SIZE 64 46 #define PKT_MAXBLR_SIZE 1520 47 #define LAST_PKTBUFSRX PKTBUFSRX - 1 48 #define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) 49 #define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) 50 51 DECLARE_GLOBAL_DATA_PTR; 52 53 struct fec_info_s fec_info[] = { 54 #ifdef CFG_FEC0_IOBASE 55 { 56 0, /* index */ 57 CFG_FEC0_IOBASE, /* io base */ 58 CFG_FEC0_PINMUX, /* gpio pin muxing */ 59 CFG_FEC0_MIIBASE, /* mii base */ 60 -1, /* phy_addr */ 61 0, /* duplex and speed */ 62 0, /* phy name */ 63 0, /* phyname init */ 64 0, /* RX BD */ 65 0, /* TX BD */ 66 0, /* rx Index */ 67 0, /* tx Index */ 68 0, /* tx buffer */ 69 0, /* initialized flag */ 70 (struct fec_info_s *)-1, 71 }, 72 #endif 73 #ifdef CFG_FEC1_IOBASE 74 { 75 1, /* index */ 76 CFG_FEC1_IOBASE, /* io base */ 77 CFG_FEC1_PINMUX, /* gpio pin muxing */ 78 CFG_FEC1_MIIBASE, /* mii base */ 79 -1, /* phy_addr */ 80 0, /* duplex and speed */ 81 0, /* phy name */ 82 0, /* phy name init */ 83 #ifdef CFG_FEC_BUF_USE_SRAM 84 (cbd_t *)DBUF_LENGTH, /* RX BD */ 85 #else 86 0, /* RX BD */ 87 #endif 88 0, /* TX BD */ 89 0, /* rx Index */ 90 0, /* tx Index */ 91 0, /* tx buffer */ 92 0, /* initialized flag */ 93 (struct fec_info_s *)-1, 94 } 95 #endif 96 }; 97 98 int fec_send(struct eth_device *dev, volatile void *packet, int length); 99 int fec_recv(struct eth_device *dev); 100 int fec_init(struct eth_device *dev, bd_t * bd); 101 void fec_halt(struct eth_device *dev); 102 void fec_reset(struct eth_device *dev); 103 104 extern int fecpin_setclear(struct eth_device *dev, int setclear); 105 106 #ifdef CFG_DISCOVER_PHY 107 extern void __mii_init(void); 108 extern uint mii_send(uint mii_cmd); 109 extern int mii_discover_phy(struct eth_device *dev); 110 extern int mcffec_miiphy_read(char *devname, unsigned char addr, 111 unsigned char reg, unsigned short *value); 112 extern int mcffec_miiphy_write(char *devname, unsigned char addr, 113 unsigned char reg, unsigned short value); 114 #endif 115 116 void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) 117 { 118 if ((dup_spd >> 16) == FULL) { 119 /* Set maximum frame length */ 120 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | 121 FEC_RCR_PROM | 0x100; 122 fecp->tcr = FEC_TCR_FDEN; 123 } else { 124 /* Half duplex mode */ 125 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | 126 FEC_RCR_MII_MODE | FEC_RCR_DRT; 127 fecp->tcr &= ~FEC_TCR_FDEN; 128 } 129 130 if ((dup_spd & 0xFFFF) == _100BASET) { 131 #ifdef CONFIG_MCF5445x 132 fecp->rcr &= ~0x200; /* disabled 10T base */ 133 #endif 134 #ifdef MII_DEBUG 135 printf("100Mbps\n"); 136 #endif 137 bd->bi_ethspeed = 100; 138 } else { 139 #ifdef CONFIG_MCF5445x 140 fecp->rcr |= 0x200; /* enabled 10T base */ 141 #endif 142 #ifdef MII_DEBUG 143 printf("10Mbps\n"); 144 #endif 145 bd->bi_ethspeed = 10; 146 } 147 } 148 149 int fec_send(struct eth_device *dev, volatile void *packet, int length) 150 { 151 struct fec_info_s *info = dev->priv; 152 volatile fec_t *fecp = (fec_t *) (info->iobase); 153 int j, rc; 154 u16 phyStatus; 155 156 miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); 157 158 /* section 16.9.23.3 159 * Wait for ready 160 */ 161 j = 0; 162 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 163 (j < MCFFEC_TOUT_LOOP)) { 164 udelay(1); 165 j++; 166 } 167 if (j >= MCFFEC_TOUT_LOOP) { 168 printf("TX not ready\n"); 169 } 170 171 info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; 172 info->txbd[info->txIdx].cbd_datlen = length; 173 info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; 174 175 /* Activate transmit Buffer Descriptor polling */ 176 fecp->tdar = 0x01000000; /* Descriptor polling active */ 177 178 #ifndef CFG_FEC_BUF_USE_SRAM 179 /* 180 * FEC unable to initial transmit data packet. 181 * A nop will ensure the descriptor polling active completed. 182 * CF Internal RAM has shorter cycle access than DRAM. If use 183 * DRAM as Buffer descriptor and data, a nop is a must. 184 * Affect only V2 and V3. 185 */ 186 __asm__ ("nop"); 187 188 #endif 189 190 #ifdef CFG_UNIFY_CACHE 191 icache_invalid(); 192 #endif 193 194 j = 0; 195 while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && 196 (j < MCFFEC_TOUT_LOOP)) { 197 udelay(1); 198 j++; 199 } 200 if (j >= MCFFEC_TOUT_LOOP) { 201 printf("TX timeout\n"); 202 } 203 204 #ifdef ET_DEBUG 205 printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", 206 __FILE__, __LINE__, __FUNCTION__, j, 207 info->txbd[info->txIdx].cbd_sc, 208 (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); 209 #endif 210 211 /* return only status bits */ 212 rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); 213 info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; 214 215 return rc; 216 } 217 218 int fec_recv(struct eth_device *dev) 219 { 220 struct fec_info_s *info = dev->priv; 221 volatile fec_t *fecp = (fec_t *) (info->iobase); 222 int length; 223 224 for (;;) { 225 #ifndef CFG_FEC_BUF_USE_SRAM 226 #endif 227 #ifdef CFG_UNIFY_CACHE 228 icache_invalid(); 229 #endif 230 /* section 16.9.23.2 */ 231 if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { 232 length = -1; 233 break; /* nothing received - leave for() loop */ 234 } 235 236 length = info->rxbd[info->rxIdx].cbd_datlen; 237 238 if (info->rxbd[info->rxIdx].cbd_sc & 0x003f) { 239 printf("%s[%d] err: %x\n", 240 __FUNCTION__, __LINE__, 241 info->rxbd[info->rxIdx].cbd_sc); 242 #ifdef ET_DEBUG 243 printf("%s[%d] err: %x\n", 244 __FUNCTION__, __LINE__, 245 info->rxbd[info->rxIdx].cbd_sc); 246 #endif 247 } else { 248 249 length -= 4; 250 /* Pass the packet up to the protocol layers. */ 251 NetReceive(NetRxPackets[info->rxIdx], length); 252 253 fecp->eir |= FEC_EIR_RXF; 254 } 255 256 /* Give the buffer back to the FEC. */ 257 info->rxbd[info->rxIdx].cbd_datlen = 0; 258 259 /* wrap around buffer index when necessary */ 260 if (info->rxIdx == LAST_PKTBUFSRX) { 261 info->rxbd[PKTBUFSRX - 1].cbd_sc = BD_ENET_RX_W_E; 262 info->rxIdx = 0; 263 } else { 264 info->rxbd[info->rxIdx].cbd_sc = BD_ENET_RX_EMPTY; 265 info->rxIdx++; 266 } 267 268 /* Try to fill Buffer Descriptors */ 269 fecp->rdar = 0x01000000; /* Descriptor polling active */ 270 } 271 272 return length; 273 } 274 275 #ifdef ET_DEBUG 276 void dbgFecRegs(struct eth_device *dev) 277 { 278 struct fec_info_s *info = dev->priv; 279 volatile fec_t *fecp = (fec_t *) (info->iobase); 280 281 printf("=====\n"); 282 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); 283 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); 284 printf("r_des_active %x - %x\n", (int)&fecp->rdar, fecp->rdar); 285 printf("x_des_active %x - %x\n", (int)&fecp->tdar, fecp->tdar); 286 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); 287 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); 288 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); 289 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); 290 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); 291 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); 292 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); 293 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); 294 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); 295 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); 296 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); 297 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); 298 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); 299 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); 300 printf("r_bound %x - %x\n", (int)&fecp->frbr, fecp->frbr); 301 printf("r_fstart %x - %x\n", (int)&fecp->frsr, fecp->frsr); 302 printf("r_drng %x - %x\n", (int)&fecp->erdsr, fecp->erdsr); 303 printf("x_drng %x - %x\n", (int)&fecp->etdsr, fecp->etdsr); 304 printf("r_bufsz %x - %x\n", (int)&fecp->emrbr, fecp->emrbr); 305 306 printf("\n"); 307 printf("rmon_t_drop %x - %x\n", (int)&fecp->rmon_t_drop, 308 fecp->rmon_t_drop); 309 printf("rmon_t_packets %x - %x\n", (int)&fecp->rmon_t_packets, 310 fecp->rmon_t_packets); 311 printf("rmon_t_bc_pkt %x - %x\n", (int)&fecp->rmon_t_bc_pkt, 312 fecp->rmon_t_bc_pkt); 313 printf("rmon_t_mc_pkt %x - %x\n", (int)&fecp->rmon_t_mc_pkt, 314 fecp->rmon_t_mc_pkt); 315 printf("rmon_t_crc_align %x - %x\n", (int)&fecp->rmon_t_crc_align, 316 fecp->rmon_t_crc_align); 317 printf("rmon_t_undersize %x - %x\n", (int)&fecp->rmon_t_undersize, 318 fecp->rmon_t_undersize); 319 printf("rmon_t_oversize %x - %x\n", (int)&fecp->rmon_t_oversize, 320 fecp->rmon_t_oversize); 321 printf("rmon_t_frag %x - %x\n", (int)&fecp->rmon_t_frag, 322 fecp->rmon_t_frag); 323 printf("rmon_t_jab %x - %x\n", (int)&fecp->rmon_t_jab, 324 fecp->rmon_t_jab); 325 printf("rmon_t_col %x - %x\n", (int)&fecp->rmon_t_col, 326 fecp->rmon_t_col); 327 printf("rmon_t_p64 %x - %x\n", (int)&fecp->rmon_t_p64, 328 fecp->rmon_t_p64); 329 printf("rmon_t_p65to127 %x - %x\n", (int)&fecp->rmon_t_p65to127, 330 fecp->rmon_t_p65to127); 331 printf("rmon_t_p128to255 %x - %x\n", (int)&fecp->rmon_t_p128to255, 332 fecp->rmon_t_p128to255); 333 printf("rmon_t_p256to511 %x - %x\n", (int)&fecp->rmon_t_p256to511, 334 fecp->rmon_t_p256to511); 335 printf("rmon_t_p512to1023 %x - %x\n", (int)&fecp->rmon_t_p512to1023, 336 fecp->rmon_t_p512to1023); 337 printf("rmon_t_p1024to2047 %x - %x\n", (int)&fecp->rmon_t_p1024to2047, 338 fecp->rmon_t_p1024to2047); 339 printf("rmon_t_p_gte2048 %x - %x\n", (int)&fecp->rmon_t_p_gte2048, 340 fecp->rmon_t_p_gte2048); 341 printf("rmon_t_octets %x - %x\n", (int)&fecp->rmon_t_octets, 342 fecp->rmon_t_octets); 343 344 printf("\n"); 345 printf("ieee_t_drop %x - %x\n", (int)&fecp->ieee_t_drop, 346 fecp->ieee_t_drop); 347 printf("ieee_t_frame_ok %x - %x\n", (int)&fecp->ieee_t_frame_ok, 348 fecp->ieee_t_frame_ok); 349 printf("ieee_t_1col %x - %x\n", (int)&fecp->ieee_t_1col, 350 fecp->ieee_t_1col); 351 printf("ieee_t_mcol %x - %x\n", (int)&fecp->ieee_t_mcol, 352 fecp->ieee_t_mcol); 353 printf("ieee_t_def %x - %x\n", (int)&fecp->ieee_t_def, 354 fecp->ieee_t_def); 355 printf("ieee_t_lcol %x - %x\n", (int)&fecp->ieee_t_lcol, 356 fecp->ieee_t_lcol); 357 printf("ieee_t_excol %x - %x\n", (int)&fecp->ieee_t_excol, 358 fecp->ieee_t_excol); 359 printf("ieee_t_macerr %x - %x\n", (int)&fecp->ieee_t_macerr, 360 fecp->ieee_t_macerr); 361 printf("ieee_t_cserr %x - %x\n", (int)&fecp->ieee_t_cserr, 362 fecp->ieee_t_cserr); 363 printf("ieee_t_sqe %x - %x\n", (int)&fecp->ieee_t_sqe, 364 fecp->ieee_t_sqe); 365 printf("ieee_t_fdxfc %x - %x\n", (int)&fecp->ieee_t_fdxfc, 366 fecp->ieee_t_fdxfc); 367 printf("ieee_t_octets_ok %x - %x\n", (int)&fecp->ieee_t_octets_ok, 368 fecp->ieee_t_octets_ok); 369 370 printf("\n"); 371 printf("rmon_r_drop %x - %x\n", (int)&fecp->rmon_r_drop, 372 fecp->rmon_r_drop); 373 printf("rmon_r_packets %x - %x\n", (int)&fecp->rmon_r_packets, 374 fecp->rmon_r_packets); 375 printf("rmon_r_bc_pkt %x - %x\n", (int)&fecp->rmon_r_bc_pkt, 376 fecp->rmon_r_bc_pkt); 377 printf("rmon_r_mc_pkt %x - %x\n", (int)&fecp->rmon_r_mc_pkt, 378 fecp->rmon_r_mc_pkt); 379 printf("rmon_r_crc_align %x - %x\n", (int)&fecp->rmon_r_crc_align, 380 fecp->rmon_r_crc_align); 381 printf("rmon_r_undersize %x - %x\n", (int)&fecp->rmon_r_undersize, 382 fecp->rmon_r_undersize); 383 printf("rmon_r_oversize %x - %x\n", (int)&fecp->rmon_r_oversize, 384 fecp->rmon_r_oversize); 385 printf("rmon_r_frag %x - %x\n", (int)&fecp->rmon_r_frag, 386 fecp->rmon_r_frag); 387 printf("rmon_r_jab %x - %x\n", (int)&fecp->rmon_r_jab, 388 fecp->rmon_r_jab); 389 printf("rmon_r_p64 %x - %x\n", (int)&fecp->rmon_r_p64, 390 fecp->rmon_r_p64); 391 printf("rmon_r_p65to127 %x - %x\n", (int)&fecp->rmon_r_p65to127, 392 fecp->rmon_r_p65to127); 393 printf("rmon_r_p128to255 %x - %x\n", (int)&fecp->rmon_r_p128to255, 394 fecp->rmon_r_p128to255); 395 printf("rmon_r_p256to511 %x - %x\n", (int)&fecp->rmon_r_p256to511, 396 fecp->rmon_r_p256to511); 397 printf("rmon_r_p512to1023 %x - %x\n", (int)&fecp->rmon_r_p512to1023, 398 fecp->rmon_r_p512to1023); 399 printf("rmon_r_p1024to2047 %x - %x\n", (int)&fecp->rmon_r_p1024to2047, 400 fecp->rmon_r_p1024to2047); 401 printf("rmon_r_p_gte2048 %x - %x\n", (int)&fecp->rmon_r_p_gte2048, 402 fecp->rmon_r_p_gte2048); 403 printf("rmon_r_octets %x - %x\n", (int)&fecp->rmon_r_octets, 404 fecp->rmon_r_octets); 405 406 printf("\n"); 407 printf("ieee_r_drop %x - %x\n", (int)&fecp->ieee_r_drop, 408 fecp->ieee_r_drop); 409 printf("ieee_r_frame_ok %x - %x\n", (int)&fecp->ieee_r_frame_ok, 410 fecp->ieee_r_frame_ok); 411 printf("ieee_r_crc %x - %x\n", (int)&fecp->ieee_r_crc, 412 fecp->ieee_r_crc); 413 printf("ieee_r_align %x - %x\n", (int)&fecp->ieee_r_align, 414 fecp->ieee_r_align); 415 printf("ieee_r_macerr %x - %x\n", (int)&fecp->ieee_r_macerr, 416 fecp->ieee_r_macerr); 417 printf("ieee_r_fdxfc %x - %x\n", (int)&fecp->ieee_r_fdxfc, 418 fecp->ieee_r_fdxfc); 419 printf("ieee_r_octets_ok %x - %x\n", (int)&fecp->ieee_r_octets_ok, 420 fecp->ieee_r_octets_ok); 421 422 printf("\n\n\n"); 423 } 424 #endif 425 426 int fec_init(struct eth_device *dev, bd_t * bd) 427 { 428 struct fec_info_s *info = dev->priv; 429 volatile fec_t *fecp = (fec_t *) (info->iobase); 430 int i; 431 u8 *ea = NULL; 432 433 fecpin_setclear(dev, 1); 434 435 fec_reset(dev); 436 437 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ 438 defined (CFG_DISCOVER_PHY) 439 440 mii_init(); 441 442 setFecDuplexSpeed(fecp, bd, info->dup_spd); 443 #else 444 #ifndef CFG_DISCOVER_PHY 445 setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); 446 #endif /* ifndef CFG_DISCOVER_PHY */ 447 #endif /* CONFIG_CMD_MII || CONFIG_MII */ 448 449 /* We use strictly polling mode only */ 450 fecp->eimr = 0; 451 452 /* Clear any pending interrupt */ 453 fecp->eir = 0xffffffff; 454 455 /* Set station address */ 456 if ((u32) fecp == CFG_FEC0_IOBASE) { 457 #ifdef CFG_FEC1_IOBASE 458 volatile fec_t *fecp1 = (fec_t *) (CFG_FEC1_IOBASE); 459 ea = &bd->bi_enet1addr[0]; 460 fecp1->palr = 461 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 462 fecp1->paur = (ea[4] << 24) | (ea[5] << 16); 463 #endif 464 ea = &bd->bi_enetaddr[0]; 465 fecp->palr = 466 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 467 fecp->paur = (ea[4] << 24) | (ea[5] << 16); 468 } else { 469 #ifdef CFG_FEC0_IOBASE 470 volatile fec_t *fecp0 = (fec_t *) (CFG_FEC0_IOBASE); 471 ea = &bd->bi_enetaddr[0]; 472 fecp0->palr = 473 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 474 fecp0->paur = (ea[4] << 24) | (ea[5] << 16); 475 #endif 476 #ifdef CFG_FEC1_IOBASE 477 ea = &bd->bi_enet1addr[0]; 478 fecp->palr = 479 (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]); 480 fecp->paur = (ea[4] << 24) | (ea[5] << 16); 481 #endif 482 } 483 484 /* Clear unicast address hash table */ 485 fecp->iaur = 0; 486 fecp->ialr = 0; 487 488 /* Clear multicast address hash table */ 489 fecp->gaur = 0; 490 fecp->galr = 0; 491 492 /* Set maximum receive buffer size. */ 493 fecp->emrbr = PKT_MAXBLR_SIZE; 494 495 /* 496 * Setup Buffers and Buffer Desriptors 497 */ 498 info->rxIdx = 0; 499 info->txIdx = 0; 500 501 /* 502 * Setup Receiver Buffer Descriptors (13.14.24.18) 503 * Settings: 504 * Empty, Wrap 505 */ 506 for (i = 0; i < PKTBUFSRX; i++) { 507 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; 508 info->rxbd[i].cbd_datlen = 0; /* Reset */ 509 info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; 510 } 511 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; 512 513 /* 514 * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) 515 * Settings: 516 * Last, Tx CRC 517 */ 518 for (i = 0; i < TX_BUF_CNT; i++) { 519 info->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC; 520 info->txbd[i].cbd_datlen = 0; /* Reset */ 521 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); 522 } 523 info->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; 524 525 /* Set receive and transmit descriptor base */ 526 fecp->erdsr = (unsigned int)(&info->rxbd[0]); 527 fecp->etdsr = (unsigned int)(&info->txbd[0]); 528 529 /* Now enable the transmit and receive processing */ 530 fecp->ecr |= FEC_ECR_ETHER_EN; 531 532 /* And last, try to fill Rx Buffer Descriptors */ 533 fecp->rdar = 0x01000000; /* Descriptor polling active */ 534 535 return 1; 536 } 537 538 void fec_reset(struct eth_device *dev) 539 { 540 struct fec_info_s *info = dev->priv; 541 volatile fec_t *fecp = (fec_t *) (info->iobase); 542 int i; 543 544 fecp->ecr = FEC_ECR_RESET; 545 for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { 546 udelay(1); 547 } 548 if (i == FEC_RESET_DELAY) { 549 printf("FEC_RESET_DELAY timeout\n"); 550 } 551 } 552 553 void fec_halt(struct eth_device *dev) 554 { 555 struct fec_info_s *info = dev->priv; 556 557 fec_reset(dev); 558 559 fecpin_setclear(dev, 0); 560 561 info->rxIdx = info->txIdx = 0; 562 memset(info->rxbd, 0, PKTBUFSRX * sizeof(cbd_t)); 563 memset(info->txbd, 0, TX_BUF_CNT * sizeof(cbd_t)); 564 memset(info->txbuf, 0, DBUF_LENGTH); 565 } 566 567 int mcffec_initialize(bd_t * bis) 568 { 569 struct eth_device *dev; 570 int i; 571 #ifdef CFG_FEC_BUF_USE_SRAM 572 u32 tmp = CFG_INIT_RAM_ADDR + 0x1000; 573 #endif 574 575 for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { 576 577 dev = 578 (struct eth_device *)memalign(CFG_CACHELINE_SIZE, 579 sizeof *dev); 580 if (dev == NULL) 581 hang(); 582 583 memset(dev, 0, sizeof(*dev)); 584 585 sprintf(dev->name, "FEC%d", fec_info[i].index); 586 587 dev->priv = &fec_info[i]; 588 dev->init = fec_init; 589 dev->halt = fec_halt; 590 dev->send = fec_send; 591 dev->recv = fec_recv; 592 593 /* setup Receive and Transmit buffer descriptor */ 594 #ifdef CFG_FEC_BUF_USE_SRAM 595 fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp); 596 tmp = (u32)fec_info[i].rxbd; 597 fec_info[i].txbd = 598 (cbd_t *)((u32)fec_info[i].txbd + tmp + 599 (PKTBUFSRX * sizeof(cbd_t))); 600 tmp = (u32)fec_info[i].txbd; 601 fec_info[i].txbuf = 602 (char *)((u32)fec_info[i].txbuf + tmp + 603 (CFG_TX_ETH_BUFFER * sizeof(cbd_t))); 604 tmp = (u32)fec_info[i].txbuf; 605 #else 606 fec_info[i].rxbd = 607 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 608 (PKTBUFSRX * sizeof(cbd_t))); 609 fec_info[i].txbd = 610 (cbd_t *) memalign(CFG_CACHELINE_SIZE, 611 (TX_BUF_CNT * sizeof(cbd_t))); 612 fec_info[i].txbuf = 613 (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); 614 #endif 615 616 #ifdef ET_DEBUG 617 printf("rxbd %x txbd %x\n", 618 (int)fec_info[i].rxbd, (int)fec_info[i].txbd); 619 #endif 620 621 fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); 622 623 eth_register(dev); 624 625 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 626 miiphy_register(dev->name, 627 mcffec_miiphy_read, mcffec_miiphy_write); 628 #endif 629 if (i > 0) 630 fec_info[i - 1].next = &fec_info[i]; 631 } 632 fec_info[i - 1].next = &fec_info[0]; 633 634 /* default speed */ 635 bis->bi_ethspeed = 10; 636 637 return 0; 638 } 639