1 /* 2 * Copyright (C) 2005-2006 Atmel Corporation 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <clk.h> 8 #include <dm.h> 9 10 /* 11 * The u-boot networking stack is a little weird. It seems like the 12 * networking core allocates receive buffers up front without any 13 * regard to the hardware that's supposed to actually receive those 14 * packets. 15 * 16 * The MACB receives packets into 128-byte receive buffers, so the 17 * buffers allocated by the core isn't very practical to use. We'll 18 * allocate our own, but we need one such buffer in case a packet 19 * wraps around the DMA ring so that we have to copy it. 20 * 21 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific 22 * configuration header. This way, the core allocates one RX buffer 23 * and one TX buffer, each of which can hold a ethernet packet of 24 * maximum size. 25 * 26 * For some reason, the networking core unconditionally specifies a 27 * 32-byte packet "alignment" (which really should be called 28 * "padding"). MACB shouldn't need that, but we'll refrain from any 29 * core modifications here... 30 */ 31 32 #include <net.h> 33 #ifndef CONFIG_DM_ETH 34 #include <netdev.h> 35 #endif 36 #include <malloc.h> 37 #include <miiphy.h> 38 39 #include <linux/mii.h> 40 #include <asm/io.h> 41 #include <asm/dma-mapping.h> 42 #include <asm/arch/clk.h> 43 #include <linux/errno.h> 44 45 #include "macb.h" 46 47 DECLARE_GLOBAL_DATA_PTR; 48 49 #define MACB_RX_BUFFER_SIZE 4096 50 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) 51 #define MACB_TX_RING_SIZE 16 52 #define MACB_TX_TIMEOUT 1000 53 #define MACB_AUTONEG_TIMEOUT 5000000 54 55 struct macb_dma_desc { 56 u32 addr; 57 u32 ctrl; 58 }; 59 60 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc)) 61 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE)) 62 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE)) 63 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1)) 64 65 #define RXADDR_USED 0x00000001 66 #define RXADDR_WRAP 0x00000002 67 68 #define RXBUF_FRMLEN_MASK 0x00000fff 69 #define RXBUF_FRAME_START 0x00004000 70 #define RXBUF_FRAME_END 0x00008000 71 #define RXBUF_TYPEID_MATCH 0x00400000 72 #define RXBUF_ADDR4_MATCH 0x00800000 73 #define RXBUF_ADDR3_MATCH 0x01000000 74 #define RXBUF_ADDR2_MATCH 0x02000000 75 #define RXBUF_ADDR1_MATCH 0x04000000 76 #define RXBUF_BROADCAST 0x80000000 77 78 #define TXBUF_FRMLEN_MASK 0x000007ff 79 #define TXBUF_FRAME_END 0x00008000 80 #define TXBUF_NOCRC 0x00010000 81 #define TXBUF_EXHAUSTED 0x08000000 82 #define TXBUF_UNDERRUN 0x10000000 83 #define TXBUF_MAXRETRY 0x20000000 84 #define TXBUF_WRAP 0x40000000 85 #define TXBUF_USED 0x80000000 86 87 struct macb_device { 88 void *regs; 89 90 unsigned int rx_tail; 91 unsigned int tx_head; 92 unsigned int tx_tail; 93 unsigned int next_rx_tail; 94 bool wrapped; 95 96 void *rx_buffer; 97 void *tx_buffer; 98 struct macb_dma_desc *rx_ring; 99 struct macb_dma_desc *tx_ring; 100 101 unsigned long rx_buffer_dma; 102 unsigned long rx_ring_dma; 103 unsigned long tx_ring_dma; 104 105 struct macb_dma_desc *dummy_desc; 106 unsigned long dummy_desc_dma; 107 108 const struct device *dev; 109 #ifndef CONFIG_DM_ETH 110 struct eth_device netdev; 111 #endif 112 unsigned short phy_addr; 113 struct mii_dev *bus; 114 #ifdef CONFIG_PHYLIB 115 struct phy_device *phydev; 116 #endif 117 118 #ifdef CONFIG_DM_ETH 119 #ifdef CONFIG_CLK 120 unsigned long pclk_rate; 121 #endif 122 phy_interface_t phy_interface; 123 #endif 124 }; 125 #ifndef CONFIG_DM_ETH 126 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev) 127 #endif 128 129 static int macb_is_gem(struct macb_device *macb) 130 { 131 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2; 132 } 133 134 #ifndef cpu_is_sama5d2 135 #define cpu_is_sama5d2() 0 136 #endif 137 138 #ifndef cpu_is_sama5d4 139 #define cpu_is_sama5d4() 0 140 #endif 141 142 static int gem_is_gigabit_capable(struct macb_device *macb) 143 { 144 /* 145 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are 146 * configured to support only 10/100. 147 */ 148 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4(); 149 } 150 151 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) 152 { 153 unsigned long netctl; 154 unsigned long netstat; 155 unsigned long frame; 156 157 netctl = macb_readl(macb, NCR); 158 netctl |= MACB_BIT(MPE); 159 macb_writel(macb, NCR, netctl); 160 161 frame = (MACB_BF(SOF, 1) 162 | MACB_BF(RW, 1) 163 | MACB_BF(PHYA, macb->phy_addr) 164 | MACB_BF(REGA, reg) 165 | MACB_BF(CODE, 2) 166 | MACB_BF(DATA, value)); 167 macb_writel(macb, MAN, frame); 168 169 do { 170 netstat = macb_readl(macb, NSR); 171 } while (!(netstat & MACB_BIT(IDLE))); 172 173 netctl = macb_readl(macb, NCR); 174 netctl &= ~MACB_BIT(MPE); 175 macb_writel(macb, NCR, netctl); 176 } 177 178 static u16 macb_mdio_read(struct macb_device *macb, u8 reg) 179 { 180 unsigned long netctl; 181 unsigned long netstat; 182 unsigned long frame; 183 184 netctl = macb_readl(macb, NCR); 185 netctl |= MACB_BIT(MPE); 186 macb_writel(macb, NCR, netctl); 187 188 frame = (MACB_BF(SOF, 1) 189 | MACB_BF(RW, 2) 190 | MACB_BF(PHYA, macb->phy_addr) 191 | MACB_BF(REGA, reg) 192 | MACB_BF(CODE, 2)); 193 macb_writel(macb, MAN, frame); 194 195 do { 196 netstat = macb_readl(macb, NSR); 197 } while (!(netstat & MACB_BIT(IDLE))); 198 199 frame = macb_readl(macb, MAN); 200 201 netctl = macb_readl(macb, NCR); 202 netctl &= ~MACB_BIT(MPE); 203 macb_writel(macb, NCR, netctl); 204 205 return MACB_BFEXT(DATA, frame); 206 } 207 208 void __weak arch_get_mdio_control(const char *name) 209 { 210 return; 211 } 212 213 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 214 215 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg) 216 { 217 u16 value = 0; 218 #ifdef CONFIG_DM_ETH 219 struct udevice *dev = eth_get_dev_by_name(bus->name); 220 struct macb_device *macb = dev_get_priv(dev); 221 #else 222 struct eth_device *dev = eth_get_dev_by_name(bus->name); 223 struct macb_device *macb = to_macb(dev); 224 #endif 225 226 if (macb->phy_addr != phy_adr) 227 return -1; 228 229 arch_get_mdio_control(bus->name); 230 value = macb_mdio_read(macb, reg); 231 232 return value; 233 } 234 235 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg, 236 u16 value) 237 { 238 #ifdef CONFIG_DM_ETH 239 struct udevice *dev = eth_get_dev_by_name(bus->name); 240 struct macb_device *macb = dev_get_priv(dev); 241 #else 242 struct eth_device *dev = eth_get_dev_by_name(bus->name); 243 struct macb_device *macb = to_macb(dev); 244 #endif 245 246 if (macb->phy_addr != phy_adr) 247 return -1; 248 249 arch_get_mdio_control(bus->name); 250 macb_mdio_write(macb, reg, value); 251 252 return 0; 253 } 254 #endif 255 256 #define RX 1 257 #define TX 0 258 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx) 259 { 260 if (rx) 261 invalidate_dcache_range(macb->rx_ring_dma, 262 ALIGN(macb->rx_ring_dma + MACB_RX_DMA_DESC_SIZE, 263 PKTALIGN)); 264 else 265 invalidate_dcache_range(macb->tx_ring_dma, 266 ALIGN(macb->tx_ring_dma + MACB_TX_DMA_DESC_SIZE, 267 PKTALIGN)); 268 } 269 270 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx) 271 { 272 if (rx) 273 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + 274 ALIGN(MACB_RX_DMA_DESC_SIZE, PKTALIGN)); 275 else 276 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + 277 ALIGN(MACB_TX_DMA_DESC_SIZE, PKTALIGN)); 278 } 279 280 static inline void macb_flush_rx_buffer(struct macb_device *macb) 281 { 282 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + 283 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN)); 284 } 285 286 static inline void macb_invalidate_rx_buffer(struct macb_device *macb) 287 { 288 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + 289 ALIGN(MACB_RX_BUFFER_SIZE, PKTALIGN)); 290 } 291 292 #if defined(CONFIG_CMD_NET) 293 294 static int _macb_send(struct macb_device *macb, const char *name, void *packet, 295 int length) 296 { 297 unsigned long paddr, ctrl; 298 unsigned int tx_head = macb->tx_head; 299 int i; 300 301 paddr = dma_map_single(packet, length, DMA_TO_DEVICE); 302 303 ctrl = length & TXBUF_FRMLEN_MASK; 304 ctrl |= TXBUF_FRAME_END; 305 if (tx_head == (MACB_TX_RING_SIZE - 1)) { 306 ctrl |= TXBUF_WRAP; 307 macb->tx_head = 0; 308 } else { 309 macb->tx_head++; 310 } 311 312 macb->tx_ring[tx_head].ctrl = ctrl; 313 macb->tx_ring[tx_head].addr = paddr; 314 barrier(); 315 macb_flush_ring_desc(macb, TX); 316 /* Do we need check paddr and length is dcache line aligned? */ 317 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN)); 318 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); 319 320 /* 321 * I guess this is necessary because the networking core may 322 * re-use the transmit buffer as soon as we return... 323 */ 324 for (i = 0; i <= MACB_TX_TIMEOUT; i++) { 325 barrier(); 326 macb_invalidate_ring_desc(macb, TX); 327 ctrl = macb->tx_ring[tx_head].ctrl; 328 if (ctrl & TXBUF_USED) 329 break; 330 udelay(1); 331 } 332 333 dma_unmap_single(packet, length, paddr); 334 335 if (i <= MACB_TX_TIMEOUT) { 336 if (ctrl & TXBUF_UNDERRUN) 337 printf("%s: TX underrun\n", name); 338 if (ctrl & TXBUF_EXHAUSTED) 339 printf("%s: TX buffers exhausted in mid frame\n", name); 340 } else { 341 printf("%s: TX timeout\n", name); 342 } 343 344 /* No one cares anyway */ 345 return 0; 346 } 347 348 static void reclaim_rx_buffers(struct macb_device *macb, 349 unsigned int new_tail) 350 { 351 unsigned int i; 352 353 i = macb->rx_tail; 354 355 macb_invalidate_ring_desc(macb, RX); 356 while (i > new_tail) { 357 macb->rx_ring[i].addr &= ~RXADDR_USED; 358 i++; 359 if (i > MACB_RX_RING_SIZE) 360 i = 0; 361 } 362 363 while (i < new_tail) { 364 macb->rx_ring[i].addr &= ~RXADDR_USED; 365 i++; 366 } 367 368 barrier(); 369 macb_flush_ring_desc(macb, RX); 370 macb->rx_tail = new_tail; 371 } 372 373 static int _macb_recv(struct macb_device *macb, uchar **packetp) 374 { 375 unsigned int next_rx_tail = macb->next_rx_tail; 376 void *buffer; 377 int length; 378 u32 status; 379 380 macb->wrapped = false; 381 for (;;) { 382 macb_invalidate_ring_desc(macb, RX); 383 384 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED)) 385 return -EAGAIN; 386 387 status = macb->rx_ring[next_rx_tail].ctrl; 388 if (status & RXBUF_FRAME_START) { 389 if (next_rx_tail != macb->rx_tail) 390 reclaim_rx_buffers(macb, next_rx_tail); 391 macb->wrapped = false; 392 } 393 394 if (status & RXBUF_FRAME_END) { 395 buffer = macb->rx_buffer + 128 * macb->rx_tail; 396 length = status & RXBUF_FRMLEN_MASK; 397 398 macb_invalidate_rx_buffer(macb); 399 if (macb->wrapped) { 400 unsigned int headlen, taillen; 401 402 headlen = 128 * (MACB_RX_RING_SIZE 403 - macb->rx_tail); 404 taillen = length - headlen; 405 memcpy((void *)net_rx_packets[0], 406 buffer, headlen); 407 memcpy((void *)net_rx_packets[0] + headlen, 408 macb->rx_buffer, taillen); 409 *packetp = (void *)net_rx_packets[0]; 410 } else { 411 *packetp = buffer; 412 } 413 414 if (++next_rx_tail >= MACB_RX_RING_SIZE) 415 next_rx_tail = 0; 416 macb->next_rx_tail = next_rx_tail; 417 return length; 418 } else { 419 if (++next_rx_tail >= MACB_RX_RING_SIZE) { 420 macb->wrapped = true; 421 next_rx_tail = 0; 422 } 423 } 424 barrier(); 425 } 426 } 427 428 static void macb_phy_reset(struct macb_device *macb, const char *name) 429 { 430 int i; 431 u16 status, adv; 432 433 adv = ADVERTISE_CSMA | ADVERTISE_ALL; 434 macb_mdio_write(macb, MII_ADVERTISE, adv); 435 printf("%s: Starting autonegotiation...\n", name); 436 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE 437 | BMCR_ANRESTART)); 438 439 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 440 status = macb_mdio_read(macb, MII_BMSR); 441 if (status & BMSR_ANEGCOMPLETE) 442 break; 443 udelay(100); 444 } 445 446 if (status & BMSR_ANEGCOMPLETE) 447 printf("%s: Autonegotiation complete\n", name); 448 else 449 printf("%s: Autonegotiation timed out (status=0x%04x)\n", 450 name, status); 451 } 452 453 #ifdef CONFIG_MACB_SEARCH_PHY 454 static int macb_phy_find(struct macb_device *macb, const char *name) 455 { 456 int i; 457 u16 phy_id; 458 459 /* Search for PHY... */ 460 for (i = 0; i < 32; i++) { 461 macb->phy_addr = i; 462 phy_id = macb_mdio_read(macb, MII_PHYSID1); 463 if (phy_id != 0xffff) { 464 printf("%s: PHY present at %d\n", name, i); 465 return 1; 466 } 467 } 468 469 /* PHY isn't up to snuff */ 470 printf("%s: PHY not found\n", name); 471 472 return 0; 473 } 474 #endif /* CONFIG_MACB_SEARCH_PHY */ 475 476 #ifdef CONFIG_DM_ETH 477 static int macb_phy_init(struct udevice *dev, const char *name) 478 #else 479 static int macb_phy_init(struct macb_device *macb, const char *name) 480 #endif 481 { 482 #ifdef CONFIG_DM_ETH 483 struct macb_device *macb = dev_get_priv(dev); 484 #endif 485 u32 ncfgr; 486 u16 phy_id, status, adv, lpa; 487 int media, speed, duplex; 488 int i; 489 490 arch_get_mdio_control(name); 491 #ifdef CONFIG_MACB_SEARCH_PHY 492 /* Auto-detect phy_addr */ 493 if (!macb_phy_find(macb, name)) 494 return 0; 495 #endif /* CONFIG_MACB_SEARCH_PHY */ 496 497 /* Check if the PHY is up to snuff... */ 498 phy_id = macb_mdio_read(macb, MII_PHYSID1); 499 if (phy_id == 0xffff) { 500 printf("%s: No PHY present\n", name); 501 return 0; 502 } 503 504 #ifdef CONFIG_PHYLIB 505 #ifdef CONFIG_DM_ETH 506 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev, 507 macb->phy_interface); 508 #else 509 /* need to consider other phy interface mode */ 510 macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev, 511 PHY_INTERFACE_MODE_RGMII); 512 #endif 513 if (!macb->phydev) { 514 printf("phy_connect failed\n"); 515 return -ENODEV; 516 } 517 518 phy_config(macb->phydev); 519 #endif 520 521 status = macb_mdio_read(macb, MII_BMSR); 522 if (!(status & BMSR_LSTATUS)) { 523 /* Try to re-negotiate if we don't have link already. */ 524 macb_phy_reset(macb, name); 525 526 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 527 status = macb_mdio_read(macb, MII_BMSR); 528 if (status & BMSR_LSTATUS) 529 break; 530 udelay(100); 531 } 532 } 533 534 if (!(status & BMSR_LSTATUS)) { 535 printf("%s: link down (status: 0x%04x)\n", 536 name, status); 537 return 0; 538 } 539 540 /* First check for GMAC and that it is GiB capable */ 541 if (gem_is_gigabit_capable(macb)) { 542 lpa = macb_mdio_read(macb, MII_STAT1000); 543 544 if (lpa & (LPA_1000FULL | LPA_1000HALF)) { 545 duplex = ((lpa & LPA_1000FULL) ? 1 : 0); 546 547 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n", 548 name, 549 duplex ? "full" : "half", 550 lpa); 551 552 ncfgr = macb_readl(macb, NCFGR); 553 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 554 ncfgr |= GEM_BIT(GBE); 555 556 if (duplex) 557 ncfgr |= MACB_BIT(FD); 558 559 macb_writel(macb, NCFGR, ncfgr); 560 561 return 1; 562 } 563 } 564 565 /* fall back for EMAC checking */ 566 adv = macb_mdio_read(macb, MII_ADVERTISE); 567 lpa = macb_mdio_read(macb, MII_LPA); 568 media = mii_nway_result(lpa & adv); 569 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) 570 ? 1 : 0); 571 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 572 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", 573 name, 574 speed ? "100" : "10", 575 duplex ? "full" : "half", 576 lpa); 577 578 ncfgr = macb_readl(macb, NCFGR); 579 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE)); 580 if (speed) 581 ncfgr |= MACB_BIT(SPD); 582 if (duplex) 583 ncfgr |= MACB_BIT(FD); 584 macb_writel(macb, NCFGR, ncfgr); 585 586 return 1; 587 } 588 589 static int gmac_init_multi_queues(struct macb_device *macb) 590 { 591 int i, num_queues = 1; 592 u32 queue_mask; 593 594 /* bit 0 is never set but queue 0 always exists */ 595 queue_mask = gem_readl(macb, DCFG6) & 0xff; 596 queue_mask |= 0x1; 597 598 for (i = 1; i < MACB_MAX_QUEUES; i++) 599 if (queue_mask & (1 << i)) 600 num_queues++; 601 602 macb->dummy_desc->ctrl = TXBUF_USED; 603 macb->dummy_desc->addr = 0; 604 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma + 605 ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN)); 606 607 for (i = 1; i < num_queues; i++) 608 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1); 609 610 return 0; 611 } 612 613 #ifdef CONFIG_DM_ETH 614 static int _macb_init(struct udevice *dev, const char *name) 615 #else 616 static int _macb_init(struct macb_device *macb, const char *name) 617 #endif 618 { 619 #ifdef CONFIG_DM_ETH 620 struct macb_device *macb = dev_get_priv(dev); 621 #endif 622 unsigned long paddr; 623 int i; 624 625 /* 626 * macb_halt should have been called at some point before now, 627 * so we'll assume the controller is idle. 628 */ 629 630 /* initialize DMA descriptors */ 631 paddr = macb->rx_buffer_dma; 632 for (i = 0; i < MACB_RX_RING_SIZE; i++) { 633 if (i == (MACB_RX_RING_SIZE - 1)) 634 paddr |= RXADDR_WRAP; 635 macb->rx_ring[i].addr = paddr; 636 macb->rx_ring[i].ctrl = 0; 637 paddr += 128; 638 } 639 macb_flush_ring_desc(macb, RX); 640 macb_flush_rx_buffer(macb); 641 642 for (i = 0; i < MACB_TX_RING_SIZE; i++) { 643 macb->tx_ring[i].addr = 0; 644 if (i == (MACB_TX_RING_SIZE - 1)) 645 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; 646 else 647 macb->tx_ring[i].ctrl = TXBUF_USED; 648 } 649 macb_flush_ring_desc(macb, TX); 650 651 macb->rx_tail = 0; 652 macb->tx_head = 0; 653 macb->tx_tail = 0; 654 macb->next_rx_tail = 0; 655 656 macb_writel(macb, RBQP, macb->rx_ring_dma); 657 macb_writel(macb, TBQP, macb->tx_ring_dma); 658 659 if (macb_is_gem(macb)) { 660 /* Check the multi queue and initialize the queue for tx */ 661 gmac_init_multi_queues(macb); 662 663 /* 664 * When the GMAC IP with GE feature, this bit is used to 665 * select interface between RGMII and GMII. 666 * When the GMAC IP without GE feature, this bit is used 667 * to select interface between RMII and MII. 668 */ 669 #ifdef CONFIG_DM_ETH 670 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) 671 gem_writel(macb, UR, GEM_BIT(RGMII)); 672 else 673 gem_writel(macb, UR, 0); 674 #else 675 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII) 676 gem_writel(macb, UR, GEM_BIT(RGMII)); 677 #else 678 gem_writel(macb, UR, 0); 679 #endif 680 #endif 681 } else { 682 /* choose RMII or MII mode. This depends on the board */ 683 #ifdef CONFIG_DM_ETH 684 #ifdef CONFIG_AT91FAMILY 685 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) { 686 macb_writel(macb, USRIO, 687 MACB_BIT(RMII) | MACB_BIT(CLKEN)); 688 } else { 689 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 690 } 691 #else 692 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) 693 macb_writel(macb, USRIO, 0); 694 else 695 macb_writel(macb, USRIO, MACB_BIT(MII)); 696 #endif 697 #else 698 #ifdef CONFIG_RMII 699 #ifdef CONFIG_AT91FAMILY 700 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); 701 #else 702 macb_writel(macb, USRIO, 0); 703 #endif 704 #else 705 #ifdef CONFIG_AT91FAMILY 706 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 707 #else 708 macb_writel(macb, USRIO, MACB_BIT(MII)); 709 #endif 710 #endif /* CONFIG_RMII */ 711 #endif 712 } 713 714 #ifdef CONFIG_DM_ETH 715 if (!macb_phy_init(dev, name)) 716 #else 717 if (!macb_phy_init(macb, name)) 718 #endif 719 return -1; 720 721 /* Enable TX and RX */ 722 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); 723 724 return 0; 725 } 726 727 static void _macb_halt(struct macb_device *macb) 728 { 729 u32 ncr, tsr; 730 731 /* Halt the controller and wait for any ongoing transmission to end. */ 732 ncr = macb_readl(macb, NCR); 733 ncr |= MACB_BIT(THALT); 734 macb_writel(macb, NCR, ncr); 735 736 do { 737 tsr = macb_readl(macb, TSR); 738 } while (tsr & MACB_BIT(TGO)); 739 740 /* Disable TX and RX, and clear statistics */ 741 macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); 742 } 743 744 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr) 745 { 746 u32 hwaddr_bottom; 747 u16 hwaddr_top; 748 749 /* set hardware address */ 750 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 | 751 enetaddr[2] << 16 | enetaddr[3] << 24; 752 macb_writel(macb, SA1B, hwaddr_bottom); 753 hwaddr_top = enetaddr[4] | enetaddr[5] << 8; 754 macb_writel(macb, SA1T, hwaddr_top); 755 return 0; 756 } 757 758 static u32 macb_mdc_clk_div(int id, struct macb_device *macb) 759 { 760 u32 config; 761 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK) 762 unsigned long macb_hz = macb->pclk_rate; 763 #else 764 unsigned long macb_hz = get_macb_pclk_rate(id); 765 #endif 766 767 if (macb_hz < 20000000) 768 config = MACB_BF(CLK, MACB_CLK_DIV8); 769 else if (macb_hz < 40000000) 770 config = MACB_BF(CLK, MACB_CLK_DIV16); 771 else if (macb_hz < 80000000) 772 config = MACB_BF(CLK, MACB_CLK_DIV32); 773 else 774 config = MACB_BF(CLK, MACB_CLK_DIV64); 775 776 return config; 777 } 778 779 static u32 gem_mdc_clk_div(int id, struct macb_device *macb) 780 { 781 u32 config; 782 783 #if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK) 784 unsigned long macb_hz = macb->pclk_rate; 785 #else 786 unsigned long macb_hz = get_macb_pclk_rate(id); 787 #endif 788 789 if (macb_hz < 20000000) 790 config = GEM_BF(CLK, GEM_CLK_DIV8); 791 else if (macb_hz < 40000000) 792 config = GEM_BF(CLK, GEM_CLK_DIV16); 793 else if (macb_hz < 80000000) 794 config = GEM_BF(CLK, GEM_CLK_DIV32); 795 else if (macb_hz < 120000000) 796 config = GEM_BF(CLK, GEM_CLK_DIV48); 797 else if (macb_hz < 160000000) 798 config = GEM_BF(CLK, GEM_CLK_DIV64); 799 else 800 config = GEM_BF(CLK, GEM_CLK_DIV96); 801 802 return config; 803 } 804 805 /* 806 * Get the DMA bus width field of the network configuration register that we 807 * should program. We find the width from decoding the design configuration 808 * register to find the maximum supported data bus width. 809 */ 810 static u32 macb_dbw(struct macb_device *macb) 811 { 812 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) { 813 case 4: 814 return GEM_BF(DBW, GEM_DBW128); 815 case 2: 816 return GEM_BF(DBW, GEM_DBW64); 817 case 1: 818 default: 819 return GEM_BF(DBW, GEM_DBW32); 820 } 821 } 822 823 static void _macb_eth_initialize(struct macb_device *macb) 824 { 825 int id = 0; /* This is not used by functions we call */ 826 u32 ncfgr; 827 828 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */ 829 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE, 830 &macb->rx_buffer_dma); 831 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE, 832 &macb->rx_ring_dma); 833 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE, 834 &macb->tx_ring_dma); 835 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE, 836 &macb->dummy_desc_dma); 837 838 /* 839 * Do some basic initialization so that we at least can talk 840 * to the PHY 841 */ 842 if (macb_is_gem(macb)) { 843 ncfgr = gem_mdc_clk_div(id, macb); 844 ncfgr |= macb_dbw(macb); 845 } else { 846 ncfgr = macb_mdc_clk_div(id, macb); 847 } 848 849 macb_writel(macb, NCFGR, ncfgr); 850 } 851 852 #ifndef CONFIG_DM_ETH 853 static int macb_send(struct eth_device *netdev, void *packet, int length) 854 { 855 struct macb_device *macb = to_macb(netdev); 856 857 return _macb_send(macb, netdev->name, packet, length); 858 } 859 860 static int macb_recv(struct eth_device *netdev) 861 { 862 struct macb_device *macb = to_macb(netdev); 863 uchar *packet; 864 int length; 865 866 macb->wrapped = false; 867 for (;;) { 868 macb->next_rx_tail = macb->rx_tail; 869 length = _macb_recv(macb, &packet); 870 if (length >= 0) { 871 net_process_received_packet(packet, length); 872 reclaim_rx_buffers(macb, macb->next_rx_tail); 873 } else if (length < 0) { 874 return length; 875 } 876 } 877 } 878 879 static int macb_init(struct eth_device *netdev, bd_t *bd) 880 { 881 struct macb_device *macb = to_macb(netdev); 882 883 return _macb_init(macb, netdev->name); 884 } 885 886 static void macb_halt(struct eth_device *netdev) 887 { 888 struct macb_device *macb = to_macb(netdev); 889 890 return _macb_halt(macb); 891 } 892 893 static int macb_write_hwaddr(struct eth_device *netdev) 894 { 895 struct macb_device *macb = to_macb(netdev); 896 897 return _macb_write_hwaddr(macb, netdev->enetaddr); 898 } 899 900 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) 901 { 902 struct macb_device *macb; 903 struct eth_device *netdev; 904 905 macb = malloc(sizeof(struct macb_device)); 906 if (!macb) { 907 printf("Error: Failed to allocate memory for MACB%d\n", id); 908 return -1; 909 } 910 memset(macb, 0, sizeof(struct macb_device)); 911 912 netdev = &macb->netdev; 913 914 macb->regs = regs; 915 macb->phy_addr = phy_addr; 916 917 if (macb_is_gem(macb)) 918 sprintf(netdev->name, "gmac%d", id); 919 else 920 sprintf(netdev->name, "macb%d", id); 921 922 netdev->init = macb_init; 923 netdev->halt = macb_halt; 924 netdev->send = macb_send; 925 netdev->recv = macb_recv; 926 netdev->write_hwaddr = macb_write_hwaddr; 927 928 _macb_eth_initialize(macb); 929 930 eth_register(netdev); 931 932 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 933 int retval; 934 struct mii_dev *mdiodev = mdio_alloc(); 935 if (!mdiodev) 936 return -ENOMEM; 937 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN); 938 mdiodev->read = macb_miiphy_read; 939 mdiodev->write = macb_miiphy_write; 940 941 retval = mdio_register(mdiodev); 942 if (retval < 0) 943 return retval; 944 macb->bus = miiphy_get_dev_by_name(netdev->name); 945 #endif 946 return 0; 947 } 948 #endif /* !CONFIG_DM_ETH */ 949 950 #ifdef CONFIG_DM_ETH 951 952 static int macb_start(struct udevice *dev) 953 { 954 return _macb_init(dev, dev->name); 955 } 956 957 static int macb_send(struct udevice *dev, void *packet, int length) 958 { 959 struct macb_device *macb = dev_get_priv(dev); 960 961 return _macb_send(macb, dev->name, packet, length); 962 } 963 964 static int macb_recv(struct udevice *dev, int flags, uchar **packetp) 965 { 966 struct macb_device *macb = dev_get_priv(dev); 967 968 macb->next_rx_tail = macb->rx_tail; 969 macb->wrapped = false; 970 971 return _macb_recv(macb, packetp); 972 } 973 974 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length) 975 { 976 struct macb_device *macb = dev_get_priv(dev); 977 978 reclaim_rx_buffers(macb, macb->next_rx_tail); 979 980 return 0; 981 } 982 983 static void macb_stop(struct udevice *dev) 984 { 985 struct macb_device *macb = dev_get_priv(dev); 986 987 _macb_halt(macb); 988 } 989 990 static int macb_write_hwaddr(struct udevice *dev) 991 { 992 struct eth_pdata *plat = dev_get_platdata(dev); 993 struct macb_device *macb = dev_get_priv(dev); 994 995 return _macb_write_hwaddr(macb, plat->enetaddr); 996 } 997 998 static const struct eth_ops macb_eth_ops = { 999 .start = macb_start, 1000 .send = macb_send, 1001 .recv = macb_recv, 1002 .stop = macb_stop, 1003 .free_pkt = macb_free_pkt, 1004 .write_hwaddr = macb_write_hwaddr, 1005 }; 1006 1007 #ifdef CONFIG_CLK 1008 static int macb_enable_clk(struct udevice *dev) 1009 { 1010 struct macb_device *macb = dev_get_priv(dev); 1011 struct clk clk; 1012 ulong clk_rate; 1013 int ret; 1014 1015 ret = clk_get_by_index(dev, 0, &clk); 1016 if (ret) 1017 return -EINVAL; 1018 1019 ret = clk_enable(&clk); 1020 if (ret) 1021 return ret; 1022 1023 clk_rate = clk_get_rate(&clk); 1024 if (!clk_rate) 1025 return -EINVAL; 1026 1027 macb->pclk_rate = clk_rate; 1028 1029 return 0; 1030 } 1031 #endif 1032 1033 static int macb_eth_probe(struct udevice *dev) 1034 { 1035 struct eth_pdata *pdata = dev_get_platdata(dev); 1036 struct macb_device *macb = dev_get_priv(dev); 1037 const char *phy_mode; 1038 __maybe_unused int ret; 1039 1040 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", 1041 NULL); 1042 if (phy_mode) 1043 macb->phy_interface = phy_get_interface_by_name(phy_mode); 1044 if (macb->phy_interface == -1) { 1045 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 1046 return -EINVAL; 1047 } 1048 1049 macb->regs = (void *)pdata->iobase; 1050 1051 #ifdef CONFIG_CLK 1052 ret = macb_enable_clk(dev); 1053 if (ret) 1054 return ret; 1055 #endif 1056 1057 _macb_eth_initialize(macb); 1058 1059 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 1060 macb->bus = mdio_alloc(); 1061 if (!macb->bus) 1062 return -ENOMEM; 1063 strncpy(macb->bus->name, dev->name, MDIO_NAME_LEN); 1064 macb->bus->read = macb_miiphy_read; 1065 macb->bus->write = macb_miiphy_write; 1066 1067 ret = mdio_register(macb->bus); 1068 if (ret < 0) 1069 return ret; 1070 macb->bus = miiphy_get_dev_by_name(dev->name); 1071 #endif 1072 1073 return 0; 1074 } 1075 1076 static int macb_eth_remove(struct udevice *dev) 1077 { 1078 struct macb_device *macb = dev_get_priv(dev); 1079 1080 #ifdef CONFIG_PHYLIB 1081 free(macb->phydev); 1082 #endif 1083 mdio_unregister(macb->bus); 1084 mdio_free(macb->bus); 1085 1086 return 0; 1087 } 1088 1089 static int macb_eth_ofdata_to_platdata(struct udevice *dev) 1090 { 1091 struct eth_pdata *pdata = dev_get_platdata(dev); 1092 1093 pdata->iobase = dev_get_addr(dev); 1094 return 0; 1095 } 1096 1097 static const struct udevice_id macb_eth_ids[] = { 1098 { .compatible = "cdns,macb" }, 1099 { .compatible = "cdns,at91sam9260-macb" }, 1100 { .compatible = "atmel,sama5d2-gem" }, 1101 { .compatible = "atmel,sama5d3-gem" }, 1102 { .compatible = "atmel,sama5d4-gem" }, 1103 { } 1104 }; 1105 1106 U_BOOT_DRIVER(eth_macb) = { 1107 .name = "eth_macb", 1108 .id = UCLASS_ETH, 1109 .of_match = macb_eth_ids, 1110 .ofdata_to_platdata = macb_eth_ofdata_to_platdata, 1111 .probe = macb_eth_probe, 1112 .remove = macb_eth_remove, 1113 .ops = &macb_eth_ops, 1114 .priv_auto_alloc_size = sizeof(struct macb_device), 1115 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1116 }; 1117 #endif 1118 1119 #endif 1120