1 /* 2 * Copyright (C) 2005-2006 Atmel Corporation 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 #include <common.h> 7 #include <dm.h> 8 9 /* 10 * The u-boot networking stack is a little weird. It seems like the 11 * networking core allocates receive buffers up front without any 12 * regard to the hardware that's supposed to actually receive those 13 * packets. 14 * 15 * The MACB receives packets into 128-byte receive buffers, so the 16 * buffers allocated by the core isn't very practical to use. We'll 17 * allocate our own, but we need one such buffer in case a packet 18 * wraps around the DMA ring so that we have to copy it. 19 * 20 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific 21 * configuration header. This way, the core allocates one RX buffer 22 * and one TX buffer, each of which can hold a ethernet packet of 23 * maximum size. 24 * 25 * For some reason, the networking core unconditionally specifies a 26 * 32-byte packet "alignment" (which really should be called 27 * "padding"). MACB shouldn't need that, but we'll refrain from any 28 * core modifications here... 29 */ 30 31 #include <net.h> 32 #ifndef CONFIG_DM_ETH 33 #include <netdev.h> 34 #endif 35 #include <malloc.h> 36 #include <miiphy.h> 37 38 #include <linux/mii.h> 39 #include <asm/io.h> 40 #include <asm/dma-mapping.h> 41 #include <asm/arch/clk.h> 42 #include <linux/errno.h> 43 44 #include "macb.h" 45 46 DECLARE_GLOBAL_DATA_PTR; 47 48 #define MACB_RX_BUFFER_SIZE 4096 49 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) 50 #define MACB_TX_RING_SIZE 16 51 #define MACB_TX_TIMEOUT 1000 52 #define MACB_AUTONEG_TIMEOUT 5000000 53 54 struct macb_dma_desc { 55 u32 addr; 56 u32 ctrl; 57 }; 58 59 #define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc)) 60 #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE)) 61 #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE)) 62 #define MACB_TX_DUMMY_DMA_DESC_SIZE (DMA_DESC_BYTES(1)) 63 64 #define RXADDR_USED 0x00000001 65 #define RXADDR_WRAP 0x00000002 66 67 #define RXBUF_FRMLEN_MASK 0x00000fff 68 #define RXBUF_FRAME_START 0x00004000 69 #define RXBUF_FRAME_END 0x00008000 70 #define RXBUF_TYPEID_MATCH 0x00400000 71 #define RXBUF_ADDR4_MATCH 0x00800000 72 #define RXBUF_ADDR3_MATCH 0x01000000 73 #define RXBUF_ADDR2_MATCH 0x02000000 74 #define RXBUF_ADDR1_MATCH 0x04000000 75 #define RXBUF_BROADCAST 0x80000000 76 77 #define TXBUF_FRMLEN_MASK 0x000007ff 78 #define TXBUF_FRAME_END 0x00008000 79 #define TXBUF_NOCRC 0x00010000 80 #define TXBUF_EXHAUSTED 0x08000000 81 #define TXBUF_UNDERRUN 0x10000000 82 #define TXBUF_MAXRETRY 0x20000000 83 #define TXBUF_WRAP 0x40000000 84 #define TXBUF_USED 0x80000000 85 86 struct macb_device { 87 void *regs; 88 89 unsigned int rx_tail; 90 unsigned int tx_head; 91 unsigned int tx_tail; 92 unsigned int next_rx_tail; 93 bool wrapped; 94 95 void *rx_buffer; 96 void *tx_buffer; 97 struct macb_dma_desc *rx_ring; 98 struct macb_dma_desc *tx_ring; 99 100 unsigned long rx_buffer_dma; 101 unsigned long rx_ring_dma; 102 unsigned long tx_ring_dma; 103 104 struct macb_dma_desc *dummy_desc; 105 unsigned long dummy_desc_dma; 106 107 const struct device *dev; 108 #ifndef CONFIG_DM_ETH 109 struct eth_device netdev; 110 #endif 111 unsigned short phy_addr; 112 struct mii_dev *bus; 113 114 #ifdef CONFIG_DM_ETH 115 phy_interface_t phy_interface; 116 #endif 117 }; 118 #ifndef CONFIG_DM_ETH 119 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev) 120 #endif 121 122 static int macb_is_gem(struct macb_device *macb) 123 { 124 return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2; 125 } 126 127 #ifndef cpu_is_sama5d2 128 #define cpu_is_sama5d2() 0 129 #endif 130 131 #ifndef cpu_is_sama5d4 132 #define cpu_is_sama5d4() 0 133 #endif 134 135 static int gem_is_gigabit_capable(struct macb_device *macb) 136 { 137 /* 138 * The GEM controllers embedded in SAMA5D2 and SAMA5D4 are 139 * configured to support only 10/100. 140 */ 141 return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4(); 142 } 143 144 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) 145 { 146 unsigned long netctl; 147 unsigned long netstat; 148 unsigned long frame; 149 150 netctl = macb_readl(macb, NCR); 151 netctl |= MACB_BIT(MPE); 152 macb_writel(macb, NCR, netctl); 153 154 frame = (MACB_BF(SOF, 1) 155 | MACB_BF(RW, 1) 156 | MACB_BF(PHYA, macb->phy_addr) 157 | MACB_BF(REGA, reg) 158 | MACB_BF(CODE, 2) 159 | MACB_BF(DATA, value)); 160 macb_writel(macb, MAN, frame); 161 162 do { 163 netstat = macb_readl(macb, NSR); 164 } while (!(netstat & MACB_BIT(IDLE))); 165 166 netctl = macb_readl(macb, NCR); 167 netctl &= ~MACB_BIT(MPE); 168 macb_writel(macb, NCR, netctl); 169 } 170 171 static u16 macb_mdio_read(struct macb_device *macb, u8 reg) 172 { 173 unsigned long netctl; 174 unsigned long netstat; 175 unsigned long frame; 176 177 netctl = macb_readl(macb, NCR); 178 netctl |= MACB_BIT(MPE); 179 macb_writel(macb, NCR, netctl); 180 181 frame = (MACB_BF(SOF, 1) 182 | MACB_BF(RW, 2) 183 | MACB_BF(PHYA, macb->phy_addr) 184 | MACB_BF(REGA, reg) 185 | MACB_BF(CODE, 2)); 186 macb_writel(macb, MAN, frame); 187 188 do { 189 netstat = macb_readl(macb, NSR); 190 } while (!(netstat & MACB_BIT(IDLE))); 191 192 frame = macb_readl(macb, MAN); 193 194 netctl = macb_readl(macb, NCR); 195 netctl &= ~MACB_BIT(MPE); 196 macb_writel(macb, NCR, netctl); 197 198 return MACB_BFEXT(DATA, frame); 199 } 200 201 void __weak arch_get_mdio_control(const char *name) 202 { 203 return; 204 } 205 206 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 207 208 int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg) 209 { 210 u16 value = 0; 211 #ifdef CONFIG_DM_ETH 212 struct udevice *dev = eth_get_dev_by_name(bus->name); 213 struct macb_device *macb = dev_get_priv(dev); 214 #else 215 struct eth_device *dev = eth_get_dev_by_name(bus->name); 216 struct macb_device *macb = to_macb(dev); 217 #endif 218 219 if (macb->phy_addr != phy_adr) 220 return -1; 221 222 arch_get_mdio_control(bus->name); 223 value = macb_mdio_read(macb, reg); 224 225 return value; 226 } 227 228 int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg, 229 u16 value) 230 { 231 #ifdef CONFIG_DM_ETH 232 struct udevice *dev = eth_get_dev_by_name(bus->name); 233 struct macb_device *macb = dev_get_priv(dev); 234 #else 235 struct eth_device *dev = eth_get_dev_by_name(bus->name); 236 struct macb_device *macb = to_macb(dev); 237 #endif 238 239 if (macb->phy_addr != phy_adr) 240 return -1; 241 242 arch_get_mdio_control(bus->name); 243 macb_mdio_write(macb, reg, value); 244 245 return 0; 246 } 247 #endif 248 249 #define RX 1 250 #define TX 0 251 static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx) 252 { 253 if (rx) 254 invalidate_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + 255 MACB_RX_DMA_DESC_SIZE); 256 else 257 invalidate_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + 258 MACB_TX_DMA_DESC_SIZE); 259 } 260 261 static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx) 262 { 263 if (rx) 264 flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma + 265 MACB_RX_DMA_DESC_SIZE); 266 else 267 flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma + 268 MACB_TX_DMA_DESC_SIZE); 269 } 270 271 static inline void macb_flush_rx_buffer(struct macb_device *macb) 272 { 273 flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + 274 MACB_RX_BUFFER_SIZE); 275 } 276 277 static inline void macb_invalidate_rx_buffer(struct macb_device *macb) 278 { 279 invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma + 280 MACB_RX_BUFFER_SIZE); 281 } 282 283 #if defined(CONFIG_CMD_NET) 284 285 static int _macb_send(struct macb_device *macb, const char *name, void *packet, 286 int length) 287 { 288 unsigned long paddr, ctrl; 289 unsigned int tx_head = macb->tx_head; 290 int i; 291 292 paddr = dma_map_single(packet, length, DMA_TO_DEVICE); 293 294 ctrl = length & TXBUF_FRMLEN_MASK; 295 ctrl |= TXBUF_FRAME_END; 296 if (tx_head == (MACB_TX_RING_SIZE - 1)) { 297 ctrl |= TXBUF_WRAP; 298 macb->tx_head = 0; 299 } else { 300 macb->tx_head++; 301 } 302 303 macb->tx_ring[tx_head].ctrl = ctrl; 304 macb->tx_ring[tx_head].addr = paddr; 305 barrier(); 306 macb_flush_ring_desc(macb, TX); 307 /* Do we need check paddr and length is dcache line aligned? */ 308 flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN)); 309 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); 310 311 /* 312 * I guess this is necessary because the networking core may 313 * re-use the transmit buffer as soon as we return... 314 */ 315 for (i = 0; i <= MACB_TX_TIMEOUT; i++) { 316 barrier(); 317 macb_invalidate_ring_desc(macb, TX); 318 ctrl = macb->tx_ring[tx_head].ctrl; 319 if (ctrl & TXBUF_USED) 320 break; 321 udelay(1); 322 } 323 324 dma_unmap_single(packet, length, paddr); 325 326 if (i <= MACB_TX_TIMEOUT) { 327 if (ctrl & TXBUF_UNDERRUN) 328 printf("%s: TX underrun\n", name); 329 if (ctrl & TXBUF_EXHAUSTED) 330 printf("%s: TX buffers exhausted in mid frame\n", name); 331 } else { 332 printf("%s: TX timeout\n", name); 333 } 334 335 /* No one cares anyway */ 336 return 0; 337 } 338 339 static void reclaim_rx_buffers(struct macb_device *macb, 340 unsigned int new_tail) 341 { 342 unsigned int i; 343 344 i = macb->rx_tail; 345 346 macb_invalidate_ring_desc(macb, RX); 347 while (i > new_tail) { 348 macb->rx_ring[i].addr &= ~RXADDR_USED; 349 i++; 350 if (i > MACB_RX_RING_SIZE) 351 i = 0; 352 } 353 354 while (i < new_tail) { 355 macb->rx_ring[i].addr &= ~RXADDR_USED; 356 i++; 357 } 358 359 barrier(); 360 macb_flush_ring_desc(macb, RX); 361 macb->rx_tail = new_tail; 362 } 363 364 static int _macb_recv(struct macb_device *macb, uchar **packetp) 365 { 366 unsigned int next_rx_tail = macb->next_rx_tail; 367 void *buffer; 368 int length; 369 u32 status; 370 371 macb->wrapped = false; 372 for (;;) { 373 macb_invalidate_ring_desc(macb, RX); 374 375 if (!(macb->rx_ring[next_rx_tail].addr & RXADDR_USED)) 376 return -EAGAIN; 377 378 status = macb->rx_ring[next_rx_tail].ctrl; 379 if (status & RXBUF_FRAME_START) { 380 if (next_rx_tail != macb->rx_tail) 381 reclaim_rx_buffers(macb, next_rx_tail); 382 macb->wrapped = false; 383 } 384 385 if (status & RXBUF_FRAME_END) { 386 buffer = macb->rx_buffer + 128 * macb->rx_tail; 387 length = status & RXBUF_FRMLEN_MASK; 388 389 macb_invalidate_rx_buffer(macb); 390 if (macb->wrapped) { 391 unsigned int headlen, taillen; 392 393 headlen = 128 * (MACB_RX_RING_SIZE 394 - macb->rx_tail); 395 taillen = length - headlen; 396 memcpy((void *)net_rx_packets[0], 397 buffer, headlen); 398 memcpy((void *)net_rx_packets[0] + headlen, 399 macb->rx_buffer, taillen); 400 *packetp = (void *)net_rx_packets[0]; 401 } else { 402 *packetp = buffer; 403 } 404 405 if (++next_rx_tail >= MACB_RX_RING_SIZE) 406 next_rx_tail = 0; 407 macb->next_rx_tail = next_rx_tail; 408 return length; 409 } else { 410 if (++next_rx_tail >= MACB_RX_RING_SIZE) { 411 macb->wrapped = true; 412 next_rx_tail = 0; 413 } 414 } 415 barrier(); 416 } 417 } 418 419 static void macb_phy_reset(struct macb_device *macb, const char *name) 420 { 421 int i; 422 u16 status, adv; 423 424 adv = ADVERTISE_CSMA | ADVERTISE_ALL; 425 macb_mdio_write(macb, MII_ADVERTISE, adv); 426 printf("%s: Starting autonegotiation...\n", name); 427 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE 428 | BMCR_ANRESTART)); 429 430 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 431 status = macb_mdio_read(macb, MII_BMSR); 432 if (status & BMSR_ANEGCOMPLETE) 433 break; 434 udelay(100); 435 } 436 437 if (status & BMSR_ANEGCOMPLETE) 438 printf("%s: Autonegotiation complete\n", name); 439 else 440 printf("%s: Autonegotiation timed out (status=0x%04x)\n", 441 name, status); 442 } 443 444 #ifdef CONFIG_MACB_SEARCH_PHY 445 static int macb_phy_find(struct macb_device *macb, const char *name) 446 { 447 int i; 448 u16 phy_id; 449 450 /* Search for PHY... */ 451 for (i = 0; i < 32; i++) { 452 macb->phy_addr = i; 453 phy_id = macb_mdio_read(macb, MII_PHYSID1); 454 if (phy_id != 0xffff) { 455 printf("%s: PHY present at %d\n", name, i); 456 return 1; 457 } 458 } 459 460 /* PHY isn't up to snuff */ 461 printf("%s: PHY not found\n", name); 462 463 return 0; 464 } 465 #endif /* CONFIG_MACB_SEARCH_PHY */ 466 467 #ifdef CONFIG_DM_ETH 468 static int macb_phy_init(struct udevice *dev, const char *name) 469 #else 470 static int macb_phy_init(struct macb_device *macb, const char *name) 471 #endif 472 { 473 #ifdef CONFIG_DM_ETH 474 struct macb_device *macb = dev_get_priv(dev); 475 #endif 476 #ifdef CONFIG_PHYLIB 477 struct phy_device *phydev; 478 #endif 479 u32 ncfgr; 480 u16 phy_id, status, adv, lpa; 481 int media, speed, duplex; 482 int i; 483 484 arch_get_mdio_control(name); 485 #ifdef CONFIG_MACB_SEARCH_PHY 486 /* Auto-detect phy_addr */ 487 if (!macb_phy_find(macb, name)) 488 return 0; 489 #endif /* CONFIG_MACB_SEARCH_PHY */ 490 491 /* Check if the PHY is up to snuff... */ 492 phy_id = macb_mdio_read(macb, MII_PHYSID1); 493 if (phy_id == 0xffff) { 494 printf("%s: No PHY present\n", name); 495 return 0; 496 } 497 498 #ifdef CONFIG_PHYLIB 499 #ifdef CONFIG_DM_ETH 500 phydev = phy_connect(macb->bus, macb->phy_addr, dev, 501 macb->phy_interface); 502 #else 503 /* need to consider other phy interface mode */ 504 phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev, 505 PHY_INTERFACE_MODE_RGMII); 506 #endif 507 if (!phydev) { 508 printf("phy_connect failed\n"); 509 return -ENODEV; 510 } 511 512 phy_config(phydev); 513 #endif 514 515 status = macb_mdio_read(macb, MII_BMSR); 516 if (!(status & BMSR_LSTATUS)) { 517 /* Try to re-negotiate if we don't have link already. */ 518 macb_phy_reset(macb, name); 519 520 for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) { 521 status = macb_mdio_read(macb, MII_BMSR); 522 if (status & BMSR_LSTATUS) 523 break; 524 udelay(100); 525 } 526 } 527 528 if (!(status & BMSR_LSTATUS)) { 529 printf("%s: link down (status: 0x%04x)\n", 530 name, status); 531 return 0; 532 } 533 534 /* First check for GMAC and that it is GiB capable */ 535 if (gem_is_gigabit_capable(macb)) { 536 lpa = macb_mdio_read(macb, MII_STAT1000); 537 538 if (lpa & (LPA_1000FULL | LPA_1000HALF)) { 539 duplex = ((lpa & LPA_1000FULL) ? 1 : 0); 540 541 printf("%s: link up, 1000Mbps %s-duplex (lpa: 0x%04x)\n", 542 name, 543 duplex ? "full" : "half", 544 lpa); 545 546 ncfgr = macb_readl(macb, NCFGR); 547 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 548 ncfgr |= GEM_BIT(GBE); 549 550 if (duplex) 551 ncfgr |= MACB_BIT(FD); 552 553 macb_writel(macb, NCFGR, ncfgr); 554 555 return 1; 556 } 557 } 558 559 /* fall back for EMAC checking */ 560 adv = macb_mdio_read(macb, MII_ADVERTISE); 561 lpa = macb_mdio_read(macb, MII_LPA); 562 media = mii_nway_result(lpa & adv); 563 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) 564 ? 1 : 0); 565 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 566 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", 567 name, 568 speed ? "100" : "10", 569 duplex ? "full" : "half", 570 lpa); 571 572 ncfgr = macb_readl(macb, NCFGR); 573 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE)); 574 if (speed) 575 ncfgr |= MACB_BIT(SPD); 576 if (duplex) 577 ncfgr |= MACB_BIT(FD); 578 macb_writel(macb, NCFGR, ncfgr); 579 580 return 1; 581 } 582 583 static int gmac_init_multi_queues(struct macb_device *macb) 584 { 585 int i, num_queues = 1; 586 u32 queue_mask; 587 588 /* bit 0 is never set but queue 0 always exists */ 589 queue_mask = gem_readl(macb, DCFG6) & 0xff; 590 queue_mask |= 0x1; 591 592 for (i = 1; i < MACB_MAX_QUEUES; i++) 593 if (queue_mask & (1 << i)) 594 num_queues++; 595 596 macb->dummy_desc->ctrl = TXBUF_USED; 597 macb->dummy_desc->addr = 0; 598 flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma + 599 MACB_TX_DUMMY_DMA_DESC_SIZE); 600 601 for (i = 1; i < num_queues; i++) 602 gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1); 603 604 return 0; 605 } 606 607 #ifdef CONFIG_DM_ETH 608 static int _macb_init(struct udevice *dev, const char *name) 609 #else 610 static int _macb_init(struct macb_device *macb, const char *name) 611 #endif 612 { 613 #ifdef CONFIG_DM_ETH 614 struct macb_device *macb = dev_get_priv(dev); 615 #endif 616 unsigned long paddr; 617 int i; 618 619 /* 620 * macb_halt should have been called at some point before now, 621 * so we'll assume the controller is idle. 622 */ 623 624 /* initialize DMA descriptors */ 625 paddr = macb->rx_buffer_dma; 626 for (i = 0; i < MACB_RX_RING_SIZE; i++) { 627 if (i == (MACB_RX_RING_SIZE - 1)) 628 paddr |= RXADDR_WRAP; 629 macb->rx_ring[i].addr = paddr; 630 macb->rx_ring[i].ctrl = 0; 631 paddr += 128; 632 } 633 macb_flush_ring_desc(macb, RX); 634 macb_flush_rx_buffer(macb); 635 636 for (i = 0; i < MACB_TX_RING_SIZE; i++) { 637 macb->tx_ring[i].addr = 0; 638 if (i == (MACB_TX_RING_SIZE - 1)) 639 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; 640 else 641 macb->tx_ring[i].ctrl = TXBUF_USED; 642 } 643 macb_flush_ring_desc(macb, TX); 644 645 macb->rx_tail = 0; 646 macb->tx_head = 0; 647 macb->tx_tail = 0; 648 macb->next_rx_tail = 0; 649 650 macb_writel(macb, RBQP, macb->rx_ring_dma); 651 macb_writel(macb, TBQP, macb->tx_ring_dma); 652 653 if (macb_is_gem(macb)) { 654 /* Check the multi queue and initialize the queue for tx */ 655 gmac_init_multi_queues(macb); 656 657 /* 658 * When the GMAC IP with GE feature, this bit is used to 659 * select interface between RGMII and GMII. 660 * When the GMAC IP without GE feature, this bit is used 661 * to select interface between RMII and MII. 662 */ 663 #ifdef CONFIG_DM_ETH 664 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) 665 gem_writel(macb, UR, GEM_BIT(RGMII)); 666 else 667 gem_writel(macb, UR, 0); 668 #else 669 #if defined(CONFIG_RGMII) || defined(CONFIG_RMII) 670 gem_writel(macb, UR, GEM_BIT(RGMII)); 671 #else 672 gem_writel(macb, UR, 0); 673 #endif 674 #endif 675 } else { 676 /* choose RMII or MII mode. This depends on the board */ 677 #ifdef CONFIG_DM_ETH 678 #ifdef CONFIG_AT91FAMILY 679 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) { 680 macb_writel(macb, USRIO, 681 MACB_BIT(RMII) | MACB_BIT(CLKEN)); 682 } else { 683 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 684 } 685 #else 686 if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) 687 macb_writel(macb, USRIO, 0); 688 else 689 macb_writel(macb, USRIO, MACB_BIT(MII)); 690 #endif 691 #else 692 #ifdef CONFIG_RMII 693 #ifdef CONFIG_AT91FAMILY 694 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); 695 #else 696 macb_writel(macb, USRIO, 0); 697 #endif 698 #else 699 #ifdef CONFIG_AT91FAMILY 700 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 701 #else 702 macb_writel(macb, USRIO, MACB_BIT(MII)); 703 #endif 704 #endif /* CONFIG_RMII */ 705 #endif 706 } 707 708 #ifdef CONFIG_DM_ETH 709 if (!macb_phy_init(dev, name)) 710 #else 711 if (!macb_phy_init(macb, name)) 712 #endif 713 return -1; 714 715 /* Enable TX and RX */ 716 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); 717 718 return 0; 719 } 720 721 static void _macb_halt(struct macb_device *macb) 722 { 723 u32 ncr, tsr; 724 725 /* Halt the controller and wait for any ongoing transmission to end. */ 726 ncr = macb_readl(macb, NCR); 727 ncr |= MACB_BIT(THALT); 728 macb_writel(macb, NCR, ncr); 729 730 do { 731 tsr = macb_readl(macb, TSR); 732 } while (tsr & MACB_BIT(TGO)); 733 734 /* Disable TX and RX, and clear statistics */ 735 macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); 736 } 737 738 static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr) 739 { 740 u32 hwaddr_bottom; 741 u16 hwaddr_top; 742 743 /* set hardware address */ 744 hwaddr_bottom = enetaddr[0] | enetaddr[1] << 8 | 745 enetaddr[2] << 16 | enetaddr[3] << 24; 746 macb_writel(macb, SA1B, hwaddr_bottom); 747 hwaddr_top = enetaddr[4] | enetaddr[5] << 8; 748 macb_writel(macb, SA1T, hwaddr_top); 749 return 0; 750 } 751 752 static u32 macb_mdc_clk_div(int id, struct macb_device *macb) 753 { 754 u32 config; 755 unsigned long macb_hz = get_macb_pclk_rate(id); 756 757 if (macb_hz < 20000000) 758 config = MACB_BF(CLK, MACB_CLK_DIV8); 759 else if (macb_hz < 40000000) 760 config = MACB_BF(CLK, MACB_CLK_DIV16); 761 else if (macb_hz < 80000000) 762 config = MACB_BF(CLK, MACB_CLK_DIV32); 763 else 764 config = MACB_BF(CLK, MACB_CLK_DIV64); 765 766 return config; 767 } 768 769 static u32 gem_mdc_clk_div(int id, struct macb_device *macb) 770 { 771 u32 config; 772 unsigned long macb_hz = get_macb_pclk_rate(id); 773 774 if (macb_hz < 20000000) 775 config = GEM_BF(CLK, GEM_CLK_DIV8); 776 else if (macb_hz < 40000000) 777 config = GEM_BF(CLK, GEM_CLK_DIV16); 778 else if (macb_hz < 80000000) 779 config = GEM_BF(CLK, GEM_CLK_DIV32); 780 else if (macb_hz < 120000000) 781 config = GEM_BF(CLK, GEM_CLK_DIV48); 782 else if (macb_hz < 160000000) 783 config = GEM_BF(CLK, GEM_CLK_DIV64); 784 else 785 config = GEM_BF(CLK, GEM_CLK_DIV96); 786 787 return config; 788 } 789 790 /* 791 * Get the DMA bus width field of the network configuration register that we 792 * should program. We find the width from decoding the design configuration 793 * register to find the maximum supported data bus width. 794 */ 795 static u32 macb_dbw(struct macb_device *macb) 796 { 797 switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) { 798 case 4: 799 return GEM_BF(DBW, GEM_DBW128); 800 case 2: 801 return GEM_BF(DBW, GEM_DBW64); 802 case 1: 803 default: 804 return GEM_BF(DBW, GEM_DBW32); 805 } 806 } 807 808 static void _macb_eth_initialize(struct macb_device *macb) 809 { 810 int id = 0; /* This is not used by functions we call */ 811 u32 ncfgr; 812 813 /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */ 814 macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE, 815 &macb->rx_buffer_dma); 816 macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE, 817 &macb->rx_ring_dma); 818 macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE, 819 &macb->tx_ring_dma); 820 macb->dummy_desc = dma_alloc_coherent(MACB_TX_DUMMY_DMA_DESC_SIZE, 821 &macb->dummy_desc_dma); 822 823 /* 824 * Do some basic initialization so that we at least can talk 825 * to the PHY 826 */ 827 if (macb_is_gem(macb)) { 828 ncfgr = gem_mdc_clk_div(id, macb); 829 ncfgr |= macb_dbw(macb); 830 } else { 831 ncfgr = macb_mdc_clk_div(id, macb); 832 } 833 834 macb_writel(macb, NCFGR, ncfgr); 835 } 836 837 #ifndef CONFIG_DM_ETH 838 static int macb_send(struct eth_device *netdev, void *packet, int length) 839 { 840 struct macb_device *macb = to_macb(netdev); 841 842 return _macb_send(macb, netdev->name, packet, length); 843 } 844 845 static int macb_recv(struct eth_device *netdev) 846 { 847 struct macb_device *macb = to_macb(netdev); 848 uchar *packet; 849 int length; 850 851 macb->wrapped = false; 852 for (;;) { 853 macb->next_rx_tail = macb->rx_tail; 854 length = _macb_recv(macb, &packet); 855 if (length >= 0) { 856 net_process_received_packet(packet, length); 857 reclaim_rx_buffers(macb, macb->next_rx_tail); 858 } else if (length < 0) { 859 return length; 860 } 861 } 862 } 863 864 static int macb_init(struct eth_device *netdev, bd_t *bd) 865 { 866 struct macb_device *macb = to_macb(netdev); 867 868 return _macb_init(macb, netdev->name); 869 } 870 871 static void macb_halt(struct eth_device *netdev) 872 { 873 struct macb_device *macb = to_macb(netdev); 874 875 return _macb_halt(macb); 876 } 877 878 static int macb_write_hwaddr(struct eth_device *netdev) 879 { 880 struct macb_device *macb = to_macb(netdev); 881 882 return _macb_write_hwaddr(macb, netdev->enetaddr); 883 } 884 885 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) 886 { 887 struct macb_device *macb; 888 struct eth_device *netdev; 889 890 macb = malloc(sizeof(struct macb_device)); 891 if (!macb) { 892 printf("Error: Failed to allocate memory for MACB%d\n", id); 893 return -1; 894 } 895 memset(macb, 0, sizeof(struct macb_device)); 896 897 netdev = &macb->netdev; 898 899 macb->regs = regs; 900 macb->phy_addr = phy_addr; 901 902 if (macb_is_gem(macb)) 903 sprintf(netdev->name, "gmac%d", id); 904 else 905 sprintf(netdev->name, "macb%d", id); 906 907 netdev->init = macb_init; 908 netdev->halt = macb_halt; 909 netdev->send = macb_send; 910 netdev->recv = macb_recv; 911 netdev->write_hwaddr = macb_write_hwaddr; 912 913 _macb_eth_initialize(macb); 914 915 eth_register(netdev); 916 917 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 918 int retval; 919 struct mii_dev *mdiodev = mdio_alloc(); 920 if (!mdiodev) 921 return -ENOMEM; 922 strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN); 923 mdiodev->read = macb_miiphy_read; 924 mdiodev->write = macb_miiphy_write; 925 926 retval = mdio_register(mdiodev); 927 if (retval < 0) 928 return retval; 929 macb->bus = miiphy_get_dev_by_name(netdev->name); 930 #endif 931 return 0; 932 } 933 #endif /* !CONFIG_DM_ETH */ 934 935 #ifdef CONFIG_DM_ETH 936 937 static int macb_start(struct udevice *dev) 938 { 939 return _macb_init(dev, dev->name); 940 } 941 942 static int macb_send(struct udevice *dev, void *packet, int length) 943 { 944 struct macb_device *macb = dev_get_priv(dev); 945 946 return _macb_send(macb, dev->name, packet, length); 947 } 948 949 static int macb_recv(struct udevice *dev, int flags, uchar **packetp) 950 { 951 struct macb_device *macb = dev_get_priv(dev); 952 953 macb->next_rx_tail = macb->rx_tail; 954 macb->wrapped = false; 955 956 return _macb_recv(macb, packetp); 957 } 958 959 static int macb_free_pkt(struct udevice *dev, uchar *packet, int length) 960 { 961 struct macb_device *macb = dev_get_priv(dev); 962 963 reclaim_rx_buffers(macb, macb->next_rx_tail); 964 965 return 0; 966 } 967 968 static void macb_stop(struct udevice *dev) 969 { 970 struct macb_device *macb = dev_get_priv(dev); 971 972 _macb_halt(macb); 973 } 974 975 static int macb_write_hwaddr(struct udevice *dev) 976 { 977 struct eth_pdata *plat = dev_get_platdata(dev); 978 struct macb_device *macb = dev_get_priv(dev); 979 980 return _macb_write_hwaddr(macb, plat->enetaddr); 981 } 982 983 static const struct eth_ops macb_eth_ops = { 984 .start = macb_start, 985 .send = macb_send, 986 .recv = macb_recv, 987 .stop = macb_stop, 988 .free_pkt = macb_free_pkt, 989 .write_hwaddr = macb_write_hwaddr, 990 }; 991 992 static int macb_eth_probe(struct udevice *dev) 993 { 994 struct eth_pdata *pdata = dev_get_platdata(dev); 995 struct macb_device *macb = dev_get_priv(dev); 996 997 #ifdef CONFIG_DM_ETH 998 const char *phy_mode; 999 1000 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); 1001 if (phy_mode) 1002 macb->phy_interface = phy_get_interface_by_name(phy_mode); 1003 if (macb->phy_interface == -1) { 1004 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); 1005 return -EINVAL; 1006 } 1007 #endif 1008 1009 macb->regs = (void *)pdata->iobase; 1010 1011 _macb_eth_initialize(macb); 1012 #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) 1013 int retval; 1014 struct mii_dev *mdiodev = mdio_alloc(); 1015 if (!mdiodev) 1016 return -ENOMEM; 1017 strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); 1018 mdiodev->read = macb_miiphy_read; 1019 mdiodev->write = macb_miiphy_write; 1020 1021 retval = mdio_register(mdiodev); 1022 if (retval < 0) 1023 return retval; 1024 macb->bus = miiphy_get_dev_by_name(dev->name); 1025 #endif 1026 1027 return 0; 1028 } 1029 1030 static int macb_eth_ofdata_to_platdata(struct udevice *dev) 1031 { 1032 struct eth_pdata *pdata = dev_get_platdata(dev); 1033 1034 pdata->iobase = dev_get_addr(dev); 1035 return 0; 1036 } 1037 1038 static const struct udevice_id macb_eth_ids[] = { 1039 { .compatible = "cdns,macb" }, 1040 { } 1041 }; 1042 1043 U_BOOT_DRIVER(eth_macb) = { 1044 .name = "eth_macb", 1045 .id = UCLASS_ETH, 1046 .of_match = macb_eth_ids, 1047 .ofdata_to_platdata = macb_eth_ofdata_to_platdata, 1048 .probe = macb_eth_probe, 1049 .ops = &macb_eth_ops, 1050 .priv_auto_alloc_size = sizeof(struct macb_device), 1051 .platdata_auto_alloc_size = sizeof(struct eth_pdata), 1052 }; 1053 #endif 1054 1055 #endif 1056