xref: /openbmc/u-boot/drivers/net/macb.c (revision a380279b)
1 /*
2  * Copyright (C) 2005-2006 Atmel Corporation
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program; if not, write to the Free Software
16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
17  */
18 #include <common.h>
19 
20 /*
21  * The u-boot networking stack is a little weird.  It seems like the
22  * networking core allocates receive buffers up front without any
23  * regard to the hardware that's supposed to actually receive those
24  * packets.
25  *
26  * The MACB receives packets into 128-byte receive buffers, so the
27  * buffers allocated by the core isn't very practical to use.  We'll
28  * allocate our own, but we need one such buffer in case a packet
29  * wraps around the DMA ring so that we have to copy it.
30  *
31  * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific
32  * configuration header.  This way, the core allocates one RX buffer
33  * and one TX buffer, each of which can hold a ethernet packet of
34  * maximum size.
35  *
36  * For some reason, the networking core unconditionally specifies a
37  * 32-byte packet "alignment" (which really should be called
38  * "padding").  MACB shouldn't need that, but we'll refrain from any
39  * core modifications here...
40  */
41 
42 #include <net.h>
43 #include <netdev.h>
44 #include <malloc.h>
45 
46 #include <linux/mii.h>
47 #include <asm/io.h>
48 #include <asm/dma-mapping.h>
49 #include <asm/arch/clk.h>
50 
51 #include "macb.h"
52 
53 #define barrier() asm volatile("" ::: "memory")
54 
55 #define CONFIG_SYS_MACB_RX_BUFFER_SIZE		4096
56 #define CONFIG_SYS_MACB_RX_RING_SIZE		(CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
57 #define CONFIG_SYS_MACB_TX_RING_SIZE		16
58 #define CONFIG_SYS_MACB_TX_TIMEOUT		1000
59 #define CONFIG_SYS_MACB_AUTONEG_TIMEOUT	5000000
60 
61 struct macb_dma_desc {
62 	u32	addr;
63 	u32	ctrl;
64 };
65 
66 #define RXADDR_USED		0x00000001
67 #define RXADDR_WRAP		0x00000002
68 
69 #define RXBUF_FRMLEN_MASK	0x00000fff
70 #define RXBUF_FRAME_START	0x00004000
71 #define RXBUF_FRAME_END		0x00008000
72 #define RXBUF_TYPEID_MATCH	0x00400000
73 #define RXBUF_ADDR4_MATCH	0x00800000
74 #define RXBUF_ADDR3_MATCH	0x01000000
75 #define RXBUF_ADDR2_MATCH	0x02000000
76 #define RXBUF_ADDR1_MATCH	0x04000000
77 #define RXBUF_BROADCAST		0x80000000
78 
79 #define TXBUF_FRMLEN_MASK	0x000007ff
80 #define TXBUF_FRAME_END		0x00008000
81 #define TXBUF_NOCRC		0x00010000
82 #define TXBUF_EXHAUSTED		0x08000000
83 #define TXBUF_UNDERRUN		0x10000000
84 #define TXBUF_MAXRETRY		0x20000000
85 #define TXBUF_WRAP		0x40000000
86 #define TXBUF_USED		0x80000000
87 
88 struct macb_device {
89 	void			*regs;
90 
91 	unsigned int		rx_tail;
92 	unsigned int		tx_head;
93 	unsigned int		tx_tail;
94 
95 	void			*rx_buffer;
96 	void			*tx_buffer;
97 	struct macb_dma_desc	*rx_ring;
98 	struct macb_dma_desc	*tx_ring;
99 
100 	unsigned long		rx_buffer_dma;
101 	unsigned long		rx_ring_dma;
102 	unsigned long		tx_ring_dma;
103 
104 	const struct device	*dev;
105 	struct eth_device	netdev;
106 	unsigned short		phy_addr;
107 };
108 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
109 
110 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
111 {
112 	unsigned long netctl;
113 	unsigned long netstat;
114 	unsigned long frame;
115 
116 	netctl = macb_readl(macb, NCR);
117 	netctl |= MACB_BIT(MPE);
118 	macb_writel(macb, NCR, netctl);
119 
120 	frame = (MACB_BF(SOF, 1)
121 		 | MACB_BF(RW, 1)
122 		 | MACB_BF(PHYA, macb->phy_addr)
123 		 | MACB_BF(REGA, reg)
124 		 | MACB_BF(CODE, 2)
125 		 | MACB_BF(DATA, value));
126 	macb_writel(macb, MAN, frame);
127 
128 	do {
129 		netstat = macb_readl(macb, NSR);
130 	} while (!(netstat & MACB_BIT(IDLE)));
131 
132 	netctl = macb_readl(macb, NCR);
133 	netctl &= ~MACB_BIT(MPE);
134 	macb_writel(macb, NCR, netctl);
135 }
136 
137 static u16 macb_mdio_read(struct macb_device *macb, u8 reg)
138 {
139 	unsigned long netctl;
140 	unsigned long netstat;
141 	unsigned long frame;
142 
143 	netctl = macb_readl(macb, NCR);
144 	netctl |= MACB_BIT(MPE);
145 	macb_writel(macb, NCR, netctl);
146 
147 	frame = (MACB_BF(SOF, 1)
148 		 | MACB_BF(RW, 2)
149 		 | MACB_BF(PHYA, macb->phy_addr)
150 		 | MACB_BF(REGA, reg)
151 		 | MACB_BF(CODE, 2));
152 	macb_writel(macb, MAN, frame);
153 
154 	do {
155 		netstat = macb_readl(macb, NSR);
156 	} while (!(netstat & MACB_BIT(IDLE)));
157 
158 	frame = macb_readl(macb, MAN);
159 
160 	netctl = macb_readl(macb, NCR);
161 	netctl &= ~MACB_BIT(MPE);
162 	macb_writel(macb, NCR, netctl);
163 
164 	return MACB_BFEXT(DATA, frame);
165 }
166 
167 #if defined(CONFIG_CMD_NET)
168 
169 static int macb_send(struct eth_device *netdev, volatile void *packet,
170 		     int length)
171 {
172 	struct macb_device *macb = to_macb(netdev);
173 	unsigned long paddr, ctrl;
174 	unsigned int tx_head = macb->tx_head;
175 	int i;
176 
177 	paddr = dma_map_single(packet, length, DMA_TO_DEVICE);
178 
179 	ctrl = length & TXBUF_FRMLEN_MASK;
180 	ctrl |= TXBUF_FRAME_END;
181 	if (tx_head == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) {
182 		ctrl |= TXBUF_WRAP;
183 		macb->tx_head = 0;
184 	} else
185 		macb->tx_head++;
186 
187 	macb->tx_ring[tx_head].ctrl = ctrl;
188 	macb->tx_ring[tx_head].addr = paddr;
189 	barrier();
190 	macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
191 
192 	/*
193 	 * I guess this is necessary because the networking core may
194 	 * re-use the transmit buffer as soon as we return...
195 	 */
196 	for (i = 0; i <= CONFIG_SYS_MACB_TX_TIMEOUT; i++) {
197 		barrier();
198 		ctrl = macb->tx_ring[tx_head].ctrl;
199 		if (ctrl & TXBUF_USED)
200 			break;
201 		udelay(1);
202 	}
203 
204 	dma_unmap_single(packet, length, paddr);
205 
206 	if (i <= CONFIG_SYS_MACB_TX_TIMEOUT) {
207 		if (ctrl & TXBUF_UNDERRUN)
208 			printf("%s: TX underrun\n", netdev->name);
209 		if (ctrl & TXBUF_EXHAUSTED)
210 			printf("%s: TX buffers exhausted in mid frame\n",
211 			       netdev->name);
212 	} else {
213 		printf("%s: TX timeout\n", netdev->name);
214 	}
215 
216 	/* No one cares anyway */
217 	return 0;
218 }
219 
220 static void reclaim_rx_buffers(struct macb_device *macb,
221 			       unsigned int new_tail)
222 {
223 	unsigned int i;
224 
225 	i = macb->rx_tail;
226 	while (i > new_tail) {
227 		macb->rx_ring[i].addr &= ~RXADDR_USED;
228 		i++;
229 		if (i > CONFIG_SYS_MACB_RX_RING_SIZE)
230 			i = 0;
231 	}
232 
233 	while (i < new_tail) {
234 		macb->rx_ring[i].addr &= ~RXADDR_USED;
235 		i++;
236 	}
237 
238 	barrier();
239 	macb->rx_tail = new_tail;
240 }
241 
242 static int macb_recv(struct eth_device *netdev)
243 {
244 	struct macb_device *macb = to_macb(netdev);
245 	unsigned int rx_tail = macb->rx_tail;
246 	void *buffer;
247 	int length;
248 	int wrapped = 0;
249 	u32 status;
250 
251 	for (;;) {
252 		if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
253 			return -1;
254 
255 		status = macb->rx_ring[rx_tail].ctrl;
256 		if (status & RXBUF_FRAME_START) {
257 			if (rx_tail != macb->rx_tail)
258 				reclaim_rx_buffers(macb, rx_tail);
259 			wrapped = 0;
260 		}
261 
262 		if (status & RXBUF_FRAME_END) {
263 			buffer = macb->rx_buffer + 128 * macb->rx_tail;
264 			length = status & RXBUF_FRMLEN_MASK;
265 			if (wrapped) {
266 				unsigned int headlen, taillen;
267 
268 				headlen = 128 * (CONFIG_SYS_MACB_RX_RING_SIZE
269 						 - macb->rx_tail);
270 				taillen = length - headlen;
271 				memcpy((void *)NetRxPackets[0],
272 				       buffer, headlen);
273 				memcpy((void *)NetRxPackets[0] + headlen,
274 				       macb->rx_buffer, taillen);
275 				buffer = (void *)NetRxPackets[0];
276 			}
277 
278 			NetReceive(buffer, length);
279 			if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE)
280 				rx_tail = 0;
281 			reclaim_rx_buffers(macb, rx_tail);
282 		} else {
283 			if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) {
284 				wrapped = 1;
285 				rx_tail = 0;
286 			}
287 		}
288 		barrier();
289 	}
290 
291 	return 0;
292 }
293 
294 static void macb_phy_reset(struct macb_device *macb)
295 {
296 	struct eth_device *netdev = &macb->netdev;
297 	int i;
298 	u16 status, adv;
299 
300 	adv = ADVERTISE_CSMA | ADVERTISE_ALL;
301 	macb_mdio_write(macb, MII_ADVERTISE, adv);
302 	printf("%s: Starting autonegotiation...\n", netdev->name);
303 	macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
304 					 | BMCR_ANRESTART));
305 
306 	for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) {
307 		status = macb_mdio_read(macb, MII_BMSR);
308 		if (status & BMSR_ANEGCOMPLETE)
309 			break;
310 		udelay(100);
311 	}
312 
313 	if (status & BMSR_ANEGCOMPLETE)
314 		printf("%s: Autonegotiation complete\n", netdev->name);
315 	else
316 		printf("%s: Autonegotiation timed out (status=0x%04x)\n",
317 		       netdev->name, status);
318 }
319 
320 #ifdef CONFIG_MACB_SEARCH_PHY
321 static int macb_phy_find(struct macb_device *macb)
322 {
323 	int i;
324 	u16 phy_id;
325 
326 	/* Search for PHY... */
327 	for (i = 0; i < 32; i++) {
328 		macb->phy_addr = i;
329 		phy_id = macb_mdio_read(macb, MII_PHYSID1);
330 		if (phy_id != 0xffff) {
331 			printf("%s: PHY present at %d\n", macb->netdev.name, i);
332 			return 1;
333 		}
334 	}
335 
336 	/* PHY isn't up to snuff */
337 	printf("%s: PHY not found", macb->netdev.name);
338 
339 	return 0;
340 }
341 #endif /* CONFIG_MACB_SEARCH_PHY */
342 
343 
344 static int macb_phy_init(struct macb_device *macb)
345 {
346 	struct eth_device *netdev = &macb->netdev;
347 	u32 ncfgr;
348 	u16 phy_id, status, adv, lpa;
349 	int media, speed, duplex;
350 	int i;
351 
352 #ifdef CONFIG_MACB_SEARCH_PHY
353 	/* Auto-detect phy_addr */
354 	if (!macb_phy_find(macb)) {
355 		return 0;
356 	}
357 #endif /* CONFIG_MACB_SEARCH_PHY */
358 
359 	/* Check if the PHY is up to snuff... */
360 	phy_id = macb_mdio_read(macb, MII_PHYSID1);
361 	if (phy_id == 0xffff) {
362 		printf("%s: No PHY present\n", netdev->name);
363 		return 0;
364 	}
365 
366 	status = macb_mdio_read(macb, MII_BMSR);
367 	if (!(status & BMSR_LSTATUS)) {
368 		/* Try to re-negotiate if we don't have link already. */
369 		macb_phy_reset(macb);
370 
371 		for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) {
372 			status = macb_mdio_read(macb, MII_BMSR);
373 			if (status & BMSR_LSTATUS)
374 				break;
375 			udelay(100);
376 		}
377 	}
378 
379 	if (!(status & BMSR_LSTATUS)) {
380 		printf("%s: link down (status: 0x%04x)\n",
381 		       netdev->name, status);
382 		return 0;
383 	} else {
384 		adv = macb_mdio_read(macb, MII_ADVERTISE);
385 		lpa = macb_mdio_read(macb, MII_LPA);
386 		media = mii_nway_result(lpa & adv);
387 		speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
388 			 ? 1 : 0);
389 		duplex = (media & ADVERTISE_FULL) ? 1 : 0;
390 		printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
391 		       netdev->name,
392 		       speed ? "100" : "10",
393 		       duplex ? "full" : "half",
394 		       lpa);
395 
396 		ncfgr = macb_readl(macb, NCFGR);
397 		ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
398 		if (speed)
399 			ncfgr |= MACB_BIT(SPD);
400 		if (duplex)
401 			ncfgr |= MACB_BIT(FD);
402 		macb_writel(macb, NCFGR, ncfgr);
403 		return 1;
404 	}
405 }
406 
407 static int macb_init(struct eth_device *netdev, bd_t *bd)
408 {
409 	struct macb_device *macb = to_macb(netdev);
410 	unsigned long paddr;
411 	u32 hwaddr_bottom;
412 	u16 hwaddr_top;
413 	int i;
414 
415 	/*
416 	 * macb_halt should have been called at some point before now,
417 	 * so we'll assume the controller is idle.
418 	 */
419 
420 	/* initialize DMA descriptors */
421 	paddr = macb->rx_buffer_dma;
422 	for (i = 0; i < CONFIG_SYS_MACB_RX_RING_SIZE; i++) {
423 		if (i == (CONFIG_SYS_MACB_RX_RING_SIZE - 1))
424 			paddr |= RXADDR_WRAP;
425 		macb->rx_ring[i].addr = paddr;
426 		macb->rx_ring[i].ctrl = 0;
427 		paddr += 128;
428 	}
429 	for (i = 0; i < CONFIG_SYS_MACB_TX_RING_SIZE; i++) {
430 		macb->tx_ring[i].addr = 0;
431 		if (i == (CONFIG_SYS_MACB_TX_RING_SIZE - 1))
432 			macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
433 		else
434 			macb->tx_ring[i].ctrl = TXBUF_USED;
435 	}
436 	macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
437 
438 	macb_writel(macb, RBQP, macb->rx_ring_dma);
439 	macb_writel(macb, TBQP, macb->tx_ring_dma);
440 
441 	/* set hardware address */
442 	hwaddr_bottom = cpu_to_le32(*((u32 *)netdev->enetaddr));
443 	macb_writel(macb, SA1B, hwaddr_bottom);
444 	hwaddr_top = cpu_to_le16(*((u16 *)(netdev->enetaddr + 4)));
445 	macb_writel(macb, SA1T, hwaddr_top);
446 
447 	/* choose RMII or MII mode. This depends on the board */
448 #ifdef CONFIG_RMII
449 #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
450     defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
451 	defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
452 	macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
453 #else
454 	macb_writel(macb, USRIO, 0);
455 #endif
456 #else
457 #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
458     defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
459 	defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
460 	macb_writel(macb, USRIO, MACB_BIT(CLKEN));
461 #else
462 	macb_writel(macb, USRIO, MACB_BIT(MII));
463 #endif
464 #endif /* CONFIG_RMII */
465 
466 	if (!macb_phy_init(macb))
467 		return -1;
468 
469 	/* Enable TX and RX */
470 	macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE));
471 
472 	return 0;
473 }
474 
475 static void macb_halt(struct eth_device *netdev)
476 {
477 	struct macb_device *macb = to_macb(netdev);
478 	u32 ncr, tsr;
479 
480 	/* Halt the controller and wait for any ongoing transmission to end. */
481 	ncr = macb_readl(macb, NCR);
482 	ncr |= MACB_BIT(THALT);
483 	macb_writel(macb, NCR, ncr);
484 
485 	do {
486 		tsr = macb_readl(macb, TSR);
487 	} while (tsr & MACB_BIT(TGO));
488 
489 	/* Disable TX and RX, and clear statistics */
490 	macb_writel(macb, NCR, MACB_BIT(CLRSTAT));
491 }
492 
493 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
494 {
495 	struct macb_device *macb;
496 	struct eth_device *netdev;
497 	unsigned long macb_hz;
498 	u32 ncfgr;
499 
500 	macb = malloc(sizeof(struct macb_device));
501 	if (!macb) {
502 		printf("Error: Failed to allocate memory for MACB%d\n", id);
503 		return -1;
504 	}
505 	memset(macb, 0, sizeof(struct macb_device));
506 
507 	netdev = &macb->netdev;
508 
509 	macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE,
510 					     &macb->rx_buffer_dma);
511 	macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE
512 					   * sizeof(struct macb_dma_desc),
513 					   &macb->rx_ring_dma);
514 	macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE
515 					   * sizeof(struct macb_dma_desc),
516 					   &macb->tx_ring_dma);
517 
518 	macb->regs = regs;
519 	macb->phy_addr = phy_addr;
520 
521 	sprintf(netdev->name, "macb%d", id);
522 	netdev->init = macb_init;
523 	netdev->halt = macb_halt;
524 	netdev->send = macb_send;
525 	netdev->recv = macb_recv;
526 
527 	/*
528 	 * Do some basic initialization so that we at least can talk
529 	 * to the PHY
530 	 */
531 	macb_hz = get_macb_pclk_rate(id);
532 	if (macb_hz < 20000000)
533 		ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
534 	else if (macb_hz < 40000000)
535 		ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
536 	else if (macb_hz < 80000000)
537 		ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
538 	else
539 		ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
540 
541 	macb_writel(macb, NCFGR, ncfgr);
542 
543 	eth_register(netdev);
544 
545 	return 0;
546 }
547 
548 #endif
549 
550 #if defined(CONFIG_CMD_MII)
551 
552 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
553 {
554 	unsigned long netctl;
555 	unsigned long netstat;
556 	unsigned long frame;
557 	int iflag;
558 
559 	iflag = disable_interrupts();
560 	netctl = macb_readl(&macb, EMACB_NCR);
561 	netctl |= MACB_BIT(MPE);
562 	macb_writel(&macb, EMACB_NCR, netctl);
563 	if (iflag)
564 		enable_interrupts();
565 
566 	frame = (MACB_BF(SOF, 1)
567 		 | MACB_BF(RW, 2)
568 		 | MACB_BF(PHYA, addr)
569 		 | MACB_BF(REGA, reg)
570 		 | MACB_BF(CODE, 2));
571 	macb_writel(&macb, EMACB_MAN, frame);
572 
573 	do {
574 		netstat = macb_readl(&macb, EMACB_NSR);
575 	} while (!(netstat & MACB_BIT(IDLE)));
576 
577 	frame = macb_readl(&macb, EMACB_MAN);
578 	*value = MACB_BFEXT(DATA, frame);
579 
580 	iflag = disable_interrupts();
581 	netctl = macb_readl(&macb, EMACB_NCR);
582 	netctl &= ~MACB_BIT(MPE);
583 	macb_writel(&macb, EMACB_NCR, netctl);
584 	if (iflag)
585 		enable_interrupts();
586 
587 	return 0;
588 }
589 
590 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
591 {
592 	unsigned long netctl;
593 	unsigned long netstat;
594 	unsigned long frame;
595 	int iflag;
596 
597 	iflag = disable_interrupts();
598 	netctl = macb_readl(&macb, EMACB_NCR);
599 	netctl |= MACB_BIT(MPE);
600 	macb_writel(&macb, EMACB_NCR, netctl);
601 	if (iflag)
602 		enable_interrupts();
603 
604 	frame = (MACB_BF(SOF, 1)
605 		 | MACB_BF(RW, 1)
606 		 | MACB_BF(PHYA, addr)
607 		 | MACB_BF(REGA, reg)
608 		 | MACB_BF(CODE, 2)
609 		 | MACB_BF(DATA, value));
610 	macb_writel(&macb, EMACB_MAN, frame);
611 
612 	do {
613 		netstat = macb_readl(&macb, EMACB_NSR);
614 	} while (!(netstat & MACB_BIT(IDLE)));
615 
616 	iflag = disable_interrupts();
617 	netctl = macb_readl(&macb, EMACB_NCR);
618 	netctl &= ~MACB_BIT(MPE);
619 	macb_writel(&macb, EMACB_NCR, netctl);
620 	if (iflag)
621 		enable_interrupts();
622 
623 	return 0;
624 }
625 
626 #endif
627