1 /* 2 * Copyright (C) 2005-2006 Atmel Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 */ 18 #include <common.h> 19 20 /* 21 * The u-boot networking stack is a little weird. It seems like the 22 * networking core allocates receive buffers up front without any 23 * regard to the hardware that's supposed to actually receive those 24 * packets. 25 * 26 * The MACB receives packets into 128-byte receive buffers, so the 27 * buffers allocated by the core isn't very practical to use. We'll 28 * allocate our own, but we need one such buffer in case a packet 29 * wraps around the DMA ring so that we have to copy it. 30 * 31 * Therefore, define CONFIG_SYS_RX_ETH_BUFFER to 1 in the board-specific 32 * configuration header. This way, the core allocates one RX buffer 33 * and one TX buffer, each of which can hold a ethernet packet of 34 * maximum size. 35 * 36 * For some reason, the networking core unconditionally specifies a 37 * 32-byte packet "alignment" (which really should be called 38 * "padding"). MACB shouldn't need that, but we'll refrain from any 39 * core modifications here... 40 */ 41 42 #include <net.h> 43 #include <netdev.h> 44 #include <malloc.h> 45 #include <miiphy.h> 46 47 #include <linux/mii.h> 48 #include <asm/io.h> 49 #include <asm/dma-mapping.h> 50 #include <asm/arch/clk.h> 51 52 #include "macb.h" 53 54 #define barrier() asm volatile("" ::: "memory") 55 56 #define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096 57 #define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128) 58 #define CONFIG_SYS_MACB_TX_RING_SIZE 16 59 #define CONFIG_SYS_MACB_TX_TIMEOUT 1000 60 #define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000 61 62 struct macb_dma_desc { 63 u32 addr; 64 u32 ctrl; 65 }; 66 67 #define RXADDR_USED 0x00000001 68 #define RXADDR_WRAP 0x00000002 69 70 #define RXBUF_FRMLEN_MASK 0x00000fff 71 #define RXBUF_FRAME_START 0x00004000 72 #define RXBUF_FRAME_END 0x00008000 73 #define RXBUF_TYPEID_MATCH 0x00400000 74 #define RXBUF_ADDR4_MATCH 0x00800000 75 #define RXBUF_ADDR3_MATCH 0x01000000 76 #define RXBUF_ADDR2_MATCH 0x02000000 77 #define RXBUF_ADDR1_MATCH 0x04000000 78 #define RXBUF_BROADCAST 0x80000000 79 80 #define TXBUF_FRMLEN_MASK 0x000007ff 81 #define TXBUF_FRAME_END 0x00008000 82 #define TXBUF_NOCRC 0x00010000 83 #define TXBUF_EXHAUSTED 0x08000000 84 #define TXBUF_UNDERRUN 0x10000000 85 #define TXBUF_MAXRETRY 0x20000000 86 #define TXBUF_WRAP 0x40000000 87 #define TXBUF_USED 0x80000000 88 89 struct macb_device { 90 void *regs; 91 92 unsigned int rx_tail; 93 unsigned int tx_head; 94 unsigned int tx_tail; 95 96 void *rx_buffer; 97 void *tx_buffer; 98 struct macb_dma_desc *rx_ring; 99 struct macb_dma_desc *tx_ring; 100 101 unsigned long rx_buffer_dma; 102 unsigned long rx_ring_dma; 103 unsigned long tx_ring_dma; 104 105 const struct device *dev; 106 struct eth_device netdev; 107 unsigned short phy_addr; 108 }; 109 #define to_macb(_nd) container_of(_nd, struct macb_device, netdev) 110 111 static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value) 112 { 113 unsigned long netctl; 114 unsigned long netstat; 115 unsigned long frame; 116 117 netctl = macb_readl(macb, NCR); 118 netctl |= MACB_BIT(MPE); 119 macb_writel(macb, NCR, netctl); 120 121 frame = (MACB_BF(SOF, 1) 122 | MACB_BF(RW, 1) 123 | MACB_BF(PHYA, macb->phy_addr) 124 | MACB_BF(REGA, reg) 125 | MACB_BF(CODE, 2) 126 | MACB_BF(DATA, value)); 127 macb_writel(macb, MAN, frame); 128 129 do { 130 netstat = macb_readl(macb, NSR); 131 } while (!(netstat & MACB_BIT(IDLE))); 132 133 netctl = macb_readl(macb, NCR); 134 netctl &= ~MACB_BIT(MPE); 135 macb_writel(macb, NCR, netctl); 136 } 137 138 static u16 macb_mdio_read(struct macb_device *macb, u8 reg) 139 { 140 unsigned long netctl; 141 unsigned long netstat; 142 unsigned long frame; 143 144 netctl = macb_readl(macb, NCR); 145 netctl |= MACB_BIT(MPE); 146 macb_writel(macb, NCR, netctl); 147 148 frame = (MACB_BF(SOF, 1) 149 | MACB_BF(RW, 2) 150 | MACB_BF(PHYA, macb->phy_addr) 151 | MACB_BF(REGA, reg) 152 | MACB_BF(CODE, 2)); 153 macb_writel(macb, MAN, frame); 154 155 do { 156 netstat = macb_readl(macb, NSR); 157 } while (!(netstat & MACB_BIT(IDLE))); 158 159 frame = macb_readl(macb, MAN); 160 161 netctl = macb_readl(macb, NCR); 162 netctl &= ~MACB_BIT(MPE); 163 macb_writel(macb, NCR, netctl); 164 165 return MACB_BFEXT(DATA, frame); 166 } 167 168 #if defined(CONFIG_CMD_MII) 169 170 int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) 171 { 172 struct eth_device *dev = eth_get_dev_by_name(devname); 173 struct macb_device *macb = to_macb(dev); 174 175 if ( macb->phy_addr != phy_adr ) 176 return -1; 177 178 *value = macb_mdio_read(macb, reg); 179 180 return 0; 181 } 182 183 int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) 184 { 185 struct eth_device *dev = eth_get_dev_by_name(devname); 186 struct macb_device *macb = to_macb(dev); 187 188 if ( macb->phy_addr != phy_adr ) 189 return -1; 190 191 macb_mdio_write(macb, reg, value); 192 193 return 0; 194 } 195 #endif 196 197 198 #if defined(CONFIG_CMD_NET) 199 200 static int macb_send(struct eth_device *netdev, void *packet, int length) 201 { 202 struct macb_device *macb = to_macb(netdev); 203 unsigned long paddr, ctrl; 204 unsigned int tx_head = macb->tx_head; 205 int i; 206 207 paddr = dma_map_single(packet, length, DMA_TO_DEVICE); 208 209 ctrl = length & TXBUF_FRMLEN_MASK; 210 ctrl |= TXBUF_FRAME_END; 211 if (tx_head == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) { 212 ctrl |= TXBUF_WRAP; 213 macb->tx_head = 0; 214 } else 215 macb->tx_head++; 216 217 macb->tx_ring[tx_head].ctrl = ctrl; 218 macb->tx_ring[tx_head].addr = paddr; 219 barrier(); 220 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART)); 221 222 /* 223 * I guess this is necessary because the networking core may 224 * re-use the transmit buffer as soon as we return... 225 */ 226 for (i = 0; i <= CONFIG_SYS_MACB_TX_TIMEOUT; i++) { 227 barrier(); 228 ctrl = macb->tx_ring[tx_head].ctrl; 229 if (ctrl & TXBUF_USED) 230 break; 231 udelay(1); 232 } 233 234 dma_unmap_single(packet, length, paddr); 235 236 if (i <= CONFIG_SYS_MACB_TX_TIMEOUT) { 237 if (ctrl & TXBUF_UNDERRUN) 238 printf("%s: TX underrun\n", netdev->name); 239 if (ctrl & TXBUF_EXHAUSTED) 240 printf("%s: TX buffers exhausted in mid frame\n", 241 netdev->name); 242 } else { 243 printf("%s: TX timeout\n", netdev->name); 244 } 245 246 /* No one cares anyway */ 247 return 0; 248 } 249 250 static void reclaim_rx_buffers(struct macb_device *macb, 251 unsigned int new_tail) 252 { 253 unsigned int i; 254 255 i = macb->rx_tail; 256 while (i > new_tail) { 257 macb->rx_ring[i].addr &= ~RXADDR_USED; 258 i++; 259 if (i > CONFIG_SYS_MACB_RX_RING_SIZE) 260 i = 0; 261 } 262 263 while (i < new_tail) { 264 macb->rx_ring[i].addr &= ~RXADDR_USED; 265 i++; 266 } 267 268 barrier(); 269 macb->rx_tail = new_tail; 270 } 271 272 static int macb_recv(struct eth_device *netdev) 273 { 274 struct macb_device *macb = to_macb(netdev); 275 unsigned int rx_tail = macb->rx_tail; 276 void *buffer; 277 int length; 278 int wrapped = 0; 279 u32 status; 280 281 for (;;) { 282 if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) 283 return -1; 284 285 status = macb->rx_ring[rx_tail].ctrl; 286 if (status & RXBUF_FRAME_START) { 287 if (rx_tail != macb->rx_tail) 288 reclaim_rx_buffers(macb, rx_tail); 289 wrapped = 0; 290 } 291 292 if (status & RXBUF_FRAME_END) { 293 buffer = macb->rx_buffer + 128 * macb->rx_tail; 294 length = status & RXBUF_FRMLEN_MASK; 295 if (wrapped) { 296 unsigned int headlen, taillen; 297 298 headlen = 128 * (CONFIG_SYS_MACB_RX_RING_SIZE 299 - macb->rx_tail); 300 taillen = length - headlen; 301 memcpy((void *)NetRxPackets[0], 302 buffer, headlen); 303 memcpy((void *)NetRxPackets[0] + headlen, 304 macb->rx_buffer, taillen); 305 buffer = (void *)NetRxPackets[0]; 306 } 307 308 NetReceive(buffer, length); 309 if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) 310 rx_tail = 0; 311 reclaim_rx_buffers(macb, rx_tail); 312 } else { 313 if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) { 314 wrapped = 1; 315 rx_tail = 0; 316 } 317 } 318 barrier(); 319 } 320 321 return 0; 322 } 323 324 static void macb_phy_reset(struct macb_device *macb) 325 { 326 struct eth_device *netdev = &macb->netdev; 327 int i; 328 u16 status, adv; 329 330 adv = ADVERTISE_CSMA | ADVERTISE_ALL; 331 macb_mdio_write(macb, MII_ADVERTISE, adv); 332 printf("%s: Starting autonegotiation...\n", netdev->name); 333 macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE 334 | BMCR_ANRESTART)); 335 336 for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) { 337 status = macb_mdio_read(macb, MII_BMSR); 338 if (status & BMSR_ANEGCOMPLETE) 339 break; 340 udelay(100); 341 } 342 343 if (status & BMSR_ANEGCOMPLETE) 344 printf("%s: Autonegotiation complete\n", netdev->name); 345 else 346 printf("%s: Autonegotiation timed out (status=0x%04x)\n", 347 netdev->name, status); 348 } 349 350 #ifdef CONFIG_MACB_SEARCH_PHY 351 static int macb_phy_find(struct macb_device *macb) 352 { 353 int i; 354 u16 phy_id; 355 356 /* Search for PHY... */ 357 for (i = 0; i < 32; i++) { 358 macb->phy_addr = i; 359 phy_id = macb_mdio_read(macb, MII_PHYSID1); 360 if (phy_id != 0xffff) { 361 printf("%s: PHY present at %d\n", macb->netdev.name, i); 362 return 1; 363 } 364 } 365 366 /* PHY isn't up to snuff */ 367 printf("%s: PHY not found\n", macb->netdev.name); 368 369 return 0; 370 } 371 #endif /* CONFIG_MACB_SEARCH_PHY */ 372 373 374 static int macb_phy_init(struct macb_device *macb) 375 { 376 struct eth_device *netdev = &macb->netdev; 377 u32 ncfgr; 378 u16 phy_id, status, adv, lpa; 379 int media, speed, duplex; 380 int i; 381 382 #ifdef CONFIG_MACB_SEARCH_PHY 383 /* Auto-detect phy_addr */ 384 if (!macb_phy_find(macb)) { 385 return 0; 386 } 387 #endif /* CONFIG_MACB_SEARCH_PHY */ 388 389 /* Check if the PHY is up to snuff... */ 390 phy_id = macb_mdio_read(macb, MII_PHYSID1); 391 if (phy_id == 0xffff) { 392 printf("%s: No PHY present\n", netdev->name); 393 return 0; 394 } 395 396 status = macb_mdio_read(macb, MII_BMSR); 397 if (!(status & BMSR_LSTATUS)) { 398 /* Try to re-negotiate if we don't have link already. */ 399 macb_phy_reset(macb); 400 401 for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) { 402 status = macb_mdio_read(macb, MII_BMSR); 403 if (status & BMSR_LSTATUS) 404 break; 405 udelay(100); 406 } 407 } 408 409 if (!(status & BMSR_LSTATUS)) { 410 printf("%s: link down (status: 0x%04x)\n", 411 netdev->name, status); 412 return 0; 413 } else { 414 adv = macb_mdio_read(macb, MII_ADVERTISE); 415 lpa = macb_mdio_read(macb, MII_LPA); 416 media = mii_nway_result(lpa & adv); 417 speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) 418 ? 1 : 0); 419 duplex = (media & ADVERTISE_FULL) ? 1 : 0; 420 printf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", 421 netdev->name, 422 speed ? "100" : "10", 423 duplex ? "full" : "half", 424 lpa); 425 426 ncfgr = macb_readl(macb, NCFGR); 427 ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); 428 if (speed) 429 ncfgr |= MACB_BIT(SPD); 430 if (duplex) 431 ncfgr |= MACB_BIT(FD); 432 macb_writel(macb, NCFGR, ncfgr); 433 return 1; 434 } 435 } 436 437 static int macb_init(struct eth_device *netdev, bd_t *bd) 438 { 439 struct macb_device *macb = to_macb(netdev); 440 unsigned long paddr; 441 int i; 442 443 /* 444 * macb_halt should have been called at some point before now, 445 * so we'll assume the controller is idle. 446 */ 447 448 /* initialize DMA descriptors */ 449 paddr = macb->rx_buffer_dma; 450 for (i = 0; i < CONFIG_SYS_MACB_RX_RING_SIZE; i++) { 451 if (i == (CONFIG_SYS_MACB_RX_RING_SIZE - 1)) 452 paddr |= RXADDR_WRAP; 453 macb->rx_ring[i].addr = paddr; 454 macb->rx_ring[i].ctrl = 0; 455 paddr += 128; 456 } 457 for (i = 0; i < CONFIG_SYS_MACB_TX_RING_SIZE; i++) { 458 macb->tx_ring[i].addr = 0; 459 if (i == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) 460 macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; 461 else 462 macb->tx_ring[i].ctrl = TXBUF_USED; 463 } 464 macb->rx_tail = macb->tx_head = macb->tx_tail = 0; 465 466 macb_writel(macb, RBQP, macb->rx_ring_dma); 467 macb_writel(macb, TBQP, macb->tx_ring_dma); 468 469 /* choose RMII or MII mode. This depends on the board */ 470 #ifdef CONFIG_RMII 471 #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ 472 defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ 473 defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ 474 defined(CONFIG_AT91SAM9XE) || defined(CONFIG_AT91SAM9X5) 475 macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); 476 #else 477 macb_writel(macb, USRIO, 0); 478 #endif 479 #else 480 #if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ 481 defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ 482 defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ 483 defined(CONFIG_AT91SAM9XE) || defined(CONFIG_AT91SAM9X5) 484 macb_writel(macb, USRIO, MACB_BIT(CLKEN)); 485 #else 486 macb_writel(macb, USRIO, MACB_BIT(MII)); 487 #endif 488 #endif /* CONFIG_RMII */ 489 490 if (!macb_phy_init(macb)) 491 return -1; 492 493 /* Enable TX and RX */ 494 macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE)); 495 496 return 0; 497 } 498 499 static void macb_halt(struct eth_device *netdev) 500 { 501 struct macb_device *macb = to_macb(netdev); 502 u32 ncr, tsr; 503 504 /* Halt the controller and wait for any ongoing transmission to end. */ 505 ncr = macb_readl(macb, NCR); 506 ncr |= MACB_BIT(THALT); 507 macb_writel(macb, NCR, ncr); 508 509 do { 510 tsr = macb_readl(macb, TSR); 511 } while (tsr & MACB_BIT(TGO)); 512 513 /* Disable TX and RX, and clear statistics */ 514 macb_writel(macb, NCR, MACB_BIT(CLRSTAT)); 515 } 516 517 static int macb_write_hwaddr(struct eth_device *dev) 518 { 519 struct macb_device *macb = to_macb(dev); 520 u32 hwaddr_bottom; 521 u16 hwaddr_top; 522 523 /* set hardware address */ 524 hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 | 525 dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24; 526 macb_writel(macb, SA1B, hwaddr_bottom); 527 hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8; 528 macb_writel(macb, SA1T, hwaddr_top); 529 return 0; 530 } 531 532 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) 533 { 534 struct macb_device *macb; 535 struct eth_device *netdev; 536 unsigned long macb_hz; 537 u32 ncfgr; 538 539 macb = malloc(sizeof(struct macb_device)); 540 if (!macb) { 541 printf("Error: Failed to allocate memory for MACB%d\n", id); 542 return -1; 543 } 544 memset(macb, 0, sizeof(struct macb_device)); 545 546 netdev = &macb->netdev; 547 548 macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE, 549 &macb->rx_buffer_dma); 550 macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE 551 * sizeof(struct macb_dma_desc), 552 &macb->rx_ring_dma); 553 macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE 554 * sizeof(struct macb_dma_desc), 555 &macb->tx_ring_dma); 556 557 macb->regs = regs; 558 macb->phy_addr = phy_addr; 559 560 sprintf(netdev->name, "macb%d", id); 561 netdev->init = macb_init; 562 netdev->halt = macb_halt; 563 netdev->send = macb_send; 564 netdev->recv = macb_recv; 565 netdev->write_hwaddr = macb_write_hwaddr; 566 567 /* 568 * Do some basic initialization so that we at least can talk 569 * to the PHY 570 */ 571 macb_hz = get_macb_pclk_rate(id); 572 if (macb_hz < 20000000) 573 ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); 574 else if (macb_hz < 40000000) 575 ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); 576 else if (macb_hz < 80000000) 577 ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); 578 else 579 ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); 580 581 macb_writel(macb, NCFGR, ncfgr); 582 583 eth_register(netdev); 584 585 #if defined(CONFIG_CMD_MII) 586 miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write); 587 #endif 588 return 0; 589 } 590 591 #endif 592